Author: uweigand
Date: Wed Jul 5 06:19:47 2017
New Revision: 307156
URL: http://llvm.org/viewvc/llvm-project?rev=307156&view=rev
Log:
[SystemZ] Simplify handling of ISA revisions
This moves determination of the ISA revision from the CPU name to
one single place, removing a bunch of duplicated code. It also
makes the supported ISA revisions available as feature strings.
No functional change.
Modified:
cfe/trunk/lib/Basic/Targets.cpp
Modified: cfe/trunk/lib/Basic/Targets.cpp
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Basic/Targets.cpp?rev=307156&r1=307155&r2=307156&view=diff
==============================================================================
--- cfe/trunk/lib/Basic/Targets.cpp (original)
+++ cfe/trunk/lib/Basic/Targets.cpp Wed Jul 5 06:19:47 2017
@@ -7424,13 +7424,14 @@ class SystemZTargetInfo : public TargetI
static const Builtin::Info BuiltinInfo[];
static const char *const GCCRegNames[];
std::string CPU;
+ int ISARevision;
bool HasTransactionalExecution;
bool HasVector;
public:
SystemZTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
- : TargetInfo(Triple), CPU("z10"), HasTransactionalExecution(false),
- HasVector(false) {
+ : TargetInfo(Triple), CPU("z10"), ISARevision(8),
+ HasTransactionalExecution(false), HasVector(false) {
IntMaxType = SignedLong;
Int64Type = SignedLong;
TLSSupported = true;
@@ -7452,14 +7453,7 @@ public:
Builder.defineMacro("__zarch__");
Builder.defineMacro("__LONG_DOUBLE_128__");
- const std::string ISARev = llvm::StringSwitch<std::string>(CPU)
- .Cases("arch8", "z10", "8")
- .Cases("arch9", "z196", "9")
- .Cases("arch10", "zEC12", "10")
- .Cases("arch11", "z13", "11")
- .Default("");
- if (!ISARev.empty())
- Builder.defineMacro("__ARCH__", ISARev);
+ Builder.defineMacro("__ARCH__", Twine(ISARevision));
Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
@@ -7492,37 +7486,35 @@ public:
BuiltinVaListKind getBuiltinVaListKind() const override {
return TargetInfo::SystemZBuiltinVaList;
}
+ int getISARevision(const StringRef &Name) const {
+ return llvm::StringSwitch<int>(Name)
+ .Cases("arch8", "z10", 8)
+ .Cases("arch9", "z196", 9)
+ .Cases("arch10", "zEC12", 10)
+ .Cases("arch11", "z13", 11)
+ .Default(-1);
+ }
bool setCPU(const std::string &Name) override {
CPU = Name;
- bool CPUKnown = llvm::StringSwitch<bool>(Name)
- .Case("z10", true)
- .Case("arch8", true)
- .Case("z196", true)
- .Case("arch9", true)
- .Case("zEC12", true)
- .Case("arch10", true)
- .Case("z13", true)
- .Case("arch11", true)
- .Default(false);
-
- return CPUKnown;
+ ISARevision = getISARevision(CPU);
+ return ISARevision != -1;
}
bool
initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags,
StringRef CPU,
const std::vector<std::string> &FeaturesVec) const override {
- if (CPU == "zEC12" || CPU == "arch10")
- Features["transactional-execution"] = true;
- if (CPU == "z13" || CPU == "arch11") {
+ int ISARevision = getISARevision(CPU);
+ if (ISARevision >= 10)
Features["transactional-execution"] = true;
+ if (ISARevision >= 11)
Features["vector"] = true;
- }
return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec);
}
bool handleTargetFeatures(std::vector<std::string> &Features,
DiagnosticsEngine &Diags) override {
HasTransactionalExecution = false;
+ HasVector = false;
for (const auto &Feature : Features) {
if (Feature == "+transactional-execution")
HasTransactionalExecution = true;
@@ -7541,6 +7533,10 @@ public:
bool hasFeature(StringRef Feature) const override {
return llvm::StringSwitch<bool>(Feature)
.Case("systemz", true)
+ .Case("arch8", ISARevision >= 8)
+ .Case("arch9", ISARevision >= 9)
+ .Case("arch10", ISARevision >= 10)
+ .Case("arch11", ISARevision >= 11)
.Case("htm", HasTransactionalExecution)
.Case("vx", HasVector)
.Default(false);
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