https://github.com/ukalappa-mips updated https://github.com/llvm/llvm-project/pull/159246
>From 6e82f232ece789939c4886754345a9eb3469cac6 Mon Sep 17 00:00:00 2001 From: Umesh Kalappa <ukalappa.m...@gmail.com> Date: Wed, 17 Sep 2025 05:48:57 +0000 Subject: [PATCH 1/3] RISCV: the builtins support for MIPS RV64 P8700 execution control instructions --- clang/include/clang/Basic/BuiltinsRISCV.td | 5 +++ .../include/clang/Basic/BuiltinsRISCVXMIPS.td | 27 ++++++++++++++ clang/test/CodeGen/builtins-riscv-mips.c | 35 +++++++++++++++++++ llvm/include/llvm/IR/IntrinsicsRISCV.td | 1 + llvm/include/llvm/IR/IntrinsicsRISCVXMIPS.td | 20 +++++++++++ llvm/lib/Target/RISCV/RISCVFeatures.td | 2 +- llvm/lib/Target/RISCV/RISCVInstrInfoXMips.td | 7 ++++ llvm/test/CodeGen/RISCV/xmips-exectl.ll | 35 +++++++++++++++++++ 8 files changed, 131 insertions(+), 1 deletion(-) create mode 100644 clang/include/clang/Basic/BuiltinsRISCVXMIPS.td create mode 100644 clang/test/CodeGen/builtins-riscv-mips.c create mode 100644 llvm/include/llvm/IR/IntrinsicsRISCVXMIPS.td create mode 100644 llvm/test/CodeGen/RISCV/xmips-exectl.ll diff --git a/clang/include/clang/Basic/BuiltinsRISCV.td b/clang/include/clang/Basic/BuiltinsRISCV.td index 5927eaf80d57a..2dad5ede2d64b 100644 --- a/clang/include/clang/Basic/BuiltinsRISCV.td +++ b/clang/include/clang/Basic/BuiltinsRISCV.td @@ -162,3 +162,8 @@ include "clang/Basic/BuiltinsRISCVXCV.td" // XAndes extensions. //===----------------------------------------------------------------------===// include "clang/Basic/BuiltinsRISCVXAndes.td" + +//===----------------------------------------------------------------------===// +// MIPS extensions. +//===----------------------------------------------------------------------===// +include "clang/Basic/BuiltinsRISCVXMIPS.td" diff --git a/clang/include/clang/Basic/BuiltinsRISCVXMIPS.td b/clang/include/clang/Basic/BuiltinsRISCVXMIPS.td new file mode 100644 index 0000000000000..28cf6c9bb1707 --- /dev/null +++ b/clang/include/clang/Basic/BuiltinsRISCVXMIPS.td @@ -0,0 +1,27 @@ +//==- BuiltinsRISCVXMIPS.td - RISC-V MIPS Builtin database ----*- C++ -*-==// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// This file defines the MIPS-specific builtin function database. Users of +// this file must define the BUILTIN macro to make use of this information. +// +//===----------------------------------------------------------------------===// + +class RISCVXMIPSBuiltin<string prototype, string features = ""> : TargetBuiltin { + let Spellings = ["__builtin_riscv_" # NAME]; + let Prototype = prototype; + let Features = features; +} + +//===----------------------------------------------------------------------===// +// MIPS execution control extensions . +//===----------------------------------------------------------------------===// +let Attributes = [NoThrow, Const] in { +def mips_pause : RISCVXMIPSBuiltin<"void()", "xmipsexectl">; +def mips_ehb : RISCVXMIPSBuiltin<"void()", "xmipsexectl">; +def mips_ihb : RISCVXMIPSBuiltin<"void()", "xmipsexectl">; +} \ No newline at end of file diff --git a/clang/test/CodeGen/builtins-riscv-mips.c b/clang/test/CodeGen/builtins-riscv-mips.c new file mode 100644 index 0000000000000..3c6c9b994f5d2 --- /dev/null +++ b/clang/test/CodeGen/builtins-riscv-mips.c @@ -0,0 +1,35 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 6 +// RUN: %clang_cc1 -triple riscv32-linux-elf -O3 -target-feature +xmipsexectl -emit-llvm -o - %s | FileCheck %s RISCV32 + +// CHECK-LABEL: define dso_local void @test_mips_pause( +// CHECK-SAME: ) local_unnamed_addr #[[ATTR0:[0-9]+]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: tail call void @llvm.riscv.mips.pause() +// CHECK-NEXT: ret void +// +void test_mips_pause() +{ + __builtin_riscv_mips_pause(); +} + +// CHECK-LABEL: define dso_local void @test_mips_ehb( +// CHECK-SAME: ) local_unnamed_addr #[[ATTR0]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: tail call void @llvm.riscv.mips.ehb() +// CHECK-NEXT: ret void +// +void test_mips_ehb() +{ + __builtin_riscv_mips_ehb(); +} + +// CHECK-LABEL: define dso_local void @test_mips_ihb( +// CHECK-SAME: ) local_unnamed_addr #[[ATTR0]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: tail call void @llvm.riscv.mips.ihb() +// CHECK-NEXT: ret void +// +void test_mips_ihb() +{ + __builtin_riscv_mips_ihb(); +} diff --git a/llvm/include/llvm/IR/IntrinsicsRISCV.td b/llvm/include/llvm/IR/IntrinsicsRISCV.td index 878f7b3194830..bd2c95c5af587 100644 --- a/llvm/include/llvm/IR/IntrinsicsRISCV.td +++ b/llvm/include/llvm/IR/IntrinsicsRISCV.td @@ -1949,3 +1949,4 @@ include "llvm/IR/IntrinsicsRISCVXTHead.td" include "llvm/IR/IntrinsicsRISCVXsf.td" include "llvm/IR/IntrinsicsRISCVXCV.td" include "llvm/IR/IntrinsicsRISCVXAndes.td" +include "llvm/IR/IntrinsicsRISCVXMIPS.td" diff --git a/llvm/include/llvm/IR/IntrinsicsRISCVXMIPS.td b/llvm/include/llvm/IR/IntrinsicsRISCVXMIPS.td new file mode 100644 index 0000000000000..ced96ac2e10a7 --- /dev/null +++ b/llvm/include/llvm/IR/IntrinsicsRISCVXMIPS.td @@ -0,0 +1,20 @@ +//===- IntrinsicsRISCVXMIPS.td - Defines MIPS intrinsics -------*- tablegen -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// This file defines all of the MIPS specific intrinsics for RISCV. +// +//===----------------------------------------------------------------------===// + +let TargetPrefix = "riscv" in { + def int_riscv_mips_pause : ClangBuiltin<"__builtin_riscv_mips_pause">, + Intrinsic<[], [], [IntrNoMem, IntrHasSideEffects]>; + def int_riscv_mips_ehb : ClangBuiltin<"__builtin_riscv_mips_ehb">, + Intrinsic<[], [], [IntrNoMem, IntrHasSideEffects]>; + def int_riscv_mips_ihb : ClangBuiltin<"__builtin_riscv_mips_ihb">, + Intrinsic<[], [], [IntrNoMem, IntrHasSideEffects]>; +} diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td index 95703e33926c5..6433fe888b894 100644 --- a/llvm/lib/Target/RISCV/RISCVFeatures.td +++ b/llvm/lib/Target/RISCV/RISCVFeatures.td @@ -1426,7 +1426,7 @@ def NoVendorXMIPSCBOP : Predicate<"!Subtarget->hasVendorXMIPSCBOP()">; def FeatureVendorXMIPSEXECTL : RISCVExtension<1, 0, "MIPS execution control">; def HasVendorXMIPSEXECTL - : Predicate<"Subtarget->hasVendorXMIPSEXT()">, + : Predicate<"Subtarget->hasVendorXMIPSEXECTL()">, AssemblerPredicate<(all_of FeatureVendorXMIPSEXECTL), "'Xmipsexectl' (MIPS execution control)">; diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXMips.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXMips.td index d615094329b28..115ab38e5d4c1 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoXMips.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXMips.td @@ -143,6 +143,13 @@ let Predicates = [HasVendorXMIPSEXECTL], DecoderNamespace = "XMIPS" in { def MIPS_PAUSE : MIPSExtInst_ri<0b000101, "mips.pause">; } +let Predicates = [HasVendorXMIPSEXECTL] in { + // Intrinsics + def : Pat<(int_riscv_mips_pause), (MIPS_PAUSE)>; + def : Pat<(int_riscv_mips_ihb), (MIPS_IHB)>; + def : Pat<(int_riscv_mips_ehb), (MIPS_EHB)>; +} + let Predicates = [HasVendorXMIPSCBOP], DecoderNamespace = "XMIPS" in { def MIPS_PREF : Mips_prefetch_ri<(outs), (ins GPR:$rs1, uimm9:$imm9, uimm5:$hint), "mips.pref", "$hint, ${imm9}(${rs1})">, diff --git a/llvm/test/CodeGen/RISCV/xmips-exectl.ll b/llvm/test/CodeGen/RISCV/xmips-exectl.ll new file mode 100644 index 0000000000000..bc0c96e7301b2 --- /dev/null +++ b/llvm/test/CodeGen/RISCV/xmips-exectl.ll @@ -0,0 +1,35 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --tool /home/ukalappa/llvm/github/build/bin/llc --version 6 +; RUN: llc -mtriple=riscv64 -mcpu=mips-p8700 -O3 -verify-machineinstrs < %s \ +; RUN: | FileCheck -check-prefix=MIPS %s + +target datalayout = "e-m:e-p:32:32-i64:64-n32-S128" + +define dso_local void @test_mips_pause() local_unnamed_addr { +; MIPS-LABEL: test_mips_pause: +; MIPS: # %bb.0: # %entry +; MIPS-NEXT: mips.pause +; MIPS-NEXT: ret +entry: + tail call void @llvm.riscv.mips.pause() + ret void +} + +define dso_local void @test_mips_ehb() local_unnamed_addr { +; MIPS-LABEL: test_mips_ehb: +; MIPS: # %bb.0: # %entry +; MIPS-NEXT: mips.ehb +; MIPS-NEXT: ret +entry: + tail call void @llvm.riscv.mips.ehb() + ret void +} + +define dso_local void @test_mips_ihb() local_unnamed_addr { +; MIPS-LABEL: test_mips_ihb: +; MIPS: # %bb.0: # %entry +; MIPS-NEXT: mips.ihb +; MIPS-NEXT: ret +entry: + tail call void @llvm.riscv.mips.ihb() + ret void +} >From fbcef5fa4bb0f5e19aee101c4fdbc745cff699dd Mon Sep 17 00:00:00 2001 From: Umesh Kalappa <ukalappa.m...@gmail.com> Date: Wed, 17 Sep 2025 06:13:10 +0000 Subject: [PATCH 2/3] Testcase fix. --- clang/test/CodeGen/builtins-riscv-mips.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/clang/test/CodeGen/builtins-riscv-mips.c b/clang/test/CodeGen/builtins-riscv-mips.c index 3c6c9b994f5d2..55ce50a85ab38 100644 --- a/clang/test/CodeGen/builtins-riscv-mips.c +++ b/clang/test/CodeGen/builtins-riscv-mips.c @@ -1,5 +1,5 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 6 -// RUN: %clang_cc1 -triple riscv32-linux-elf -O3 -target-feature +xmipsexectl -emit-llvm -o - %s | FileCheck %s RISCV32 +// RUN: %clang_cc1 -triple riscv32-linux-elf -O3 -target-feature +xmipsexectl -emit-llvm -o - %s | FileCheck %s // CHECK-LABEL: define dso_local void @test_mips_pause( // CHECK-SAME: ) local_unnamed_addr #[[ATTR0:[0-9]+]] { >From 3ad228791d98f29e876e0e899501afb471486a65 Mon Sep 17 00:00:00 2001 From: Umesh Kalappa <ukalappa.m...@gmail.com> Date: Thu, 18 Sep 2025 03:41:29 +0000 Subject: [PATCH 3/3] Updated the changes by adopting the suggestions. --- clang/include/clang/Basic/BuiltinsRISCVXMIPS.td | 4 ++-- llvm/include/llvm/IR/IntrinsicsRISCVXMIPS.td | 4 ++-- llvm/test/CodeGen/RISCV/xmips-exectl.ll | 8 ++++---- 3 files changed, 8 insertions(+), 8 deletions(-) diff --git a/clang/include/clang/Basic/BuiltinsRISCVXMIPS.td b/clang/include/clang/Basic/BuiltinsRISCVXMIPS.td index 28cf6c9bb1707..d14cf0858ba4a 100644 --- a/clang/include/clang/Basic/BuiltinsRISCVXMIPS.td +++ b/clang/include/clang/Basic/BuiltinsRISCVXMIPS.td @@ -18,10 +18,10 @@ class RISCVXMIPSBuiltin<string prototype, string features = ""> : TargetBuiltin } //===----------------------------------------------------------------------===// -// MIPS execution control extensions . +// MIPS execution control extensions. //===----------------------------------------------------------------------===// let Attributes = [NoThrow, Const] in { def mips_pause : RISCVXMIPSBuiltin<"void()", "xmipsexectl">; def mips_ehb : RISCVXMIPSBuiltin<"void()", "xmipsexectl">; def mips_ihb : RISCVXMIPSBuiltin<"void()", "xmipsexectl">; -} \ No newline at end of file +} diff --git a/llvm/include/llvm/IR/IntrinsicsRISCVXMIPS.td b/llvm/include/llvm/IR/IntrinsicsRISCVXMIPS.td index ced96ac2e10a7..d231feb7d6618 100644 --- a/llvm/include/llvm/IR/IntrinsicsRISCVXMIPS.td +++ b/llvm/include/llvm/IR/IntrinsicsRISCVXMIPS.td @@ -1,4 +1,4 @@ -//===- IntrinsicsRISCVXMIPS.td - Defines MIPS intrinsics -------*- tablegen -*-===// +//===- IntrinsicsRISCVXMIPS.td - MIPS intrinsics -------*- tablegen -*----===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// // -// This file defines all of the MIPS specific intrinsics for RISCV. +// This file defines all of the MIPS specific intrinsics for RISC-V. // //===----------------------------------------------------------------------===// diff --git a/llvm/test/CodeGen/RISCV/xmips-exectl.ll b/llvm/test/CodeGen/RISCV/xmips-exectl.ll index bc0c96e7301b2..a013e01c7cdc1 100644 --- a/llvm/test/CodeGen/RISCV/xmips-exectl.ll +++ b/llvm/test/CodeGen/RISCV/xmips-exectl.ll @@ -1,10 +1,10 @@ -; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --tool /home/ukalappa/llvm/github/build/bin/llc --version 6 +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6 ; RUN: llc -mtriple=riscv64 -mcpu=mips-p8700 -O3 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=MIPS %s target datalayout = "e-m:e-p:32:32-i64:64-n32-S128" -define dso_local void @test_mips_pause() local_unnamed_addr { +define void @test_mips_pause() { ; MIPS-LABEL: test_mips_pause: ; MIPS: # %bb.0: # %entry ; MIPS-NEXT: mips.pause @@ -14,7 +14,7 @@ entry: ret void } -define dso_local void @test_mips_ehb() local_unnamed_addr { +define void @test_mips_ehb() { ; MIPS-LABEL: test_mips_ehb: ; MIPS: # %bb.0: # %entry ; MIPS-NEXT: mips.ehb @@ -24,7 +24,7 @@ entry: ret void } -define dso_local void @test_mips_ihb() local_unnamed_addr { +define void @test_mips_ihb() { ; MIPS-LABEL: test_mips_ihb: ; MIPS: # %bb.0: # %entry ; MIPS-NEXT: mips.ihb _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
