llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT--> @llvm/pr-subscribers-llvm-transforms @llvm/pr-subscribers-backend-x86 Author: Phoebe Wang (phoebewang) <details> <summary>Changes</summary> The 256-bit maximum vector register size control was removed from AVX10 whitepaper, ref: https://cdrdv2.intel.com/v1/dl/getContent/784343 We have warned these options in LLVM21 through #<!-- -->28154. This patch removes underlying implementations in LLVM22. --- Patch is 455.29 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/157034.diff 156 Files Affected: - (modified) clang/docs/ReleaseNotes.rst (+4) - (modified) clang/docs/UsersManual.rst (+6-51) - (modified) clang/include/clang/Basic/BuiltinsX86.td (+382-382) - (modified) clang/include/clang/Basic/BuiltinsX86_64.td (+15-15) - (modified) clang/include/clang/Driver/Options.td (+4-14) - (modified) clang/lib/Basic/Targets/X86.cpp (+14-83) - (modified) clang/lib/Basic/Targets/X86.h (-3) - (modified) clang/lib/CodeGen/Targets/X86.cpp (+2-20) - (modified) clang/lib/Driver/ToolChains/Arch/X86.cpp (-41) - (modified) clang/lib/Headers/amxavx512intrin.h (+1-1) - (modified) clang/lib/Headers/avx10_2_512bf16intrin.h (+1-1) - (modified) clang/lib/Headers/avx10_2_512convertintrin.h (+1-1) - (modified) clang/lib/Headers/avx10_2_512niintrin.h (+1-1) - (modified) clang/lib/Headers/avx10_2_512satcvtdsintrin.h (+1-1) - (modified) clang/lib/Headers/avx10_2bf16intrin.h (+2-2) - (modified) clang/lib/Headers/avx10_2convertintrin.h (+2-2) - (modified) clang/lib/Headers/avx10_2copyintrin.h (+1-1) - (modified) clang/lib/Headers/avx10_2niintrin.h (+2-2) - (modified) clang/lib/Headers/avx10_2satcvtdsintrin.h (+2-2) - (modified) clang/lib/Headers/avx2intrin.h (-9) - (modified) clang/lib/Headers/avx512bf16intrin.h (+3-4) - (modified) clang/lib/Headers/avx512bitalgintrin.h (+1-2) - (modified) clang/lib/Headers/avx512bwintrin.h (+3-4) - (modified) clang/lib/Headers/avx512cdintrin.h (+2-2) - (modified) clang/lib/Headers/avx512dqintrin.h (+4-3) - (modified) clang/lib/Headers/avx512fintrin.h (+6-5) - (modified) clang/lib/Headers/avx512fp16intrin.h (+4-6) - (modified) clang/lib/Headers/avx512ifmaintrin.h (+2-2) - (modified) clang/lib/Headers/avx512ifmavlintrin.h (+2-2) - (modified) clang/lib/Headers/avx512vbmi2intrin.h (+3-2) - (modified) clang/lib/Headers/avx512vbmiintrin.h (+2-2) - (modified) clang/lib/Headers/avx512vbmivlintrin.h (+2-2) - (modified) clang/lib/Headers/avx512vlbf16intrin.h (+2-2) - (modified) clang/lib/Headers/avx512vlbitalgintrin.h (+2-2) - (modified) clang/lib/Headers/avx512vlbwintrin.h (+2-4) - (modified) clang/lib/Headers/avx512vlcdintrin.h (+2-4) - (modified) clang/lib/Headers/avx512vldqintrin.h (+2-4) - (modified) clang/lib/Headers/avx512vlfp16intrin.h (+2-2) - (modified) clang/lib/Headers/avx512vlintrin.h (+2-4) - (modified) clang/lib/Headers/avx512vlvbmi2intrin.h (+2-2) - (modified) clang/lib/Headers/avx512vlvnniintrin.h (+2-2) - (modified) clang/lib/Headers/avx512vlvp2intersectintrin.h (+2-2) - (modified) clang/lib/Headers/avx512vnniintrin.h (+2-2) - (modified) clang/lib/Headers/avx512vp2intersectintrin.h (+1-2) - (modified) clang/lib/Headers/avx512vpopcntdqintrin.h (+2-3) - (modified) clang/lib/Headers/avx512vpopcntdqvlintrin.h (+4-4) - (modified) clang/lib/Headers/avxintrin.h (-9) - (modified) clang/lib/Headers/emmintrin.h (-6) - (modified) clang/lib/Headers/fmaintrin.h (+2-2) - (modified) clang/lib/Headers/gfniintrin.h (+2-27) - (modified) clang/lib/Headers/mmintrin.h (+3-9) - (modified) clang/lib/Headers/movrs_avx10_2_512intrin.h (+2-2) - (modified) clang/lib/Headers/movrs_avx10_2intrin.h (+4-4) - (modified) clang/lib/Headers/pmmintrin.h (-6) - (modified) clang/lib/Headers/sm4evexintrin.h (+2-2) - (modified) clang/lib/Headers/smmintrin.h (-6) - (modified) clang/lib/Headers/tmmintrin.h (-6) - (modified) clang/lib/Headers/vaesintrin.h (+1-2) - (modified) clang/lib/Headers/xmmintrin.h (-9) - (modified) clang/test/CodeGen/X86/amx_avx512_api.c (+1-1) - (modified) clang/test/CodeGen/X86/amxavx512-builtins.c (+1-1) - (modified) clang/test/CodeGen/X86/avx10_2_512bf16-builtins.c (+2-2) - (modified) clang/test/CodeGen/X86/avx10_2_512convert-builtins.c (+2-2) - (modified) clang/test/CodeGen/X86/avx10_2_512minmax-builtins.c (+2-2) - (modified) clang/test/CodeGen/X86/avx10_2_512minmax-error.c (+2-2) - (modified) clang/test/CodeGen/X86/avx10_2_512ni-builtins.c (+2-2) - (modified) clang/test/CodeGen/X86/avx10_2_512satcvt-builtins.c (+2-2) - (modified) clang/test/CodeGen/X86/avx10_2_512satcvtds-builtins-errors.c (+2-2) - (modified) clang/test/CodeGen/X86/avx10_2_512satcvtds-builtins-x64-error.c (+1-1) - (modified) clang/test/CodeGen/X86/avx10_2_512satcvtds-builtins-x64.c (+1-1) - (modified) clang/test/CodeGen/X86/avx10_2_512satcvtds-builtins.c (+2-2) - (modified) clang/test/CodeGen/X86/avx10_2bf16-builtins.c (+2-2) - (modified) clang/test/CodeGen/X86/avx10_2convert-builtins.c (+2-2) - (modified) clang/test/CodeGen/X86/avx10_2minmax-builtins.c (+2-2) - (modified) clang/test/CodeGen/X86/avx10_2ni-builtins.c (+2-2) - (modified) clang/test/CodeGen/X86/avx10_2satcvt-builtins.c (+2-2) - (modified) clang/test/CodeGen/X86/avx10_2satcvtds-builtins-x64.c (+1-1) - (modified) clang/test/CodeGen/X86/avx10_2satcvtds-builtins.c (+2-2) - (modified) clang/test/CodeGen/X86/avx512-error.c (+4-14) - (modified) clang/test/CodeGen/X86/avx512copy-builtins.c (+1-1) - (modified) clang/test/CodeGen/X86/avx512vlbw-builtins.c (+4-4) - (modified) clang/test/CodeGen/X86/avxvnniint16-builtins.c (+4-4) - (modified) clang/test/CodeGen/X86/avxvnniint8-builtins.c (+4-4) - (modified) clang/test/CodeGen/X86/movrs-avx10.2-512-builtins-error-32.c (+1-1) - (modified) clang/test/CodeGen/X86/movrs-avx10.2-512-builtins.c (+1-1) - (modified) clang/test/CodeGen/X86/movrs-avx10.2-builtins-error-32.c (+1-1) - (modified) clang/test/CodeGen/X86/movrs-avx10.2-builtins.c (+1-1) - (modified) clang/test/CodeGen/X86/sm4-evex-builtins.c (+2-2) - (modified) clang/test/CodeGen/attr-cpuspecific.c (+1-1) - (modified) clang/test/CodeGen/attr-target-x86.c (+7-12) - (modified) clang/test/CodeGen/regcall2.c (+2-2) - (modified) clang/test/CodeGen/target-avx-abi-diag.c (+1-53) - (modified) clang/test/CodeGen/target-builtin-noerror.c (+2-4) - (modified) clang/test/Driver/x86-target-features.c (+8-34) - (modified) clang/test/Preprocessor/predefined-arch-macros-x86.c (-1) - (modified) clang/test/Preprocessor/predefined-arch-macros.c (-48) - (modified) clang/test/Preprocessor/x86_target_features.c (+14-59) - (modified) llvm/include/llvm/TargetParser/X86TargetParser.def (+2-2) - (modified) llvm/lib/IR/Verifier.cpp (-10) - (modified) llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp (-3) - (modified) llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp (-12) - (modified) llvm/lib/Target/X86/X86.td (+12-14) - (modified) llvm/lib/Target/X86/X86ISelLowering.cpp (+14-20) - (modified) llvm/lib/Target/X86/X86ISelLoweringCall.cpp (+2-2) - (modified) llvm/lib/Target/X86/X86InstrAMX.td (+7-7) - (modified) llvm/lib/Target/X86/X86InstrAVX10.td (+52-79) - (modified) llvm/lib/Target/X86/X86InstrAVX512.td (+21-21) - (modified) llvm/lib/Target/X86/X86InstrPredicates.td (-3) - (modified) llvm/lib/Target/X86/X86Subtarget.cpp (-18) - (modified) llvm/lib/Target/X86/X86Subtarget.h (+2-4) - (modified) llvm/lib/Target/X86/X86TargetTransformInfo.cpp (+2-2) - (modified) llvm/lib/TargetParser/Host.cpp (+2-8) - (modified) llvm/lib/TargetParser/X86TargetParser.cpp (+18-22) - (modified) llvm/test/CodeGen/X86/amx-across-func-tilemovrow.ll (+3-3) - (modified) llvm/test/CodeGen/X86/amx-avx512-intrinsics.ll (+1-1) - (modified) llvm/test/CodeGen/X86/amx-tile-avx512-internals.ll (+1-1) - (modified) llvm/test/CodeGen/X86/avx10.2-fma-commute.ll (+1-1) - (modified) llvm/test/CodeGen/X86/avx10_2-cmp.ll (+2-2) - (modified) llvm/test/CodeGen/X86/avx10_2_512bf16-arith.ll (+2-2) - (modified) llvm/test/CodeGen/X86/avx10_2_512bf16-intrinsics.ll (+2-2) - (modified) llvm/test/CodeGen/X86/avx10_2_512convert-intrinsics.ll (+2-2) - (modified) llvm/test/CodeGen/X86/avx10_2_512fptosi_satcvtds.ll (+2-2) - (modified) llvm/test/CodeGen/X86/avx10_2_512minmax-intrinsics.ll (+2-2) - (modified) llvm/test/CodeGen/X86/avx10_2_512ni-intrinsics.ll (+2-2) - (modified) llvm/test/CodeGen/X86/avx10_2_512satcvt-intrinsics.ll (+2-2) - (modified) llvm/test/CodeGen/X86/avx10_2_512satcvtds-intrinsics.ll (+2-2) - (modified) llvm/test/CodeGen/X86/avx10_2bf16-arith.ll (+6-19) - (modified) llvm/test/CodeGen/X86/avx10_2bf16-intrinsics.ll (+2-2) - (modified) llvm/test/CodeGen/X86/avx10_2convert-intrinsics.ll (+2-2) - (modified) llvm/test/CodeGen/X86/avx10_2fptosi_satcvtds.ll (+2-2) - (modified) llvm/test/CodeGen/X86/avx10_2minmax-intrinsics.ll (+2-2) - (modified) llvm/test/CodeGen/X86/avx10_2ni-intrinsics.ll (+2-2) - (modified) llvm/test/CodeGen/X86/avx10_2satcvt-intrinsics.ll (+2-2) - (modified) llvm/test/CodeGen/X86/avx10_2satcvtds-intrinsics.ll (+2-2) - (modified) llvm/test/CodeGen/X86/avx10_2satcvtds-x64-intrinsics.ll (+1-1) - (modified) llvm/test/CodeGen/X86/avx512bwvl-arith.ll (+14-28) - (modified) llvm/test/CodeGen/X86/avx512copy-intrinsics.ll (+1-1) - (modified) llvm/test/CodeGen/X86/avxvnniint16-intrinsics.ll (+2-2) - (modified) llvm/test/CodeGen/X86/avxvnniint8-intrinsics.ll (+2-2) - (modified) llvm/test/CodeGen/X86/comi-flags.ll (+1-1) - (removed) llvm/test/CodeGen/X86/evex512-mem.ll (-29) - (modified) llvm/test/CodeGen/X86/fminimum-fmaximum.ll (+1-1) - (modified) llvm/test/CodeGen/X86/fminimumnum-fmaximumnum.ll (+1-1) - (modified) llvm/test/CodeGen/X86/movrs-avx10.2-512-intrinsics.ll (+1-1) - (modified) llvm/test/CodeGen/X86/movrs-avx10.2-intrinsics.ll (+1-1) - (removed) llvm/test/CodeGen/X86/pr90844.ll (-36) - (modified) llvm/test/CodeGen/X86/sm4-evex-intrinsics.ll (+2-2) - (modified) llvm/test/CodeGen/X86/vector-fshl-128.ll (+1-2) - (modified) llvm/test/CodeGen/X86/vector-fshl-256.ll (+89-140) - (modified) llvm/test/CodeGen/X86/vector-fshr-128.ll (+1-2) - (modified) llvm/test/CodeGen/X86/vector-fshr-256.ll (+68-104) - (modified) llvm/test/Instrumentation/MemorySanitizer/X86/avx10_2_512ni-intrinsics.ll (+1-1) - (modified) llvm/test/Instrumentation/MemorySanitizer/X86/avx10_2ni-intrinsics.ll (+1-1) - (modified) llvm/test/Transforms/LoopVectorize/X86/cost-conditional-branches.ll (+175-17) - (modified) llvm/test/Transforms/SLPVectorizer/X86/revec-getExtractWithExtendCost.ll (+1-1) - (modified) llvm/test/Transforms/SLPVectorizer/X86/revec-load-compress.ll (+1-1) ``````````diff diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst index dd53b4d46f3cc..7b2a0bdfefa2b 100644 --- a/clang/docs/ReleaseNotes.rst +++ b/clang/docs/ReleaseNotes.rst @@ -373,6 +373,10 @@ X86 Support - NOTE: Please avoid use of the __builtin_ia32_* intrinsics - these are not guaranteed to exist in future releases, or match behaviour with previous releases of clang or other compilers. +- Remove `m[no-]avx10.x-[256,512]` and `m[no-]evex512` options from Clang + driver. +- Remove `[no-]evex512` feature request from intrinsics and builtins. +- Change features `avx10.x-[256,512]` to `avx10.x`. Arm and AArch64 Support ^^^^^^^^^^^^^^^^^^^^^^^ diff --git a/clang/docs/UsersManual.rst b/clang/docs/UsersManual.rst index 0e85c8109fd5e..a8bbf146431ea 100644 --- a/clang/docs/UsersManual.rst +++ b/clang/docs/UsersManual.rst @@ -4581,59 +4581,14 @@ implicitly included in later levels. - ``-march=x86-64-v3``: (close to Haswell) AVX, AVX2, BMI1, BMI2, F16C, FMA, LZCNT, MOVBE, XSAVE - ``-march=x86-64-v4``: AVX512F, AVX512BW, AVX512CD, AVX512DQ, AVX512VL -`Intel AVX10 ISA <https://cdrdv2.intel.com/v1/dl/getContent/784267>`_ is +`Intel AVX10 ISA <https://cdrdv2.intel.com/v1/dl/getContent/784343>`_ is a major new vector ISA incorporating the modern vectorization aspects of Intel AVX-512. This ISA will be supported on all future Intel processors. -Users are supposed to use the new options ``-mavx10.N`` and ``-mavx10.N-512`` -on these processors and should not use traditional AVX512 options anymore. - -The ``N`` in ``-mavx10.N`` represents a continuous integer number starting -from ``1``. ``-mavx10.N`` is an alias of ``-mavx10.N-256``, which means to -enable all instructions within AVX10 version N at a maximum vector length of -256 bits. ``-mavx10.N-512`` enables all instructions at a maximum vector -length of 512 bits, which is a superset of instructions ``-mavx10.N`` enabled. - -Current binaries built with AVX512 features can run on Intel AVX10/512 capable -processors without re-compile, but cannot run on AVX10/256 capable processors. -Users need to re-compile their code with ``-mavx10.N``, and maybe update some -code that calling to 512-bit X86 specific intrinsics and passing or returning -512-bit vector types in function call, if they want to run on AVX10/256 capable -processors. Binaries built with ``-mavx10.N`` can run on both AVX10/256 and -AVX10/512 capable processors. - -Users can add a ``-mno-evex512`` in the command line with AVX512 options if -they want to run the binary on both legacy AVX512 and new AVX10/256 capable -processors. The option has the same constraints as ``-mavx10.N``, i.e., -cannot call to 512-bit X86 specific intrinsics and pass or return 512-bit vector -types in function call. - -Users should avoid using AVX512 features in function target attributes when -developing code for AVX10. If they have to do so, they need to add an explicit -``evex512`` or ``no-evex512`` together with AVX512 features for 512-bit or -non-512-bit functions respectively to avoid unexpected code generation. Both -command line option and target attribute of EVEX512 feature can only be used -with AVX512. They don't affect vector size of AVX10. - -User should not mix the use AVX10 and AVX512 options together at any time, -because the option combinations are conflicting sometimes. For example, a -combination of ``-mavx512f -mavx10.1-256`` doesn't show a clear intention to -compiler, since instructions in AVX512F and AVX10.1/256 intersect but do not -overlap. In this case, compiler will emit warning for it, but the behavior -is determined. It will generate the same code as option ``-mavx10.1-512``. -A similar case is ``-mavx512f -mavx10.2-256``, which equals to -``-mavx10.1-512 -mavx10.2-256``, because ``avx10.2-256`` implies ``avx10.1-256`` -and ``-mavx512f -mavx10.1-256`` equals to ``-mavx10.1-512``. - -There are some new macros introduced with AVX10 support. ``-mavx10.1-256`` will -enable ``__AVX10_1__`` and ``__EVEX256__``, while ``-mavx10.1-512`` enables -``__AVX10_1__``, ``__EVEX256__``, ``__EVEX512__`` and ``__AVX10_1_512__``. -Besides, both ``-mavx10.1-256`` and ``-mavx10.1-512`` will enable all AVX512 -feature specific macros. A AVX512 feature will enable both ``__EVEX256__``, -``__EVEX512__`` and its own macro. So ``__EVEX512__`` can be used to guard code -that can run on both legacy AVX512 and AVX10/512 capable processors but cannot -run on AVX10/256, while a AVX512 macro like ``__AVX512F__`` cannot tell the -difference among the three options. Users need to check additional macros -``__AVX10_1__`` and ``__EVEX512__`` if they want to make distinction. +Users are supposed to use the new options ``-mavx10.N`` on these processors +and should not use traditional AVX512 options anymore. The ``N`` in +``-mavx10.N`` represents a continuous integer number starting +from ``1``. Current binaries built with AVX512 features can run on Intel AVX10 +capable processors without re-compile. ARM ^^^ diff --git a/clang/include/clang/Basic/BuiltinsX86.td b/clang/include/clang/Basic/BuiltinsX86.td index acd8f70c4a5f2..cdd5d54a68d79 100644 --- a/clang/include/clang/Basic/BuiltinsX86.td +++ b/clang/include/clang/Basic/BuiltinsX86.td @@ -387,7 +387,7 @@ let Features = "vaes", Attributes = [NoThrow, Const, RequiredVectorWidth<256>] i def aesenc256 : X86Builtin<"_Vector<4, long long int>(_Vector<4, long long int>, _Vector<4, long long int>)">; } -let Features = "avx512f,evex512,vaes", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { +let Features = "avx512f,vaes", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { def aesenc512 : X86Builtin<"_Vector<8, long long int>(_Vector<8, long long int>, _Vector<8, long long int>)">; } @@ -395,7 +395,7 @@ let Features = "vaes", Attributes = [NoThrow, Const, RequiredVectorWidth<256>] i def aesenclast256 : X86Builtin<"_Vector<4, long long int>(_Vector<4, long long int>, _Vector<4, long long int>)">; } -let Features = "avx512f,evex512,vaes", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { +let Features = "avx512f,vaes", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { def aesenclast512 : X86Builtin<"_Vector<8, long long int>(_Vector<8, long long int>, _Vector<8, long long int>)">; } @@ -403,7 +403,7 @@ let Features = "vaes", Attributes = [NoThrow, Const, RequiredVectorWidth<256>] i def aesdec256 : X86Builtin<"_Vector<4, long long int>(_Vector<4, long long int>, _Vector<4, long long int>)">; } -let Features = "avx512f,evex512,vaes", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { +let Features = "avx512f,vaes", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { def aesdec512 : X86Builtin<"_Vector<8, long long int>(_Vector<8, long long int>, _Vector<8, long long int>)">; } @@ -411,7 +411,7 @@ let Features = "vaes", Attributes = [NoThrow, Const, RequiredVectorWidth<256>] i def aesdeclast256 : X86Builtin<"_Vector<4, long long int>(_Vector<4, long long int>, _Vector<4, long long int>)">; } -let Features = "avx512f,evex512,vaes", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { +let Features = "avx512f,vaes", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { def aesdeclast512 : X86Builtin<"_Vector<8, long long int>(_Vector<8, long long int>, _Vector<8, long long int>)">; } @@ -423,7 +423,7 @@ let Features = "avx,gfni", Attributes = [NoThrow, Const, RequiredVectorWidth<256 def vgf2p8affineinvqb_v32qi : X86Builtin<"_Vector<32, char>(_Vector<32, char>, _Vector<32, char>, _Constant char)">; } -let Features = "avx512f,evex512,gfni", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { +let Features = "avx512f,gfni", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { def vgf2p8affineinvqb_v64qi : X86Builtin<"_Vector<64, char>(_Vector<64, char>, _Vector<64, char>, _Constant char)">; } @@ -435,7 +435,7 @@ let Features = "avx,gfni", Attributes = [NoThrow, Const, RequiredVectorWidth<256 def vgf2p8affineqb_v32qi : X86Builtin<"_Vector<32, char>(_Vector<32, char>, _Vector<32, char>, _Constant char)">; } -let Features = "avx512f,evex512,gfni", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { +let Features = "avx512f,gfni", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { def vgf2p8affineqb_v64qi : X86Builtin<"_Vector<64, char>(_Vector<64, char>, _Vector<64, char>, _Constant char)">; } @@ -447,7 +447,7 @@ let Features = "avx,gfni", Attributes = [NoThrow, Const, RequiredVectorWidth<256 def vgf2p8mulb_v32qi : X86Builtin<"_Vector<32, char>(_Vector<32, char>, _Vector<32, char>)">; } -let Features = "avx512f,evex512,gfni", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { +let Features = "avx512f,gfni", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { def vgf2p8mulb_v64qi : X86Builtin<"_Vector<64, char>(_Vector<64, char>, _Vector<64, char>)">; } @@ -459,7 +459,7 @@ let Features = "vpclmulqdq", Attributes = [NoThrow, Const, RequiredVectorWidth<2 def pclmulqdq256 : X86Builtin<"_Vector<4, long long int>(_Vector<4, long long int>, _Vector<4, long long int>, _Constant char)">; } -let Features = "avx512f,evex512,vpclmulqdq", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { +let Features = "avx512f,vpclmulqdq", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { def pclmulqdq512 : X86Builtin<"_Vector<8, long long int>(_Vector<8, long long int>, _Vector<8, long long int>, _Constant char)">; } @@ -830,7 +830,7 @@ let Features = "fma|fma4", Attributes = [NoThrow, Const, RequiredVectorWidth<256 def vfmaddsubpd256 : X86Builtin<"_Vector<4, double>(_Vector<4, double>, _Vector<4, double>, _Vector<4, double>)">; } -let Features = "avx512f,evex512", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { +let Features = "avx512f", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { def vfmaddpd512_mask : X86Builtin<"_Vector<8, double>(_Vector<8, double>, _Vector<8, double>, _Vector<8, double>, unsigned char, _Constant int)">; def vfmaddpd512_maskz : X86Builtin<"_Vector<8, double>(_Vector<8, double>, _Vector<8, double>, _Vector<8, double>, unsigned char, _Constant int)">; def vfmaddpd512_mask3 : X86Builtin<"_Vector<8, double>(_Vector<8, double>, _Vector<8, double>, _Vector<8, double>, unsigned char, _Constant int)">; @@ -936,7 +936,7 @@ let Features = "pku", Attributes = [NoThrow] in { def wrpkru : X86Builtin<"void(unsigned int)">; } -let Features = "avx512f,evex512", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { +let Features = "avx512f", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { def sqrtpd512 : X86Builtin<"_Vector<8, double>(_Vector<8, double>, _Constant int)">; def sqrtps512 : X86Builtin<"_Vector<16, float>(_Vector<16, float>, _Constant int)">; } @@ -946,7 +946,7 @@ let Features = "avx512f", Attributes = [NoThrow, Const, RequiredVectorWidth<128> def rsqrt14ss_mask : X86Builtin<"_Vector<4, float>(_Vector<4, float>, _Vector<4, float>, _Vector<4, float>, unsigned char)">; } -let Features = "avx512f,evex512", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { +let Features = "avx512f", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { def rsqrt14pd512_mask : X86Builtin<"_Vector<8, double>(_Vector<8, double>, _Vector<8, double>, unsigned char)">; def rsqrt14ps512_mask : X86Builtin<"_Vector<16, float>(_Vector<16, float>, _Vector<16, float>, unsigned short)">; } @@ -956,7 +956,7 @@ let Features = "avx512f", Attributes = [NoThrow, Const, RequiredVectorWidth<128> def rcp14ss_mask : X86Builtin<"_Vector<4, float>(_Vector<4, float>, _Vector<4, float>, _Vector<4, float>, unsigned char)">; } -let Features = "avx512f,evex512", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { +let Features = "avx512f", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { def rcp14pd512_mask : X86Builtin<"_Vector<8, double>(_Vector<8, double>, _Vector<8, double>, unsigned char)">; def rcp14ps512_mask : X86Builtin<"_Vector<16, float>(_Vector<16, float>, _Vector<16, float>, unsigned short)">; def cvttps2dq512_mask : X86Builtin<"_Vector<16, int>(_Vector<16, float>, _Vector<16, int>, unsigned short, _Constant int)">; @@ -974,7 +974,7 @@ let Features = "avx512vl", Attributes = [NoThrow, Const, RequiredVectorWidth<128 def cmpps128_mask : X86Builtin<"unsigned char(_Vector<4, float>, _Vector<4, float>, _Constant int, unsigned char)">; } -let Features = "avx512f,evex512", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { +let Features = "avx512f", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { def cmppd512_mask : X86Builtin<"unsigned char(_Vector<8, double>, _Vector<8, double>, _Constant int, unsigned char, _Constant int)">; } @@ -986,7 +986,7 @@ let Features = "avx512vl", Attributes = [NoThrow, Const, RequiredVectorWidth<128 def cmppd128_mask : X86Builtin<"unsigned char(_Vector<2, double>, _Vector<2, double>, _Constant int, unsigned char)">; } -let Features = "avx512f,evex512", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { +let Features = "avx512f", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { def rndscaleps_mask : X86Builtin<"_Vector<16, float>(_Vector<16, float>, _Constant int, _Vector<16, float>, unsigned short, _Constant int)">; def rndscalepd_mask : X86Builtin<"_Vector<8, double>(_Vector<8, double>, _Constant int, _Vector<8, double>, unsigned char, _Constant int)">; def cvtps2dq512_mask : X86Builtin<"_Vector<16, int>(_Vector<16, float>, _Vector<16, int>, unsigned short, _Constant int)">; @@ -1004,12 +1004,12 @@ let Features = "avx512f,evex512", Attributes = [NoThrow, Const, RequiredVectorWi def vcvtph2ps512_mask : X86Builtin<"_Vector<16, float>(_Vector<16, short>, _Vector<16, float>, unsigned short, _Constant int)">; } -let Features = "avx512f,evex512", Attributes = [NoThrow, Const, Constexpr, RequiredVectorWidth<512>] in { +let Features = "avx512f", Attributes = [NoThrow, Const, Constexpr, RequiredVectorWidth<512>] in { def pmuldq512 : X86Builtin<"_Vector<8, long long int>(_Vector<16, int>, _Vector<16, int>)">; def pmuludq512 : X86Builtin<"_Vector<8, long long int>(_Vector<16, int>, _Vector<16, int>)">; } -let Features = "avx512f,evex512", Attributes = [NoThrow, RequiredVectorWidth<512>] in { +let Features = "avx512f", Attributes = [NoThrow, RequiredVectorWidth<512>] in { def loaddqusi512_mask : X86Builtin<"_Vector<16, int>(int const *, _Vector<16, int>, unsigned short)">; def loaddqudi512_mask : X86Builtin<"_Vector<8, long long int>(long long int const *, _Vector<8, long long int>, unsigned char)">; def loadups512_mask : X86Builtin<"_Vector<16, float>(float const *, _Vector<16, float>, unsigned short)">; @@ -1024,7 +1024,7 @@ let Features = "avx512f,evex512", Attributes = [NoThrow, RequiredVectorWidth<512 def storeaps512_mask : X86Builtin<"void(_Vector<16, float *>, _Vector<16, float>, unsigned short)">; } -let Features = "avx512f,evex512", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { +let Features = "avx512f", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { def alignq512 : X86Builtin<"_Vector<8, long long int>(_Vector<8, long long int>, _Vector<8, long long int>, _Constant int)">; def alignd512 : X86Builtin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>, _Constant int)">; } @@ -1045,7 +1045,7 @@ let Features = "avx512vl", Attributes = [NoThrow, Const, RequiredVectorWidth<256 def alignq256 : X86Builtin<"_Vector<4, long long int>(_Vector<4, long long int>, _Vector<4, long long int>, _Constant int)">; } -let Features = "avx512f,evex512", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { +let Features = "avx512f", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { def extractf64x4_mask : X86Builtin<"_Vector<4, double>(_Vector<8, double>, _Constant int, _Vector<4, double>, unsigned char)">; def extractf32x4_mask : X86Builtin<"_Vector<4, float>(_Vector<16, float>, _Constant int, _Vector<4, float>, unsigned char)">; } @@ -1058,7 +1058,7 @@ let Features = "avx512vl,avx512vnni|avxvnni", Attributes = [NoThrow, Const, Requ def vpdpbusd256 : X86Builtin<"_Vector<8, int>(_Vector<8, int>, _Vector<8, int>, _Vector<8, int>)">; } -let Features = "avx512vnni,evex512", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { +let Features = "avx512vnni", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { def vpdpbusd512 : X86Builtin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>, _Vector<16, int>)">; } @@ -1070,7 +1070,7 @@ let Features = "avx512vl,avx512vnni|avxvnni", Attributes = [NoThrow, Const, Requ def vpdpbusds256 : X86Builtin<"_Vector<8, int>(_Vector<8, int>, _Vector<8, int>, _Vector<8, int>)">; } -let Features = "avx512vnni,evex512", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { +let Features = "avx512vnni", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { def vpdpbusds512 : X86Builtin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>, _Vector<16, int>)">; } @@ -1082,7 +1082,7 @@ let Features = "avx512vl,avx512vnni|avxvnni", Attributes = [NoThrow, Const, Requ def vpdpwssd256 : X86Builtin<"_Vector<8, int>(_Vector<8, int>, _Vector<8, int>, _Vector<8, int>)">; } -let Features = "avx512vnni,evex512", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { +let Features = "avx512vnni", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { def vpdpwssd512 : X86Builtin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>, _Vector<16, int>)">; } @@ -1094,55 +1094,55 @@ let Features = "avx512vl,avx512vnni|avxvnni", Attributes = [NoThrow, Const, Requ def vpdpwssds256 : X86Builtin<"_Vector<8, int>(_Vector<8, int>, _Vector<8, int>, _Vector<8, int>)">; } -let Features = "avx512vnni,evex512", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { +let Features = "avx512vnni", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { def vpdpwssds512 : X86Builtin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>, _Vector<16, int>)">; } -let Features = "avxvnniint8|avx10.2-256", Attributes = [NoThrow, Const, RequiredVectorWidth<128>] in { +let Features = "avxvnniint8|avx10.2", Attributes = [NoThrow, Const, RequiredVectorWidth<128>] in { def vpdpbssd128 : X86Builtin<"_Vector<4, int>(_Vector<4, int>, _Vector<4, int>, _Vector<4, int>)">; } -let Features = "avxvnniint8|avx10.2-256", Attributes = [NoThrow, Const, RequiredVectorWidth<256>] in { +let Features = "avxvnniint8|avx10.2", Attributes = [NoThrow, Const, RequiredVectorWidth<256>] in { def vpdpbssd256 : X86Builtin<"_Vector<8, int>(_Vector<8, int>, _Vector<8, int>, _Vector<8, int>)">; } -let Features = "avxvnniint8|avx10.2-256", Attributes = [NoThrow, Const, RequiredVectorWidth<128>] in { +let Features = "avxvnniint8|avx10.2", Attributes = [NoThrow, Const, RequiredVectorWidth<128>] in { def vpdpbssds128 : X86Builtin<"_Vector<4, int>(_Vector<4, int>, _Vector<4, int>, _Vector<4, int>)">; } -let Features = "avxvnniint8|avx10.2-256", Attributes = [NoThrow, Const, RequiredVectorWidth<256>] in { +let Features = "avxvnniint8|avx10.2", Attributes = [NoThrow, Const, RequiredVectorWidth<256>] in { def vpdpbssds256 : X86Builtin<"_Vector<8, int>(_Vector<8, int>, _Vector<8, int>, _Vector<8, int>)">; } -let Features = "avxvnniint8|avx10.2-256", Attributes = [NoThrow, Const, RequiredVectorWidth<128>] in { +let Features = "avxvnniint8|avx10.2", Attributes = [NoThrow, Const, RequiredVectorWidth<128>] in { def vpdpbsud128 : X86Builtin<"_Vector<4, int>(_Vector<4, int>, _Vector<4, int>, _Vector<4, int>)">; } -let Features = "avxvnniint8|avx10.2-256", Attributes = [NoThrow, Const, RequiredVectorWidth<256>] in { +let Features = "avxvnniint8|avx10.2", Attributes = [NoThrow, Const, RequiredVectorWidth<256>] in { def vpdpbsud256 : X86Builtin<"_Vector<8, int>(_Vector<8, int>, _Vector<8, int>, _Vector<8, int>)">; } -let Features = "avxvnniint8|avx10.2-256", Attributes = [NoThrow, Const, RequiredVectorWidth<128>] in { +let Features = "avxvnniint8|avx10.2", Attributes = [NoThrow, Const, RequiredVectorWidth<128>] in { def vpdpbsuds128 : X86Builtin<"_Vector<4, int>(_Vector<4, int>, _Vector<4, int>, _Vector<4, int>)">; } -let Features = "avxvnniint8|avx10.2-256", Attributes = [... [truncated] `````````` </details> https://github.com/llvm/llvm-project/pull/157034 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
