llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT--> @llvm/pr-subscribers-clang Author: Paul Walker (paulwalker-arm) <details> <summary>Changes</summary> Only set a target guard if it deviates from its default value[1]. When a target guard is set, it is automatically AND'd with its default value. This means there is no need to use SVETargetGuard="sve,bf16" because SVETargetGuard="bf16" is sufficient. [1] Defaults: SVETargetGuard="sve", SMETargetGuard="sme" --- Patch is 42.13 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/152547.diff 3 Files Affected: - (modified) clang/include/clang/Basic/arm_sme.td (+78-102) - (modified) clang/include/clang/Basic/arm_sve.td (+44-44) - (modified) clang/utils/TableGen/SveEmitter.cpp (+2-2) ``````````diff diff --git a/clang/include/clang/Basic/arm_sme.td b/clang/include/clang/Basic/arm_sme.td index c491eb0f7e460..a4eb92e76968c 100644 --- a/clang/include/clang/Basic/arm_sme.td +++ b/clang/include/clang/Basic/arm_sme.td @@ -21,23 +21,21 @@ let SVETargetGuard = InvalidMode in { // Loads multiclass ZALoad<string n_suffix, string t, string i_prefix, list<ImmCheck> ch> { - let SMETargetGuard = "sme" in { - def NAME # _H : MInst<"svld1_hor_" # n_suffix, "vimPQ", t, - [IsLoad, IsOverloadNone, IsStreaming, IsInOutZA], - MemEltTyDefault, i_prefix # "_horiz", ch>; - - def NAME # _H_VNUM : MInst<"svld1_hor_vnum_" # n_suffix, "vimPQl", t, - [IsLoad, IsOverloadNone, IsStreaming, IsInOutZA], - MemEltTyDefault, i_prefix # "_horiz", ch>; - - def NAME # _V : MInst<"svld1_ver_" # n_suffix, "vimPQ", t, - [IsLoad, IsOverloadNone, IsStreaming, IsInOutZA], - MemEltTyDefault, i_prefix # "_vert", ch>; - - def NAME # _V_VNUM : MInst<"svld1_ver_vnum_" # n_suffix, "vimPQl", t, - [IsLoad, IsOverloadNone, IsStreaming, IsInOutZA], - MemEltTyDefault, i_prefix # "_vert", ch>; - } + def NAME # _H : MInst<"svld1_hor_" # n_suffix, "vimPQ", t, + [IsLoad, IsOverloadNone, IsStreaming, IsInOutZA], + MemEltTyDefault, i_prefix # "_horiz", ch>; + + def NAME # _H_VNUM : MInst<"svld1_hor_vnum_" # n_suffix, "vimPQl", t, + [IsLoad, IsOverloadNone, IsStreaming, IsInOutZA], + MemEltTyDefault, i_prefix # "_horiz", ch>; + + def NAME # _V : MInst<"svld1_ver_" # n_suffix, "vimPQ", t, + [IsLoad, IsOverloadNone, IsStreaming, IsInOutZA], + MemEltTyDefault, i_prefix # "_vert", ch>; + + def NAME # _V_VNUM : MInst<"svld1_ver_vnum_" # n_suffix, "vimPQl", t, + [IsLoad, IsOverloadNone, IsStreaming, IsInOutZA], + MemEltTyDefault, i_prefix # "_vert", ch>; } defm SVLD1_ZA8 : ZALoad<"za8", "c", "aarch64_sme_ld1b", [ImmCheck<0, ImmCheck0_0>]>; @@ -46,7 +44,6 @@ defm SVLD1_ZA32 : ZALoad<"za32", "i", "aarch64_sme_ld1w", [ImmCheck<0, ImmCheck0 defm SVLD1_ZA64 : ZALoad<"za64", "l", "aarch64_sme_ld1d", [ImmCheck<0, ImmCheck0_7>]>; defm SVLD1_ZA128 : ZALoad<"za128", "q", "aarch64_sme_ld1q", [ImmCheck<0, ImmCheck0_15>]>; -let SMETargetGuard = "sme" in { def SVLDR_VNUM_ZA : MInst<"svldr_vnum_za", "vmQl", "", [IsOverloadNone, IsStreamingCompatible, IsInOutZA], MemEltTyDefault, "aarch64_sme_ldr">; @@ -54,29 +51,26 @@ def SVLDR_VNUM_ZA : MInst<"svldr_vnum_za", "vmQl", "", def SVLDR_ZA : MInst<"svldr_za", "vmQ", "", [IsOverloadNone, IsStreamingCompatible, IsInOutZA], MemEltTyDefault, "aarch64_sme_ldr", []>; -} //////////////////////////////////////////////////////////////////////////////// // Stores multiclass ZAStore<string n_suffix, string t, string i_prefix, list<ImmCheck> ch> { - let SMETargetGuard = "sme" in { - def NAME # _H : MInst<"svst1_hor_" # n_suffix, "vimP%", t, - [IsStore, IsOverloadNone, IsStreaming, IsInZA], - MemEltTyDefault, i_prefix # "_horiz", ch>; - - def NAME # _H_VNUM : MInst<"svst1_hor_vnum_" # n_suffix, "vimP%l", t, - [IsStore, IsOverloadNone, IsStreaming, IsInZA], - MemEltTyDefault, i_prefix # "_horiz", ch>; - - def NAME # _V : MInst<"svst1_ver_" # n_suffix, "vimP%", t, - [IsStore, IsOverloadNone, IsStreaming, IsInZA], - MemEltTyDefault, i_prefix # "_vert", ch>; - - def NAME # _V_VNUM : MInst<"svst1_ver_vnum_" # n_suffix, "vimP%l", t, - [IsStore, IsOverloadNone, IsStreaming, IsInZA], - MemEltTyDefault, i_prefix # "_vert", ch>; - } + def NAME # _H : MInst<"svst1_hor_" # n_suffix, "vimP%", t, + [IsStore, IsOverloadNone, IsStreaming, IsInZA], + MemEltTyDefault, i_prefix # "_horiz", ch>; + + def NAME # _H_VNUM : MInst<"svst1_hor_vnum_" # n_suffix, "vimP%l", t, + [IsStore, IsOverloadNone, IsStreaming, IsInZA], + MemEltTyDefault, i_prefix # "_horiz", ch>; + + def NAME # _V : MInst<"svst1_ver_" # n_suffix, "vimP%", t, + [IsStore, IsOverloadNone, IsStreaming, IsInZA], + MemEltTyDefault, i_prefix # "_vert", ch>; + + def NAME # _V_VNUM : MInst<"svst1_ver_vnum_" # n_suffix, "vimP%l", t, + [IsStore, IsOverloadNone, IsStreaming, IsInZA], + MemEltTyDefault, i_prefix # "_vert", ch>; } defm SVST1_ZA8 : ZAStore<"za8", "c", "aarch64_sme_st1b", [ImmCheck<0, ImmCheck0_0>]>; @@ -85,7 +79,6 @@ defm SVST1_ZA32 : ZAStore<"za32", "i", "aarch64_sme_st1w", [ImmCheck<0, ImmCheck defm SVST1_ZA64 : ZAStore<"za64", "l", "aarch64_sme_st1d", [ImmCheck<0, ImmCheck0_7>]>; defm SVST1_ZA128 : ZAStore<"za128", "q", "aarch64_sme_st1q", [ImmCheck<0, ImmCheck0_15>]>; -let SMETargetGuard = "sme" in { def SVSTR_VNUM_ZA : MInst<"svstr_vnum_za", "vm%l", "", [IsOverloadNone, IsStreamingCompatible, IsInZA], MemEltTyDefault, "aarch64_sme_str">; @@ -93,21 +86,18 @@ def SVSTR_VNUM_ZA : MInst<"svstr_vnum_za", "vm%l", "", def SVSTR_ZA : MInst<"svstr_za", "vm%", "", [IsOverloadNone, IsStreamingCompatible, IsInZA], MemEltTyDefault, "aarch64_sme_str", []>; -} //////////////////////////////////////////////////////////////////////////////// // Read horizontal/vertical ZA slices multiclass ZARead<string n_suffix, string t, string i_prefix, list<ImmCheck> ch> { - let SMETargetGuard = "sme" in { - def NAME # _H : SInst<"svread_hor_" # n_suffix # "[_{d}]", "ddPim", t, - MergeOp1, i_prefix # "_horiz", - [IsReadZA, IsStreaming, IsInZA], ch>; - - def NAME # _V : SInst<"svread_ver_" # n_suffix # "[_{d}]", "ddPim", t, - MergeOp1, i_prefix # "_vert", - [IsReadZA, IsStreaming, IsInZA], ch>; - } + def NAME # _H : SInst<"svread_hor_" # n_suffix # "[_{d}]", "ddPim", t, + MergeOp1, i_prefix # "_horiz", + [IsReadZA, IsStreaming, IsInZA], ch>; + + def NAME # _V : SInst<"svread_ver_" # n_suffix # "[_{d}]", "ddPim", t, + MergeOp1, i_prefix # "_vert", + [IsReadZA, IsStreaming, IsInZA], ch>; } defm SVREAD_ZA8 : ZARead<"za8", "cUcm", "aarch64_sme_read", [ImmCheck<2, ImmCheck0_0>]>; @@ -120,15 +110,13 @@ defm SVREAD_ZA128 : ZARead<"za128", "csilUcUsUiUlmhbfd", "aarch64_sme_readq", [I // Write horizontal/vertical ZA slices multiclass ZAWrite<string n_suffix, string t, string i_prefix, list<ImmCheck> ch> { - let SMETargetGuard = "sme" in { - def NAME # _H : SInst<"svwrite_hor_" # n_suffix # "[_{d}]", "vimPd", t, - MergeOp1, i_prefix # "_horiz", - [IsWriteZA, IsStreaming, IsInOutZA], ch>; - - def NAME # _V : SInst<"svwrite_ver_" # n_suffix # "[_{d}]", "vimPd", t, - MergeOp1, i_prefix # "_vert", - [IsWriteZA, IsStreaming, IsInOutZA], ch>; - } + def NAME # _H : SInst<"svwrite_hor_" # n_suffix # "[_{d}]", "vimPd", t, + MergeOp1, i_prefix # "_horiz", + [IsWriteZA, IsStreaming, IsInOutZA], ch>; + + def NAME # _V : SInst<"svwrite_ver_" # n_suffix # "[_{d}]", "vimPd", t, + MergeOp1, i_prefix # "_vert", + [IsWriteZA, IsStreaming, IsInOutZA], ch>; } defm SVWRITE_ZA8 : ZAWrite<"za8", "cUcm", "aarch64_sme_write", [ImmCheck<0, ImmCheck0_0>]>; @@ -140,13 +128,11 @@ defm SVWRITE_ZA128 : ZAWrite<"za128", "csilUcUsUiUlmhbfd", "aarch64_sme_writeq", //////////////////////////////////////////////////////////////////////////////// // SME - Zero -let SMETargetGuard = "sme" in { - def SVZERO_MASK_ZA : SInst<"svzero_mask_za", "vi", "", MergeNone, "aarch64_sme_zero", - [IsOverloadNone, IsStreamingCompatible, IsInOutZA], - [ImmCheck<0, ImmCheck0_255>]>; - def SVZERO_ZA : SInst<"svzero_za", "vv", "", MergeNone, "aarch64_sme_zero", - [IsOverloadNone, IsStreamingCompatible, IsOutZA]>; -} +def SVZERO_MASK_ZA : SInst<"svzero_mask_za", "vi", "", MergeNone, "aarch64_sme_zero", + [IsOverloadNone, IsStreamingCompatible, IsInOutZA], + [ImmCheck<0, ImmCheck0_255>]>; +def SVZERO_ZA : SInst<"svzero_za", "vv", "", MergeNone, "aarch64_sme_zero", + [IsOverloadNone, IsStreamingCompatible, IsOutZA]>; let SMETargetGuard = "sme2p1" in { def SVZERO_ZA64_VG1x2 : SInst<"svzero_za64_vg1x2", "vm", "", MergeNone, "aarch64_sme_zero_za64_vg1x2", @@ -171,11 +157,9 @@ let SMETargetGuard = "sme2p1" in { // SME - Counting elements in a streaming vector multiclass ZACount<string n_suffix> { - let SMETargetGuard = "sme" in { - def NAME : SInst<"sv" # n_suffix, "nv", "", MergeNone, - "aarch64_sme_" # n_suffix, - [IsOverloadNone, IsStreamingCompatible]>; - } + def NAME : SInst<"sv" # n_suffix, "nv", "", MergeNone, + "aarch64_sme_" # n_suffix, + [IsOverloadNone, IsStreamingCompatible]>; } defm SVCNTSB : ZACount<"cntsb">; @@ -187,11 +171,9 @@ defm SVCNTSD : ZACount<"cntsd">; // SME - ADDHA/ADDVA multiclass ZAAdd<string n_suffix> { - let SMETargetGuard = "sme" in { - def NAME # _ZA32: SInst<"sv" # n_suffix # "_za32[_{d}]", "viPPd", "iUi", MergeOp1, - "aarch64_sme_" # n_suffix, [IsStreaming, IsInOutZA], - [ImmCheck<0, ImmCheck0_3>]>; - } + def NAME # _ZA32: SInst<"sv" # n_suffix # "_za32[_{d}]", "viPPd", "iUi", MergeOp1, + "aarch64_sme_" # n_suffix, [IsStreaming, IsInOutZA], + [ImmCheck<0, ImmCheck0_3>]>; let SMETargetGuard = "sme-i16i64" in { def NAME # _ZA64: SInst<"sv" # n_suffix # "_za64[_{d}]", "viPPd", "lUl", MergeOp1, @@ -207,13 +189,11 @@ defm SVADDVA : ZAAdd<"addva">; // SME - SMOPA, SMOPS, UMOPA, UMOPS multiclass ZAIntOuterProd<string n_suffix1, string n_suffix2> { - let SMETargetGuard = "sme" in { - def NAME # _ZA32_B: SInst<"sv" # n_suffix2 # "_za32[_{d}]", - "viPPdd", !cond(!eq(n_suffix1, "s") : "", true: "U") # "c", - MergeOp1, "aarch64_sme_" # n_suffix1 # n_suffix2 # "_wide", - [IsStreaming, IsInOutZA], - [ImmCheck<0, ImmCheck0_3>]>; - } + def NAME # _ZA32_B: SInst<"sv" # n_suffix2 # "_za32[_{d}]", + "viPPdd", !cond(!eq(n_suffix1, "s") : "", true: "U") # "c", + MergeOp1, "aarch64_sme_" # n_suffix1 # n_suffix2 # "_wide", + [IsStreaming, IsInOutZA], + [ImmCheck<0, ImmCheck0_3>]>; let SMETargetGuard = "sme-i16i64" in { def NAME # _ZA64_H: SInst<"sv" # n_suffix2 # "_za64[_{d}]", @@ -233,14 +213,12 @@ defm SVUMOPS : ZAIntOuterProd<"u", "mops">; // SME - SUMOPA, SUMOPS, USMOPA, USMOPS multiclass ZAIntOuterProdMixedSigns<string n_suffix1, string n_suffix2> { - let SMETargetGuard = "sme" in { - def NAME # _ZA32_B: SInst<"sv" # n_suffix1 # n_suffix2 # "_za32[_{d}]", - "viPPd" # !cond(!eq(n_suffix1, "su") : "u", true: "x"), - !cond(!eq(n_suffix1, "su") : "", true: "U") # "c", - MergeOp1, "aarch64_sme_" # n_suffix1 # n_suffix2 # "_wide", - [IsStreaming, IsInOutZA], - [ImmCheck<0, ImmCheck0_3>]>; - } + def NAME # _ZA32_B: SInst<"sv" # n_suffix1 # n_suffix2 # "_za32[_{d}]", + "viPPd" # !cond(!eq(n_suffix1, "su") : "u", true: "x"), + !cond(!eq(n_suffix1, "su") : "", true: "U") # "c", + MergeOp1, "aarch64_sme_" # n_suffix1 # n_suffix2 # "_wide", + [IsStreaming, IsInOutZA], + [ImmCheck<0, ImmCheck0_3>]>; let SMETargetGuard = "sme-i16i64" in { def NAME # _ZA64_H: SInst<"sv" # n_suffix1 # n_suffix2 # "_za64[_{d}]", @@ -261,22 +239,20 @@ defm SVUSMOPS : ZAIntOuterProdMixedSigns<"us", "mops">; // SME - FMOPA, FMOPS multiclass ZAFPOuterProd<string n_suffix> { - let SMETargetGuard = "sme" in { - def NAME # _ZA32_B: SInst<"sv" # n_suffix # "_za32[_{d}]", "viPPdd", "h", - MergeOp1, "aarch64_sme_" # n_suffix # "_wide", - [IsStreaming, IsInOutZA], - [ImmCheck<0, ImmCheck0_3>]>; + def NAME # _ZA32_B: SInst<"sv" # n_suffix # "_za32[_{d}]", "viPPdd", "h", + MergeOp1, "aarch64_sme_" # n_suffix # "_wide", + [IsStreaming, IsInOutZA], + [ImmCheck<0, ImmCheck0_3>]>; - def NAME # _ZA32_H: SInst<"sv" # n_suffix # "_za32[_{d}]", "viPPdd", "b", - MergeOp1, "aarch64_sme_" # n_suffix # "_wide", - [IsStreaming, IsInOutZA], - [ImmCheck<0, ImmCheck0_3>]>; + def NAME # _ZA32_H: SInst<"sv" # n_suffix # "_za32[_{d}]", "viPPdd", "b", + MergeOp1, "aarch64_sme_" # n_suffix # "_wide", + [IsStreaming, IsInOutZA], + [ImmCheck<0, ImmCheck0_3>]>; - def NAME # _ZA32_S: SInst<"sv" # n_suffix # "_za32[_{d}]", "viPPdd", "f", - MergeOp1, "aarch64_sme_" # n_suffix, - [IsStreaming, IsInOutZA], - [ImmCheck<0, ImmCheck0_3>]>; - } + def NAME # _ZA32_S: SInst<"sv" # n_suffix # "_za32[_{d}]", "viPPdd", "f", + MergeOp1, "aarch64_sme_" # n_suffix, + [IsStreaming, IsInOutZA], + [ImmCheck<0, ImmCheck0_3>]>; let SMETargetGuard = "sme-f64f64" in { def NAME # _ZA64_D: SInst<"sv" # n_suffix # "_za64[_{d}]", "viPPdd", "d", diff --git a/clang/include/clang/Basic/arm_sve.td b/clang/include/clang/Basic/arm_sve.td index 07786c6c8a7ee..1c8f4849da1a4 100644 --- a/clang/include/clang/Basic/arm_sve.td +++ b/clang/include/clang/Basic/arm_sve.td @@ -36,7 +36,7 @@ def SVLD1UH_VNUM : MInst<"svld1uh_vnum_{d}", "dPXl", "ilUiUl", [IsLoa def SVLD1SW_VNUM : MInst<"svld1sw_vnum_{d}", "dPUl", "lUl", [IsLoad, VerifyRuntimeMode], MemEltTyInt32, "aarch64_sve_ld1">; def SVLD1UW_VNUM : MInst<"svld1uw_vnum_{d}", "dPYl", "lUl", [IsLoad, IsZExtReturn, VerifyRuntimeMode], MemEltTyInt32, "aarch64_sve_ld1">; -let SVETargetGuard = "sve", SMETargetGuard = InvalidMode in { +let SMETargetGuard = InvalidMode in { // Load one vector (vector base) def SVLD1_GATHER_BASES_U : MInst<"svld1_gather[_{2}base]_{d}", "dPu", "ilUiUlfd", [IsGatherLoad], MemEltTyDefault, "aarch64_sve_ld1_gather_scalar_offset">; def SVLD1SB_GATHER_BASES_U : MInst<"svld1sb_gather[_{2}base]_{d}", "dPu", "ilUiUl", [IsGatherLoad], MemEltTyInt8, "aarch64_sve_ld1_gather_scalar_offset">; @@ -134,7 +134,7 @@ def SVLDFF1SW_VNUM : MInst<"svldff1sw_vnum_{d}", "dPUl", "lUl", [I def SVLDFF1UW_VNUM : MInst<"svldff1uw_vnum_{d}", "dPYl", "lUl", [IsLoad, IsZExtReturn], MemEltTyInt32, "aarch64_sve_ldff1">; } -let SVETargetGuard = "sve", SMETargetGuard = InvalidMode in { +let SMETargetGuard = InvalidMode in { // First-faulting load one vector (vector base) def SVLDFF1_GATHER_BASES_U : MInst<"svldff1_gather[_{2}base]_{d}", "dPu", "ilUiUlfd", [IsGatherLoad], MemEltTyDefault, "aarch64_sve_ldff1_gather_scalar_offset">; def SVLDFF1SB_GATHER_BASES_U : MInst<"svldff1sb_gather[_{2}base]_{d}", "dPu", "ilUiUl", [IsGatherLoad], MemEltTyInt8, "aarch64_sve_ldff1_gather_scalar_offset">; @@ -251,15 +251,15 @@ def SVLD3_VNUM : SInst<"svld3_vnum[_{2}]", "3Pcl", "csilUcUsUiUlhfdbm", MergeNon def SVLD4_VNUM : SInst<"svld4_vnum[_{2}]", "4Pcl", "csilUcUsUiUlhfdbm", MergeNone, "aarch64_sve_ld4_sret", [IsStructLoad, VerifyRuntimeMode]>; // Load one octoword and replicate (scalar base) -let SVETargetGuard = "sve,f64mm", SMETargetGuard = InvalidMode in { +let SVETargetGuard = "f64mm", SMETargetGuard = InvalidMode in { def SVLD1RO : SInst<"svld1ro[_{2}]", "dPc", "csilUcUsUiUlhfdbm", MergeNone, "aarch64_sve_ld1ro">; } -let SVETargetGuard = "sve,bf16", SMETargetGuard = InvalidMode in { +let SVETargetGuard = "bf16", SMETargetGuard = InvalidMode in { def SVBFMMLA : SInst<"svbfmmla[_{0}]", "MMdd", "b", MergeNone, "aarch64_sve_bfmmla", [IsOverloadNone]>; } -let SVETargetGuard = "sve,bf16", SMETargetGuard = "sme,bf16" in { +let SVETargetGuard = "bf16", SMETargetGuard = "bf16" in { def SVBFDOT : SInst<"svbfdot[_{0}]", "MMdd", "b", MergeNone, "aarch64_sve_bfdot", [IsOverloadNone, VerifyRuntimeMode]>; def SVBFMLALB : SInst<"svbfmlalb[_{0}]", "MMdd", "b", MergeNone, "aarch64_sve_bfmlalb", [IsOverloadNone, VerifyRuntimeMode]>; def SVBFMLALT : SInst<"svbfmlalt[_{0}]", "MMdd", "b", MergeNone, "aarch64_sve_bfmlalt", [IsOverloadNone, VerifyRuntimeMode]>; @@ -326,7 +326,7 @@ def SVST1H_VNUM_U : MInst<"svst1h_vnum[_{d}]", "vPFld", "UiUl", [Is def SVST1W_VNUM_S : MInst<"svst1w_vnum[_{d}]", "vPCld", "l", [IsStore, VerifyRuntimeMode], MemEltTyInt32, "aarch64_sve_st1">; def SVST1W_VNUM_U : MInst<"svst1w_vnum[_{d}]", "vPGld", "Ul", [IsStore, VerifyRuntimeMode], MemEltTyInt32, "aarch64_sve_st1">; -let SVETargetGuard = "sve", SMETargetGuard = InvalidMode in { +let SMETargetGuard = InvalidMode in { // Store one vector (vector base) def SVST1_SCATTER_BASES_U : MInst<"svst1_scatter[_{2}base_{d}]", "vPud", "ilUiUlfd", [IsScatterStore], MemEltTyDefault, "aarch64_sve_st1_scatter_scalar_offset">; def SVST1B_SCATTER_BASES_U : MInst<"svst1b_scatter[_{2}base_{d}]", "vPud", "ilUiUl", [IsScatterStore], MemEltTyInt8, "aarch64_sve_st1_scatter_scalar_offset">; @@ -464,7 +464,7 @@ def SVPRFH_VNUM : MInst<"svprfh_vnum", "vPQlJ", "s", [IsPrefetch, VerifyRuntimeM def SVPRFW_VNUM : MInst<"svprfw_vnum", "vPQlJ", "i", [IsPrefetch, VerifyRuntimeMode], MemEltTyInt32, "aarch64_sve_prf">; def SVPRFD_VNUM : MInst<"svprfd_vnum", "vPQlJ", "l", [IsPrefetch, VerifyRuntimeMode], MemEltTyInt64, "aarch64_sve_prf">; -let SVETargetGuard = "sve", SMETargetGuard = InvalidMode in { +let SMETargetGuard = InvalidMode in { // Prefetch (Vector bases) def SVPRFB_GATHER_BASES : MInst<"svprfb_gather[_{2}base]", "vPdJ", "UiUl", [IsGatherPrefetch], MemEltTyInt8, "aarch64_sve_prfb_gather_scalar_offset">; def SVPRFH_GATHER_BASES : MInst<"svprfh_gather[_{2}base]", "vPdJ", "UiUl", [IsGatherPrefetch], MemEltTyInt16, "aarch64_sve_prfh_gather_scalar_offset">; @@ -502,7 +502,7 @@ def SVPRFD_GATHER_BASES_OFFSET : MInst<"svprfd_gather[_{2}base]_index", "vPdlJ" //////////////////////////////////////////////////////////////////////////////// // Address calculations -let SVETargetGuard = "sve", SMETargetGuard = InvalidMode in { +let SMETargetGuard = InvalidMode in { def SVADRB : SInst<"svadrb[_{0}base]_[{2}]offset", "uud", "ilUiUl", MergeNone, "aarch64_sve_adrb">; def SVADRH : SInst<"svadrh[_{0}base]_[{2}]index", "uud", "ilUiUl", MergeNone, "aarch64_sve_adrh">; def SVADRW : SInst<"svadrw[_{0}base]_[{2}]index", "uud", "ilUiUl", MergeNone, "aarch64_sve_adrw">; @@ -778,11 +778,11 @@ defm SVRINTX : SInstZPZ<"svrintx", "hfd", "aarch64_sve_frintx">; defm SVRINTZ : SInstZPZ<"svrintz", "hfd", "aarch64_sve_frintz">; defm SVSQRT : S... [truncated] `````````` </details> https://github.com/llvm/llvm-project/pull/152547 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
