Author: Amr Hesham Date: 2025-06-03T00:22:44+02:00 New Revision: 071e55baf1ab16264021c9c52ecd4f88c325e988
URL: https://github.com/llvm/llvm-project/commit/071e55baf1ab16264021c9c52ecd4f88c325e988 DIFF: https://github.com/llvm/llvm-project/commit/071e55baf1ab16264021c9c52ecd4f88c325e988.diff LOG: [CIR][NFS] Remove unnecessary constraints asserts in VecCmpOp (#142473) We already have constraints in CIROps to make sure that the operands and result type are vectors [VecCmpOp](https://github.com/llvm/llvm-project/blob/b88dfb0b23d0a1863414fb9450ee444766bfe7c9/clang/include/clang/CIR/Dialect/IR/CIROps.td#L2149-L2151) Added: Modified: clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp Removed: ################################################################################ diff --git a/clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp b/clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp index 73732a81c039b..f61e85ce3ccec 100644 --- a/clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp +++ b/clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp @@ -1858,10 +1858,6 @@ mlir::LogicalResult CIRToLLVMVecInsertOpLowering::matchAndRewrite( mlir::LogicalResult CIRToLLVMVecCmpOpLowering::matchAndRewrite( cir::VecCmpOp op, OpAdaptor adaptor, mlir::ConversionPatternRewriter &rewriter) const { - assert(mlir::isa<cir::VectorType>(op.getType()) && - mlir::isa<cir::VectorType>(op.getLhs().getType()) && - mlir::isa<cir::VectorType>(op.getRhs().getType()) && - "Vector compare with non-vector type"); mlir::Type elementType = elementTypeIfVector(op.getLhs().getType()); mlir::Value bitResult; if (auto intType = mlir::dyn_cast<cir::IntType>(elementType)) { _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
