https://github.com/maryammo created
https://github.com/llvm/llvm-project/pull/142480
Define the __dmr type used to manipulate the new DMR registers introduced by
the Dense Math Facility (DMF) on PowerPC, and add six Clang builtins that
correspond to the integer outer-product accumulate to ACC instructions:
__builtin_mma_dmxvi8gerx4, __builtin_mma_pmdmxvi8gerx4,
__builtin_mma_dmxvi8gerx4pp, __builtin_mma_pmdmxvi8gerx4pp,
__builtin_mma_dmxvi8gerx4spp, and __builtin_mma_pmdmxvi8gerx4spp.
>From 5ef7a4ca7c2a838a6b2100968d5023e0797b2848 Mon Sep 17 00:00:00 2001
From: Maryam Moghadas <marya...@ca.ibm.com>
Date: Mon, 2 Jun 2025 19:54:57 +0000
Subject: [PATCH] [Clang][PowerPC] Add __dmr type and DMF integer calculation
builtins
Define the __dmr type used to manipulate the new DMR registers introduced by
the Dense Math Facility (DMF) on PowerPC, and add six Clang builtins that
correspond to the integer outer-product accumulate to ACC instructions:
__builtin_mma_dmxvi8gerx4, __builtin_mma_pmdmxvi8gerx4,
__builtin_mma_dmxvi8gerx4pp, __builtin_mma_pmdmxvi8gerx4pp,
__builtin_mma_dmxvi8gerx4spp, and __builtin_mma_pmdmxvi8gerx4spp.
---
clang/include/clang/Basic/BuiltinsPPC.def | 12 ++
clang/include/clang/Basic/PPCTypes.def | 1 +
clang/lib/AST/ASTContext.cpp | 1 +
clang/test/AST/ast-dump-ppc-types.c | 13 +-
.../CodeGen/PowerPC/builtins-ppc-mmaplus.c | 94 +++++++++
.../PowerPC/ppc-future-mma-builtin-err.c | 21 ++
...ppc-future-paired-vec-memops-builtin-err.c | 20 ++
.../test/CodeGen/PowerPC/ppc-mmaplus-types.c | 184 ++++++++++++++++++
.../test/CodeGenCXX/ppc-mangle-mma-types.cpp | 5 +
clang/test/Sema/ppc-pair-mma-types.c | 98 ++++++++++
.../TypeSystem/Clang/TypeSystemClang.cpp | 1 +
11 files changed, 447 insertions(+), 3 deletions(-)
create mode 100644 clang/test/CodeGen/PowerPC/builtins-ppc-mmaplus.c
create mode 100644 clang/test/CodeGen/PowerPC/ppc-future-mma-builtin-err.c
create mode 100644
clang/test/CodeGen/PowerPC/ppc-future-paired-vec-memops-builtin-err.c
create mode 100644 clang/test/CodeGen/PowerPC/ppc-mmaplus-types.c
diff --git a/clang/include/clang/Basic/BuiltinsPPC.def
b/clang/include/clang/Basic/BuiltinsPPC.def
index bb7d54bbb793e..099500754a0e0 100644
--- a/clang/include/clang/Basic/BuiltinsPPC.def
+++ b/clang/include/clang/Basic/BuiltinsPPC.def
@@ -1134,6 +1134,18 @@ UNALIASED_CUSTOM_BUILTIN(mma_pmxvbf16ger2np,
"vW512*VVi15i15i3", true,
"mma,paired-vector-memops")
UNALIASED_CUSTOM_BUILTIN(mma_pmxvbf16ger2nn, "vW512*VVi15i15i3", true,
"mma,paired-vector-memops")
+UNALIASED_CUSTOM_BUILTIN(mma_dmxvi8gerx4, "vW1024*W256V", false,
+ "mma,paired-vector-memops")
+UNALIASED_CUSTOM_BUILTIN(mma_pmdmxvi8gerx4, "vW1024*W256Vi255i15i15", false,
+ "mma,paired-vector-memops")
+UNALIASED_CUSTOM_BUILTIN(mma_dmxvi8gerx4pp, "vW1024*W256V", true,
+ "mma,paired-vector-memops")
+UNALIASED_CUSTOM_BUILTIN(mma_pmdmxvi8gerx4pp, "vW1024*W256Vi255i15i15", true,
+ "mma,paired-vector-memops")
+UNALIASED_CUSTOM_BUILTIN(mma_dmxvi8gerx4spp, "vW1024*W256V", true,
+ "mma,paired-vector-memops")
+UNALIASED_CUSTOM_BUILTIN(mma_pmdmxvi8gerx4spp, "vW1024*W256Vi255i15i15", true,
+ "mma,paired-vector-memops")
// FIXME: Obviously incomplete.
diff --git a/clang/include/clang/Basic/PPCTypes.def
b/clang/include/clang/Basic/PPCTypes.def
index 9e2cb2aedc9fc..cfc9de3a473d4 100644
--- a/clang/include/clang/Basic/PPCTypes.def
+++ b/clang/include/clang/Basic/PPCTypes.def
@@ -30,6 +30,7 @@
#endif
+PPC_VECTOR_MMA_TYPE(__dmr, VectorDmr, 1024)
PPC_VECTOR_MMA_TYPE(__vector_quad, VectorQuad, 512)
PPC_VECTOR_VSX_TYPE(__vector_pair, VectorPair, 256)
diff --git a/clang/lib/AST/ASTContext.cpp b/clang/lib/AST/ASTContext.cpp
index 45f9602856840..ffb4ca61b00c4 100644
--- a/clang/lib/AST/ASTContext.cpp
+++ b/clang/lib/AST/ASTContext.cpp
@@ -3455,6 +3455,7 @@ static void encodeTypeForFunctionPointerAuth(const
ASTContext &Ctx,
case BuiltinType::BFloat16:
case BuiltinType::VectorQuad:
case BuiltinType::VectorPair:
+ case BuiltinType::VectorDmr:
OS << "?";
return;
diff --git a/clang/test/AST/ast-dump-ppc-types.c
b/clang/test/AST/ast-dump-ppc-types.c
index 26ae5441f20d7..a430268284413 100644
--- a/clang/test/AST/ast-dump-ppc-types.c
+++ b/clang/test/AST/ast-dump-ppc-types.c
@@ -1,9 +1,11 @@
+// RUN: %clang_cc1 -triple powerpc64le-unknown-unknown -target-cpu future \
+// RUN: -ast-dump %s | FileCheck %s
// RUN: %clang_cc1 -triple powerpc64le-unknown-unknown -target-cpu pwr10 \
-// RUN: -ast-dump -ast-dump-filter __vector %s | FileCheck %s
+// RUN: -ast-dump %s | FileCheck %s
// RUN: %clang_cc1 -triple powerpc64le-unknown-unknown -target-cpu pwr9 \
-// RUN: -ast-dump -ast-dump-filter __vector %s | FileCheck %s
+// RUN: -ast-dump %s | FileCheck %s
// RUN: %clang_cc1 -triple powerpc64le-unknown-unknown -target-cpu pwr8 \
-// RUN: -ast-dump -ast-dump-filter __vector %s | FileCheck %s
+// RUN: -ast-dump %s | FileCheck %s
// RUN: %clang_cc1 -triple x86_64-unknown-unknown -ast-dump %s | FileCheck %s \
// RUN: --check-prefix=CHECK-X86_64
// RUN: %clang_cc1 -triple arm-unknown-unknown -ast-dump %s | FileCheck %s \
@@ -15,16 +17,21 @@
// are correctly defined. We also added checks on a couple of other targets to
// ensure the types are target-dependent.
+// CHECK: TypedefDecl {{.*}} implicit __dmr '__dmr'
+// CHECK: `-BuiltinType {{.*}} '__dmr'
// CHECK: TypedefDecl {{.*}} implicit __vector_quad '__vector_quad'
// CHECK-NEXT: -BuiltinType {{.*}} '__vector_quad'
// CHECK: TypedefDecl {{.*}} implicit __vector_pair '__vector_pair'
// CHECK-NEXT: -BuiltinType {{.*}} '__vector_pair'
+// CHECK-X86_64-NOT: __dmr
// CHECK-X86_64-NOT: __vector_quad
// CHECK-X86_64-NOT: __vector_pair
+// CHECK-ARM-NOT: __dmr
// CHECK-ARM-NOT: __vector_quad
// CHECK-ARM-NOT: __vector_pair
+// CHECK-RISCV64-NOT: __dmr
// CHECK-RISCV64-NOT: __vector_quad
// CHECK-RISCV64-NOT: __vector_pair
diff --git a/clang/test/CodeGen/PowerPC/builtins-ppc-mmaplus.c
b/clang/test/CodeGen/PowerPC/builtins-ppc-mmaplus.c
new file mode 100644
index 0000000000000..2c335218ed32a
--- /dev/null
+++ b/clang/test/CodeGen/PowerPC/builtins-ppc-mmaplus.c
@@ -0,0 +1,94 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// RUN: %clang_cc1 -O3 -triple powerpc64le-unknown-unknown -target-cpu future \
+// RUN: -emit-llvm %s -o - | FileCheck %s
+// RUN: %clang_cc1 -O3 -triple powerpc64-ibm-aix -target-cpu future \
+// RUN: -emit-llvm %s -o - | FileCheck %s
+
+
+// CHECK-LABEL: @test_dmxvi8gerx4(
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[TMP0:%.*]] = load <256 x i1>, ptr [[VPP:%.*]], align 32,
!tbaa [[TBAA2:![0-9]+]]
+// CHECK-NEXT: [[TMP1:%.*]] = tail call <1024 x i1>
@llvm.ppc.mma.dmxvi8gerx4(<256 x i1> [[TMP0]], <16 x i8> [[VC:%.*]])
+// CHECK-NEXT: store <1024 x i1> [[TMP1]], ptr [[RESP:%.*]], align 128,
!tbaa [[TBAA6:![0-9]+]]
+// CHECK-NEXT: ret void
+//
+void test_dmxvi8gerx4(unsigned char *vdmrp, unsigned char *vpp, vector
unsigned char vc, unsigned char *resp) {
+ __dmr vdmr = *((__dmr *)vdmrp);
+ __vector_pair vp = *((__vector_pair *)vpp);
+ __builtin_mma_dmxvi8gerx4(&vdmr, vp, vc);
+ *((__dmr *)resp) = vdmr;
+}
+
+// CHECK-LABEL: @test_pmdmxvi8gerx4(
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[TMP0:%.*]] = load <256 x i1>, ptr [[VPP:%.*]], align 32,
!tbaa [[TBAA2]]
+// CHECK-NEXT: [[TMP1:%.*]] = tail call <1024 x i1>
@llvm.ppc.mma.pmdmxvi8gerx4(<256 x i1> [[TMP0]], <16 x i8> [[VC:%.*]], i32 0,
i32 0, i32 0)
+// CHECK-NEXT: store <1024 x i1> [[TMP1]], ptr [[RESP:%.*]], align 128,
!tbaa [[TBAA6]]
+// CHECK-NEXT: ret void
+//
+void test_pmdmxvi8gerx4(unsigned char *vdmrp, unsigned char *vpp, vector
unsigned char vc, unsigned char *resp) {
+ __dmr vdmr = *((__dmr *)vdmrp);
+ __vector_pair vp = *((__vector_pair *)vpp);
+ __builtin_mma_pmdmxvi8gerx4(&vdmr, vp, vc, 0, 0, 0);
+ *((__dmr *)resp) = vdmr;
+}
+
+// CHECK-LABEL: @test_dmxvi8gerx4pp(
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[TMP0:%.*]] = load <1024 x i1>, ptr [[VDMRP:%.*]], align
128, !tbaa [[TBAA6]]
+// CHECK-NEXT: [[TMP1:%.*]] = load <256 x i1>, ptr [[VPP:%.*]], align 32,
!tbaa [[TBAA2]]
+// CHECK-NEXT: [[TMP2:%.*]] = tail call <1024 x i1>
@llvm.ppc.mma.dmxvi8gerx4pp(<1024 x i1> [[TMP0]], <256 x i1> [[TMP1]], <16 x
i8> [[VC:%.*]])
+// CHECK-NEXT: store <1024 x i1> [[TMP2]], ptr [[RESP:%.*]], align 128,
!tbaa [[TBAA6]]
+// CHECK-NEXT: ret void
+//
+void test_dmxvi8gerx4pp(unsigned char *vdmrp, unsigned char *vpp, vector
unsigned char vc, unsigned char *resp) {
+ __dmr vdmr = *((__dmr *)vdmrp);
+ __vector_pair vp = *((__vector_pair *)vpp);
+ __builtin_mma_dmxvi8gerx4pp(&vdmr, vp, vc);
+ *((__dmr *)resp) = vdmr;
+}
+
+// CHECK-LABEL: @test_pmdmxvi8gerx4pp(
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[TMP0:%.*]] = load <1024 x i1>, ptr [[VDMRP:%.*]], align
128, !tbaa [[TBAA6]]
+// CHECK-NEXT: [[TMP1:%.*]] = load <256 x i1>, ptr [[VPP:%.*]], align 32,
!tbaa [[TBAA2]]
+// CHECK-NEXT: [[TMP2:%.*]] = tail call <1024 x i1>
@llvm.ppc.mma.pmdmxvi8gerx4pp(<1024 x i1> [[TMP0]], <256 x i1> [[TMP1]], <16 x
i8> [[VC:%.*]], i32 0, i32 0, i32 0)
+// CHECK-NEXT: store <1024 x i1> [[TMP2]], ptr [[RESP:%.*]], align 128,
!tbaa [[TBAA6]]
+// CHECK-NEXT: ret void
+//
+void test_pmdmxvi8gerx4pp(unsigned char *vdmrp, unsigned char *vpp, vector
unsigned char vc, unsigned char *resp) {
+ __dmr vdmr = *((__dmr *)vdmrp);
+ __vector_pair vp = *((__vector_pair *)vpp);
+ __builtin_mma_pmdmxvi8gerx4pp(&vdmr, vp, vc, 0, 0, 0);
+ *((__dmr *)resp) = vdmr;
+}
+
+// CHECK-LABEL: @test_dmxvi8gerx4spp(
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[TMP0:%.*]] = load <1024 x i1>, ptr [[VDMRP:%.*]], align
128, !tbaa [[TBAA6]]
+// CHECK-NEXT: [[TMP1:%.*]] = load <256 x i1>, ptr [[VPP:%.*]], align 32,
!tbaa [[TBAA2]]
+// CHECK-NEXT: [[TMP2:%.*]] = tail call <1024 x i1>
@llvm.ppc.mma.dmxvi8gerx4spp(<1024 x i1> [[TMP0]], <256 x i1> [[TMP1]], <16 x
i8> [[VC:%.*]])
+// CHECK-NEXT: store <1024 x i1> [[TMP2]], ptr [[RESP:%.*]], align 128,
!tbaa [[TBAA6]]
+// CHECK-NEXT: ret void
+//
+void test_dmxvi8gerx4spp(unsigned char *vdmrp, unsigned char *vpp, vector
unsigned char vc, unsigned char *resp) {
+ __dmr vdmr = *((__dmr *)vdmrp);
+ __vector_pair vp = *((__vector_pair *)vpp);
+ __builtin_mma_dmxvi8gerx4spp(&vdmr, vp, vc);
+ *((__dmr *)resp) = vdmr;
+}
+
+// CHECK-LABEL: @test_pmdmxvi8gerx4spp(
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[TMP0:%.*]] = load <1024 x i1>, ptr [[VDMRP:%.*]], align
128, !tbaa [[TBAA6]]
+// CHECK-NEXT: [[TMP1:%.*]] = load <256 x i1>, ptr [[VPP:%.*]], align 32,
!tbaa [[TBAA2]]
+// CHECK-NEXT: [[TMP2:%.*]] = tail call <1024 x i1>
@llvm.ppc.mma.pmdmxvi8gerx4spp(<1024 x i1> [[TMP0]], <256 x i1> [[TMP1]], <16 x
i8> [[VC:%.*]], i32 0, i32 0, i32 0)
+// CHECK-NEXT: store <1024 x i1> [[TMP2]], ptr [[RESP:%.*]], align 128,
!tbaa [[TBAA6]]
+// CHECK-NEXT: ret void
+//
+void test_pmdmxvi8gerx4spp(unsigned char *vdmrp, unsigned char *vpp, vector
unsigned char vc, unsigned char *resp) {
+ __dmr vdmr = *((__dmr *)vdmrp);
+ __vector_pair vp = *((__vector_pair *)vpp);
+ __builtin_mma_pmdmxvi8gerx4spp(&vdmr, vp, vc, 0, 0, 0);
+ *((__dmr *)resp) = vdmr;
+}
diff --git a/clang/test/CodeGen/PowerPC/ppc-future-mma-builtin-err.c
b/clang/test/CodeGen/PowerPC/ppc-future-mma-builtin-err.c
new file mode 100644
index 0000000000000..c6029f9eb8352
--- /dev/null
+++ b/clang/test/CodeGen/PowerPC/ppc-future-mma-builtin-err.c
@@ -0,0 +1,21 @@
+// RUN: not %clang_cc1 -triple powerpc64le-unknown-linux-gnu -target-cpu
future \
+// RUN: %s -emit-llvm-only 2>&1 | FileCheck %s
+
+__attribute__((target("no-mma")))
+void test_mma(unsigned char *vdmrp, unsigned char *vpp, vector unsigned char
vc) {
+ __dmr vdmr = *((__dmr *)vdmrp);
+ __vector_pair vp = *((__vector_pair *)vpp);
+ __builtin_mma_dmxvi8gerx4(&vdmr, vp, vc);
+ __builtin_mma_pmdmxvi8gerx4(&vdmr, vp, vc, 0, 0, 0);
+ __builtin_mma_dmxvi8gerx4pp(&vdmr, vp, vc);
+ __builtin_mma_pmdmxvi8gerx4pp(&vdmr, vp, vc, 0, 0, 0);
+ __builtin_mma_dmxvi8gerx4spp(&vdmr, vp, vc);
+ __builtin_mma_pmdmxvi8gerx4spp(&vdmr, vp, vc, 0, 0, 0);
+
+// CHECK: error: '__builtin_mma_dmxvi8gerx4' needs target feature
mma,paired-vector-memops
+// CHECK: error: '__builtin_mma_pmdmxvi8gerx4' needs target feature
mma,paired-vector-memops
+// CHECK: error: '__builtin_mma_dmxvi8gerx4pp' needs target feature
mma,paired-vector-memops
+// CHECK: error: '__builtin_mma_pmdmxvi8gerx4pp' needs target feature
mma,paired-vector-memops
+// CHECK: error: '__builtin_mma_dmxvi8gerx4spp' needs target feature
mma,paired-vector-memops
+// CHECK: error: '__builtin_mma_pmdmxvi8gerx4spp' needs target feature
mma,paired-vector-memops
+}
diff --git
a/clang/test/CodeGen/PowerPC/ppc-future-paired-vec-memops-builtin-err.c
b/clang/test/CodeGen/PowerPC/ppc-future-paired-vec-memops-builtin-err.c
new file mode 100644
index 0000000000000..c31847e3ca4c4
--- /dev/null
+++ b/clang/test/CodeGen/PowerPC/ppc-future-paired-vec-memops-builtin-err.c
@@ -0,0 +1,20 @@
+// RUN: not %clang_cc1 -triple powerpc64le-unknown-linux-gnu -target-cpu
future \
+// RUN: %s -emit-llvm-only 2>&1 | FileCheck %s
+
+__attribute__((target("no-paired-vector-memops")))
+void test_pair(unsigned char *vdmr, unsigned char *vpp, vector unsigned char
vc) {
+ __vector_pair vp = *((__vector_pair *)vpp);
+ __builtin_mma_dmxvi8gerx4((__dmr *)vdmr, vp, vc);
+ __builtin_mma_pmdmxvi8gerx4((__dmr *)vdmr, vp, vc, 0, 0, 0);
+ __builtin_mma_dmxvi8gerx4pp((__dmr *)vdmr, vp, vc);
+ __builtin_mma_pmdmxvi8gerx4pp((__dmr *)vdmr, vp, vc, 0, 0, 0);
+ __builtin_mma_dmxvi8gerx4spp((__dmr *)vdmr, vp, vc);
+ __builtin_mma_pmdmxvi8gerx4spp((__dmr *)vdmr, vp, vc, 0, 0, 0);
+
+// CHECK: error: '__builtin_mma_dmxvi8gerx4' needs target feature
mma,paired-vector-memops
+// CHECK: error: '__builtin_mma_pmdmxvi8gerx4' needs target feature
mma,paired-vector-memops
+// CHECK: error: '__builtin_mma_dmxvi8gerx4pp' needs target feature
mma,paired-vector-memops
+// CHECK: error: '__builtin_mma_pmdmxvi8gerx4pp' needs target feature
mma,paired-vector-memops
+// CHECK: error: '__builtin_mma_dmxvi8gerx4spp' needs target feature
mma,paired-vector-memops
+// CHECK: error: '__builtin_mma_pmdmxvi8gerx4spp' needs target feature
mma,paired-vector-memops
+}
diff --git a/clang/test/CodeGen/PowerPC/ppc-mmaplus-types.c
b/clang/test/CodeGen/PowerPC/ppc-mmaplus-types.c
new file mode 100644
index 0000000000000..dbae2d0c0829a
--- /dev/null
+++ b/clang/test/CodeGen/PowerPC/ppc-mmaplus-types.c
@@ -0,0 +1,184 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// RUN: %clang_cc1 -triple powerpc64le-linux-unknown -target-cpu future \
+// RUN: -emit-llvm -o - %s | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc64le-linux-unknown -target-cpu pwr10 \
+// RUN: -emit-llvm -o - %s | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc64le-linux-unknown -target-cpu pwr9 \
+// RUN: -emit-llvm -o - %s | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc64le-linux-unknown -target-cpu pwr8 \
+// RUN: -emit-llvm -o - %s | FileCheck %s
+
+typedef __vector_quad vq_t;
+
+// CHECK-LABEL: @test_dmr_copy(
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[PTR1_ADDR:%.*]] = alloca ptr, align 8
+// CHECK-NEXT: [[PTR2_ADDR:%.*]] = alloca ptr, align 8
+// CHECK-NEXT: store ptr [[PTR1:%.*]], ptr [[PTR1_ADDR]], align 8
+// CHECK-NEXT: store ptr [[PTR2:%.*]], ptr [[PTR2_ADDR]], align 8
+// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[PTR1_ADDR]], align 8
+// CHECK-NEXT: [[ADD_PTR:%.*]] = getelementptr inbounds <1024 x i1>, ptr
[[TMP0]], i64 2
+// CHECK-NEXT: [[TMP1:%.*]] = load <1024 x i1>, ptr [[ADD_PTR]], align 128
+// CHECK-NEXT: [[TMP2:%.*]] = load ptr, ptr [[PTR2_ADDR]], align 8
+// CHECK-NEXT: [[ADD_PTR1:%.*]] = getelementptr inbounds <1024 x i1>, ptr
[[TMP2]], i64 1
+// CHECK-NEXT: store <1024 x i1> [[TMP1]], ptr [[ADD_PTR1]], align 128
+// CHECK-NEXT: ret void
+//
+void test_dmr_copy(__dmr *ptr1, __dmr *ptr2) {
+ *(ptr2 + 1) = *(ptr1 + 2);
+}
+
+// CHECK-LABEL: @test_dmr_typedef(
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[INP_ADDR:%.*]] = alloca ptr, align 8
+// CHECK-NEXT: [[OUTP_ADDR:%.*]] = alloca ptr, align 8
+// CHECK-NEXT: [[VDMRIN:%.*]] = alloca ptr, align 8
+// CHECK-NEXT: [[VDMROUT:%.*]] = alloca ptr, align 8
+// CHECK-NEXT: store ptr [[INP:%.*]], ptr [[INP_ADDR]], align 8
+// CHECK-NEXT: store ptr [[OUTP:%.*]], ptr [[OUTP_ADDR]], align 8
+// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[INP_ADDR]], align 8
+// CHECK-NEXT: store ptr [[TMP0]], ptr [[VDMRIN]], align 8
+// CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr [[OUTP_ADDR]], align 8
+// CHECK-NEXT: store ptr [[TMP1]], ptr [[VDMROUT]], align 8
+// CHECK-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VDMRIN]], align 8
+// CHECK-NEXT: [[TMP3:%.*]] = load <1024 x i1>, ptr [[TMP2]], align 128
+// CHECK-NEXT: [[TMP4:%.*]] = load ptr, ptr [[VDMROUT]], align 8
+// CHECK-NEXT: store <1024 x i1> [[TMP3]], ptr [[TMP4]], align 128
+// CHECK-NEXT: ret void
+//
+void test_dmr_typedef(int *inp, int *outp) {
+ __dmr *vdmrin = (__dmr *)inp;
+ __dmr *vdmrout = (__dmr *)outp;
+ *vdmrout = *vdmrin;
+}
+
+// CHECK-LABEL: @test_dmr_arg(
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[VDMR_ADDR:%.*]] = alloca ptr, align 8
+// CHECK-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 8
+// CHECK-NEXT: [[VDMRP:%.*]] = alloca ptr, align 8
+// CHECK-NEXT: store ptr [[VDMR:%.*]], ptr [[VDMR_ADDR]], align 8
+// CHECK-NEXT: store ptr [[PTR:%.*]], ptr [[PTR_ADDR]], align 8
+// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[PTR_ADDR]], align 8
+// CHECK-NEXT: store ptr [[TMP0]], ptr [[VDMRP]], align 8
+// CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr [[VDMR_ADDR]], align 8
+// CHECK-NEXT: [[TMP2:%.*]] = load <1024 x i1>, ptr [[TMP1]], align 128
+// CHECK-NEXT: [[TMP3:%.*]] = load ptr, ptr [[VDMRP]], align 8
+// CHECK-NEXT: store <1024 x i1> [[TMP2]], ptr [[TMP3]], align 128
+// CHECK-NEXT: ret void
+//
+void test_dmr_arg(__dmr *vdmr, int *ptr) {
+ __dmr *vdmrp = (__dmr *)ptr;
+ *vdmrp = *vdmr;
+}
+
+// CHECK-LABEL: @test_dmr_const_arg(
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[VDMR_ADDR:%.*]] = alloca ptr, align 8
+// CHECK-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 8
+// CHECK-NEXT: [[VDMRP:%.*]] = alloca ptr, align 8
+// CHECK-NEXT: store ptr [[VDMR:%.*]], ptr [[VDMR_ADDR]], align 8
+// CHECK-NEXT: store ptr [[PTR:%.*]], ptr [[PTR_ADDR]], align 8
+// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[PTR_ADDR]], align 8
+// CHECK-NEXT: store ptr [[TMP0]], ptr [[VDMRP]], align 8
+// CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr [[VDMR_ADDR]], align 8
+// CHECK-NEXT: [[TMP2:%.*]] = load <1024 x i1>, ptr [[TMP1]], align 128
+// CHECK-NEXT: [[TMP3:%.*]] = load ptr, ptr [[VDMRP]], align 8
+// CHECK-NEXT: store <1024 x i1> [[TMP2]], ptr [[TMP3]], align 128
+// CHECK-NEXT: ret void
+//
+void test_dmr_const_arg(const __dmr *const vdmr, int *ptr) {
+ __dmr *vdmrp = (__dmr *)ptr;
+ *vdmrp = *vdmr;
+}
+
+// CHECK-LABEL: @test_dmr_array_arg(
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[VDMRA_ADDR:%.*]] = alloca ptr, align 8
+// CHECK-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 8
+// CHECK-NEXT: [[VDMRP:%.*]] = alloca ptr, align 8
+// CHECK-NEXT: store ptr [[VDMRA:%.*]], ptr [[VDMRA_ADDR]], align 8
+// CHECK-NEXT: store ptr [[PTR:%.*]], ptr [[PTR_ADDR]], align 8
+// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[PTR_ADDR]], align 8
+// CHECK-NEXT: store ptr [[TMP0]], ptr [[VDMRP]], align 8
+// CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr [[VDMRA_ADDR]], align 8
+// CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds <1024 x i1>, ptr
[[TMP1]], i64 0
+// CHECK-NEXT: [[TMP2:%.*]] = load <1024 x i1>, ptr [[ARRAYIDX]], align 128
+// CHECK-NEXT: [[TMP3:%.*]] = load ptr, ptr [[VDMRP]], align 8
+// CHECK-NEXT: store <1024 x i1> [[TMP2]], ptr [[TMP3]], align 128
+// CHECK-NEXT: ret void
+//
+void test_dmr_array_arg(__dmr vdmra[], int *ptr) {
+ __dmr *vdmrp = (__dmr *)ptr;
+ *vdmrp = vdmra[0];
+}
+
+// CHECK-LABEL: @test_dmr_ret(
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 8
+// CHECK-NEXT: [[VDMRP:%.*]] = alloca ptr, align 8
+// CHECK-NEXT: store ptr [[PTR:%.*]], ptr [[PTR_ADDR]], align 8
+// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[PTR_ADDR]], align 8
+// CHECK-NEXT: store ptr [[TMP0]], ptr [[VDMRP]], align 8
+// CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr [[VDMRP]], align 8
+// CHECK-NEXT: [[ADD_PTR:%.*]] = getelementptr inbounds <1024 x i1>, ptr
[[TMP1]], i64 2
+// CHECK-NEXT: ret ptr [[ADD_PTR]]
+//
+__dmr *test_dmr_ret(int *ptr) {
+ __dmr *vdmrp = (__dmr *)ptr;
+ return vdmrp + 2;
+}
+
+// CHECK-LABEL: @test_dmr_ret_const(
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 8
+// CHECK-NEXT: [[VDMRP:%.*]] = alloca ptr, align 8
+// CHECK-NEXT: store ptr [[PTR:%.*]], ptr [[PTR_ADDR]], align 8
+// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[PTR_ADDR]], align 8
+// CHECK-NEXT: store ptr [[TMP0]], ptr [[VDMRP]], align 8
+// CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr [[VDMRP]], align 8
+// CHECK-NEXT: [[ADD_PTR:%.*]] = getelementptr inbounds <1024 x i1>, ptr
[[TMP1]], i64 2
+// CHECK-NEXT: ret ptr [[ADD_PTR]]
+//
+const __dmr *test_dmr_ret_const(int *ptr) {
+ __dmr *vdmrp = (__dmr *)ptr;
+ return vdmrp + 2;
+}
+
+// CHECK-LABEL: @test_dmr_sizeof_alignof(
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 8
+// CHECK-NEXT: [[VDMRP:%.*]] = alloca ptr, align 8
+// CHECK-NEXT: [[VDMR:%.*]] = alloca <1024 x i1>, align 128
+// CHECK-NEXT: [[SIZET:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[ALIGNT:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[SIZEV:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[ALIGNV:%.*]] = alloca i32, align 4
+// CHECK-NEXT: store ptr [[PTR:%.*]], ptr [[PTR_ADDR]], align 8
+// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[PTR_ADDR]], align 8
+// CHECK-NEXT: store ptr [[TMP0]], ptr [[VDMRP]], align 8
+// CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr [[VDMRP]], align 8
+// CHECK-NEXT: [[TMP2:%.*]] = load <1024 x i1>, ptr [[TMP1]], align 128
+// CHECK-NEXT: store <1024 x i1> [[TMP2]], ptr [[VDMR]], align 128
+// CHECK-NEXT: store i32 128, ptr [[SIZET]], align 4
+// CHECK-NEXT: store i32 128, ptr [[ALIGNT]], align 4
+// CHECK-NEXT: store i32 128, ptr [[SIZEV]], align 4
+// CHECK-NEXT: store i32 128, ptr [[ALIGNV]], align 4
+// CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr [[SIZET]], align 4
+// CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[ALIGNT]], align 4
+// CHECK-NEXT: [[ADD:%.*]] = add i32 [[TMP3]], [[TMP4]]
+// CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr [[SIZEV]], align 4
+// CHECK-NEXT: [[ADD1:%.*]] = add i32 [[ADD]], [[TMP5]]
+// CHECK-NEXT: [[TMP6:%.*]] = load i32, ptr [[ALIGNV]], align 4
+// CHECK-NEXT: [[ADD2:%.*]] = add i32 [[ADD1]], [[TMP6]]
+// CHECK-NEXT: ret i32 [[ADD2]]
+//
+int test_dmr_sizeof_alignof(int *ptr) {
+ __dmr *vdmrp = (__dmr *)ptr;
+ __dmr vdmr = *vdmrp;
+ unsigned sizet = sizeof(__dmr);
+ unsigned alignt = __alignof__(__dmr);
+ unsigned sizev = sizeof(vdmr);
+ unsigned alignv = __alignof__(vdmr);
+ return sizet + alignt + sizev + alignv;
+}
diff --git a/clang/test/CodeGenCXX/ppc-mangle-mma-types.cpp
b/clang/test/CodeGenCXX/ppc-mangle-mma-types.cpp
index 74e50ceea386b..786d8dd19859c 100644
--- a/clang/test/CodeGenCXX/ppc-mangle-mma-types.cpp
+++ b/clang/test/CodeGenCXX/ppc-mangle-mma-types.cpp
@@ -1,3 +1,5 @@
+// RUN: %clang_cc1 -triple powerpc64le-linux-unknown -target-cpu future %s \
+// RUN: -emit-llvm -o - | FileCheck %s
// RUN: %clang_cc1 -triple powerpc64le-linux-unknown -target-cpu pwr10 %s \
// RUN: -emit-llvm -o - | FileCheck %s
// RUN: %clang_cc1 -triple powerpc64le-linux-unknown -target-cpu pwr9 %s \
@@ -5,6 +7,9 @@
// RUN: %clang_cc1 -triple powerpc64le-linux-unknown -target-cpu pwr8 %s \
// RUN: -emit-llvm -o - | FileCheck %s
+// CHECK: _Z2f0Pu5__dmr
+void f0(__dmr *vdmr) {}
+
// CHECK: _Z2f1Pu13__vector_quad
void f1(__vector_quad *vq) {}
diff --git a/clang/test/Sema/ppc-pair-mma-types.c
b/clang/test/Sema/ppc-pair-mma-types.c
index 6a7cfac031058..950e9d1ea0b35 100644
--- a/clang/test/Sema/ppc-pair-mma-types.c
+++ b/clang/test/Sema/ppc-pair-mma-types.c
@@ -2,12 +2,110 @@
// RUN: -target-cpu pwr10 %s -verify
// RUN: %clang_cc1 -triple powerpc64-unknown-unknown -fsyntax-only \
// RUN: -target-cpu pwr10 %s -verify
+// RUN: %clang_cc1 -triple powerpc64le-unknown-unknown -fsyntax-only \
+// RUN: -target-cpu future %s -verify
+// RUN: %clang_cc1 -triple powerpc64-unknown-unknown -fsyntax-only \
+// RUN: -target-cpu future %s -verify
// The use of PPC MMA types is strongly restricted. Non-pointer MMA variables
// can only be declared in functions and a limited number of operations are
// supported on these types. This test case checks that invalid uses of MMA
// types are correctly prevented.
+// vector dmr
+
+// typedef
+typedef __dmr dmr_t;
+
+// function argument
+void testDmrArg1(__dmr vdmr, int *ptr) { // expected-error {{invalid use of
PPC MMA type}}
+ __dmr *vdmrp = (__dmr *)ptr;
+ *vdmrp = vdmr;
+}
+
+void testDmrArg2(const __dmr vdmr, int *ptr) { // expected-error {{invalid use
of PPC MMA type}}
+ __dmr *vdmrp = (__dmr *)ptr;
+ *vdmrp = vdmr;
+}
+
+void testDmrArg3(const dmr_t vdmr, int *ptr) { // expected-error {{invalid use
of PPC MMA type}}
+ __dmr *vdmrp = (__dmr *)ptr;
+ *vdmrp = vdmr;
+}
+
+// function return
+__dmr testDmrRet1(int *ptr) { // expected-error {{invalid use of PPC MMA type}}
+ __dmr *vdmrp = (__dmr *)ptr;
+ return *vdmrp; // expected-error {{invalid use of PPC MMA type}}
+}
+
+const dmr_t testDmrRet4(int *ptr) { // expected-error {{invalid use of PPC MMA
type}}
+ __dmr *vdmrp = (__dmr *)ptr;
+ return *vdmrp; // expected-error {{invalid use of PPC MMA type}}
+}
+
+// global
+__dmr globalvdmr; // expected-error {{invalid use of PPC MMA type}}
+const __dmr globalvdmr2; // expected-error {{invalid use of PPC MMA type}}
+__dmr *globalvdmrp;
+const __dmr *const globalvdmrp2;
+dmr_t globalvdmr_t; // expected-error {{invalid use of PPC MMA type}}
+
+// struct field
+struct TestDmrStruct {
+ int a;
+ float b;
+ __dmr c; // expected-error {{invalid use of PPC MMA type}}
+ __dmr *vq;
+};
+
+// operators
+int testDmrOperators1(int *ptr) {
+ __dmr *vdmrp = (__dmr *)ptr;
+ __dmr vdmr1 = *(vdmrp + 0);
+ __dmr vdmr2 = *(vdmrp + 1);
+ __dmr vdmr3 = *(vdmrp + 2);
+ if (vdmr1) // expected-error {{statement requires expression of scalar type
('__dmr' invalid)}}
+ *(vdmrp + 10) = vdmr1;
+ if (!vdmr2) // expected-error {{invalid argument type '__dmr' to unary
expression}}
+ *(vdmrp + 11) = vdmr3;
+ int c1 = vdmr1 && vdmr2; // expected-error {{invalid operands to binary
expression ('__dmr' and '__dmr')}}
+ int c2 = vdmr2 == vdmr3; // expected-error {{invalid operands to binary
expression ('__dmr' and '__dmr')}}
+ int c3 = vdmr2 < vdmr1; // expected-error {{invalid operands to binary
expression ('__dmr' and '__dmr')}}
+ return c1 || c2 || c3;
+}
+
+void testDmrOperators2(int *ptr) {
+ __dmr *vdmrp = (__dmr *)ptr;
+ __dmr vdmr1 = *(vdmrp + 0);
+ __dmr vdmr2 = *(vdmrp + 1);
+ __dmr vdmr3 = *(vdmrp + 2);
+ vdmr1 = -vdmr1; // expected-error {{invalid argument type '__dmr' to
unary expression}}
+ vdmr2 = vdmr1 + vdmr3; // expected-error {{invalid operands to binary
expression ('__dmr' and '__dmr')}}
+ vdmr2 = vdmr2 * vdmr3; // expected-error {{invalid operands to binary
expression ('__dmr' and '__dmr')}}
+ vdmr3 = vdmr3 | vdmr3; // expected-error {{invalid operands to binary
expression ('__dmr' and '__dmr')}}
+ vdmr3 = vdmr3 << 2; // expected-error {{invalid operands to binary
expression ('__dmr' and 'int')}}
+ *(vdmrp + 10) = vdmr1;
+ *(vdmrp + 11) = vdmr2;
+ *(vdmrp + 12) = vdmr3;
+}
+
+vector unsigned char testDmrOperators3(int *ptr) {
+ __dmr *vdmrp = (__dmr *)ptr;
+ __dmr vdmr1 = *(vdmrp + 0);
+ __dmr vdmr2 = *(vdmrp + 1);
+ __dmr vdmr3 = *(vdmrp + 2);
+ vdmr1 ? *(vdmrp + 10) = vdmr2 : *(vdmrp + 11) = vdmr3; // expected-error
{{used type '__dmr' where arithmetic or pointer type is required}}
+ vdmr2 = vdmr3;
+ return vdmr2[1]; // expected-error {{subscripted value is not an array,
pointer, or vector}}
+}
+
+void testDmrOperators4(int v, void *ptr) {
+ __dmr *vdmrp = (__dmr *)ptr;
+ __dmr vdmr1 = (__dmr)v; // expected-error {{used type '__dmr' where
arithmetic or pointer type is required}}
+ __dmr vdmr2 = (__dmr)vdmrp; // expected-error {{used type '__dmr' where
arithmetic or pointer type is required}}
+}
+
// vector quad
// typedef
diff --git a/lldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.cpp
b/lldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.cpp
index 68bb3dc8581eb..5762709769784 100644
--- a/lldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.cpp
+++ b/lldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.cpp
@@ -5027,6 +5027,7 @@ lldb::Encoding
TypeSystemClang::GetEncoding(lldb::opaque_compiler_type_t type,
// PowerPC -- Matrix Multiply Assist
case clang::BuiltinType::VectorPair:
case clang::BuiltinType::VectorQuad:
+ case clang::BuiltinType::VectorDmr:
break;
// ARM -- Scalable Vector Extension
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