Author: Kiva Date: 2025-05-16T14:20:53+08:00 New Revision: af083d09bd1815bd50f2efb9f999bec145a564b1
URL: https://github.com/llvm/llvm-project/commit/af083d09bd1815bd50f2efb9f999bec145a564b1 DIFF: https://github.com/llvm/llvm-project/commit/af083d09bd1815bd50f2efb9f999bec145a564b1.diff LOG: [RISCV] Add `zihintpause` LLVM/Clang intrinsic (#139519) This PR adds the missing intrinsic `__builtin_riscv_pause` for the zihintpause extension. Spec: https://five-embeddev.com/riscv-user-isa-manual/Priv-v1.12/zihintpause.html Fixes #129961 Added: clang/test/CodeGen/RISCV/riscv-zihintpause.c llvm/test/CodeGen/RISCV/riscv-zihintpause.ll Modified: clang/docs/ReleaseNotes.rst clang/include/clang/Basic/BuiltinsRISCV.td clang/lib/CodeGen/TargetBuiltins/RISCV.cpp llvm/include/llvm/IR/IntrinsicsRISCV.td llvm/lib/Target/RISCV/RISCVInstrInfo.td Removed: ################################################################################ diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst index 4e5875c043cf2..cfe2a0277b226 100644 --- a/clang/docs/ReleaseNotes.rst +++ b/clang/docs/ReleaseNotes.rst @@ -830,6 +830,8 @@ RISC-V Support - `Zicsr` / `Zifencei` are allowed to be duplicated in the presence of `g` in `-march`. +- Add support for the `__builtin_riscv_pause()` intrinsic from the `Zihintpause` extension. + CUDA/HIP Language Changes ^^^^^^^^^^^^^^^^^^^^^^^^^ diff --git a/clang/include/clang/Basic/BuiltinsRISCV.td b/clang/include/clang/Basic/BuiltinsRISCV.td index 3263603a8a1cf..b2cd5648e008f 100644 --- a/clang/include/clang/Basic/BuiltinsRISCV.td +++ b/clang/include/clang/Basic/BuiltinsRISCV.td @@ -147,6 +147,12 @@ def ntl_load : RISCVBuiltin<"void(...)">; def ntl_store : RISCVBuiltin<"void(...)">; } // Features = "zihintntl", Attributes = [CustomTypeChecking] +//===----------------------------------------------------------------------===// +// Zihintpause extension. +//===----------------------------------------------------------------------===// +let Features = "zihintpause", Attributes = [NoThrow] in +def pause : RISCVBuiltin<"void()">; + //===----------------------------------------------------------------------===// // XCV extensions. //===----------------------------------------------------------------------===// diff --git a/clang/lib/CodeGen/TargetBuiltins/RISCV.cpp b/clang/lib/CodeGen/TargetBuiltins/RISCV.cpp index 3335239b0b6c2..0cd4f3c935e92 100644 --- a/clang/lib/CodeGen/TargetBuiltins/RISCV.cpp +++ b/clang/lib/CodeGen/TargetBuiltins/RISCV.cpp @@ -357,6 +357,12 @@ Value *CodeGenFunction::EmitRISCVBuiltinExpr(unsigned BuiltinID, return Store; } + // Zihintpause + case RISCV::BI__builtin_riscv_pause: { + llvm::Function *Fn = CGM.getIntrinsic(llvm::Intrinsic::riscv_pause); + return Builder.CreateCall(Fn, {}); + } + // XCValu case RISCV::BI__builtin_riscv_cv_alu_addN: ID = Intrinsic::riscv_cv_alu_addN; diff --git a/clang/test/CodeGen/RISCV/riscv-zihintpause.c b/clang/test/CodeGen/RISCV/riscv-zihintpause.c new file mode 100644 index 0000000000000..2e1369f3f6e0c --- /dev/null +++ b/clang/test/CodeGen/RISCV/riscv-zihintpause.c @@ -0,0 +1,14 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py +// RUN: %clang_cc1 -triple riscv32 -target-feature +zihintpause -emit-llvm %s -o - \ +// RUN: | FileCheck %s +// RUN: %clang_cc1 -triple riscv64 -target-feature +zihintpause -emit-llvm %s -o - \ +// RUN: | FileCheck %s + +// CHECK-LABEL: @test_builtin_pause( +// CHECK-NEXT: entry: +// CHECK-NEXT: call void @llvm.riscv.pause() +// CHECK-NEXT: ret void +// +void test_builtin_pause() { + __builtin_riscv_pause(); +} diff --git a/llvm/include/llvm/IR/IntrinsicsRISCV.td b/llvm/include/llvm/IR/IntrinsicsRISCV.td index 75fb41fcd381a..622a96cafb128 100644 --- a/llvm/include/llvm/IR/IntrinsicsRISCV.td +++ b/llvm/include/llvm/IR/IntrinsicsRISCV.td @@ -1886,6 +1886,11 @@ let TargetPrefix = "riscv" in { def int_riscv_vsm3me : RISCVBinaryAAXUnMasked; } // TargetPrefix = "riscv" +// Zihintpause extensions +//===----------------------------------------------------------------------===// +let TargetPrefix = "riscv" in +def int_riscv_pause : DefaultAttrsIntrinsic<[], [], [IntrNoMem, IntrHasSideEffects]>; + // Vendor extensions //===----------------------------------------------------------------------===// include "llvm/IR/IntrinsicsRISCVXTHead.td" diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td index aaeb4fd363f57..ef054120d5443 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td @@ -2198,6 +2198,14 @@ def : Pat<(binop_allwusers<add> GPR:$rs1, immop_oneuse<AddiPair>:$rs2), def : Pat<(i64 (add GPR:$rs1, negImm:$rs2)), (SUB GPR:$rs1, negImm:$rs2)>; } +//===----------------------------------------------------------------------===// +// Zihintpause +//===----------------------------------------------------------------------===// + +// Zihintpause +let Predicates = [HasStdExtZihintpause] in +def : Pat<(int_riscv_pause), (FENCE 0x1, 0x0)>; + //===----------------------------------------------------------------------===// // Standard extensions //===----------------------------------------------------------------------===// diff --git a/llvm/test/CodeGen/RISCV/riscv-zihintpause.ll b/llvm/test/CodeGen/RISCV/riscv-zihintpause.ll new file mode 100644 index 0000000000000..6c6f5e20a8b48 --- /dev/null +++ b/llvm/test/CodeGen/RISCV/riscv-zihintpause.ll @@ -0,0 +1,14 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -mtriple=riscv64 -mattr=+zihintpause -verify-machineinstrs < %s \ +; RUN: | FileCheck %s -check-prefix=RVPAUSE + +declare void @llvm.riscv.pause() + +define void @test_pause() { +; RVPAUSE-LABEL: test_pause: +; RVPAUSE: # %bb.0: +; RVPAUSE-NEXT: pause +; RVPAUSE-NEXT: ret + call void @llvm.riscv.pause() + ret void +} _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
