https://github.com/T-Tie created https://github.com/llvm/llvm-project/pull/136694
Support for Ziccamoc is added in this pr. Specification link:[https://drive.google.com/file/d/12QKRm92cLcEk8-5J9NI91m0fAQOxqNAq/view](url) >From c7fabb64f6690de12f9dbffa16ef4d74ed2b3ae9 Mon Sep 17 00:00:00 2001 From: Tie <t...@llvm.com> Date: Tue, 22 Apr 2025 12:25:32 +0000 Subject: [PATCH] Add Support for Ziccamoc --- clang/test/Preprocessor/riscv-target-features.c | 10 ++++++++++ llvm/docs/RISCVUsage.rst | 3 ++- llvm/lib/Target/RISCV/RISCVFeatures.td | 3 +++ llvm/test/CodeGen/RISCV/attributes.ll | 2 ++ llvm/test/MC/RISCV/attribute-arch.s | 3 +++ llvm/unittests/TargetParser/RISCVISAInfoTest.cpp | 1 + 6 files changed, 21 insertions(+), 1 deletion(-) diff --git a/clang/test/Preprocessor/riscv-target-features.c b/clang/test/Preprocessor/riscv-target-features.c index 253e42419f453..a58beb81c2ef5 100644 --- a/clang/test/Preprocessor/riscv-target-features.c +++ b/clang/test/Preprocessor/riscv-target-features.c @@ -124,6 +124,7 @@ // CHECK-NOT: __riscv_zicbop {{.*$}} // CHECK-NOT: __riscv_zicboz {{.*$}} // CHECK-NOT: __riscv_ziccamoa {{.*$}} +// CHECK-NOT: __riscv_ziccamoc {{.*$}} // CHECK-NOT: __riscv_ziccif {{.*$}} // CHECK-NOT: __riscv_zicclsm {{.*$}} // CHECK-NOT: __riscv_ziccrse {{.*$}} @@ -1046,6 +1047,15 @@ // RUN: -o - | FileCheck --check-prefix=CHECK-ZICCAMOA-EXT %s // CHECK-ZICCAMOA-EXT: __riscv_ziccamoa 1000000{{$}} +// RUN: %clang --target=riscv32-unknown-linux-gnu \ +// RUN: -march=rv32iziccamoc -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-ZICCAMOC-EXT %s +// CHECK-ZICCAMOC-EXT: __riscv_ziccamoc 1000000{{$}} +// RUN: %clang --target=riscv64-unknown-linux-gnu \ +// RUN: -march=rv64iziccamoc -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-ZICCAMOC-EXT %s +// CHECK-ZICCAMOC-EXT: __riscv_ziccamoc 1000000{{$}} + // RUN: %clang --target=riscv32-unknown-linux-gnu \ // RUN: -march=rv32iziccif -E -dM %s \ // RUN: -o - | FileCheck --check-prefix=CHECK-ZICCIF-EXT %s diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst index 137b537f00ea0..2338082fbb0d5 100644 --- a/llvm/docs/RISCVUsage.rst +++ b/llvm/docs/RISCVUsage.rst @@ -196,6 +196,7 @@ on support follow. ``Zicbop`` Supported ``Zicboz`` Assembly Support ``Ziccamoa`` Supported (`See note <#riscv-profiles-extensions-note>`__) + ``Ziccamoc`` Supported (`See note <#riscv-profiles-extensions-note>`__) ``Ziccif`` Supported (`See note <#riscv-profiles-extensions-note>`__) ``Zicclsm`` Supported (`See note <#riscv-profiles-extensions-note>`__) ``Ziccrse`` Supported (`See note <#riscv-profiles-extensions-note>`__) @@ -297,7 +298,7 @@ Supported .. _riscv-profiles-extensions-note: -``Za128rs``, ``Za64rs``, ``Zama16b``, ``Zic64b``, ``Ziccamoa``, ``Ziccif``, ``Zicclsm``, ``Ziccrse``, ``Shcounterenvw``, ``Shgatpa``, ``Shtvala``, ``Shvsatpa``, ``Shvstvala``, ``Shvstvecd``, ``Ssccptr``, ``Sscounterenw``, ``Ssstateen``, ``Ssstrict``, ``Sstvala``, ``Sstvecd``, ``Ssu64xl``, ``Svade``, ``Svbare`` +``Za128rs``, ``Za64rs``, ``Zama16b``, ``Zic64b``, ``Ziccamoa``, ``Ziccamoc``, ``Ziccif``, ``Zicclsm``, ``Ziccrse``, ``Shcounterenvw``, ``Shgatpa``, ``Shtvala``, ``Shvsatpa``, ``Shvstvala``, ``Shvstvecd``, ``Ssccptr``, ``Sscounterenw``, ``Ssstateen``, ``Ssstrict``, ``Sstvala``, ``Sstvecd``, ``Ssu64xl``, ``Svade``, ``Svbare`` These extensions are defined as part of the `RISC-V Profiles specification <https://github.com/riscv/riscv-profiles/releases/tag/v1.0>`__. They do not introduce any new features themselves, but instead describe existing hardware features. .. _riscv-zacas-note: diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td index f51fcf82077f4..894fcd245e6a0 100644 --- a/llvm/lib/Target/RISCV/RISCVFeatures.td +++ b/llvm/lib/Target/RISCV/RISCVFeatures.td @@ -102,6 +102,9 @@ def HasStdExtZicboz : Predicate<"Subtarget->hasStdExtZicboz()">, def FeatureStdExtZiccamoa : RISCVExtension<1, 0, "Main Memory Supports All Atomics in A">; +def FeatureStdExtZiccamoc + : RISCVExtension<1, 0, "Main memory supports atomics in Zacas">; + def FeatureStdExtZiccif : RISCVExtension<1, 0, "Main Memory Supports Instruction Fetch with Atomicity Requirement">; diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll index 4bb3eb81f3dfb..b9171e190f092 100644 --- a/llvm/test/CodeGen/RISCV/attributes.ll +++ b/llvm/test/CodeGen/RISCV/attributes.ll @@ -264,6 +264,7 @@ ; RUN: llc -mtriple=riscv64 -mattr=+zcmp %s -o - | FileCheck --check-prefixes=CHECK,RV64ZCMP %s ; RUN: llc -mtriple=riscv64 -mattr=+zcmt %s -o - | FileCheck --check-prefixes=CHECK,RV64ZCMT %s ; RUN: llc -mtriple=riscv64 -mattr=+ziccamoa %s -o - | FileCheck --check-prefixes=CHECK,RV64ZICCAMOA %s +; RUN: llc -mtriple=riscv64 -mattr=+ziccamoc %s -o - | FileCheck --check-prefixes=CHECK,RV64ZICCAMOC %s ; RUN: llc -mtriple=riscv64 -mattr=+ziccif %s -o - | FileCheck --check-prefixes=CHECK,RV64ZICCIF %s ; RUN: llc -mtriple=riscv64 -mattr=+zicclsm %s -o - | FileCheck --check-prefixes=CHECK,RV64ZICCLSM %s ; RUN: llc -mtriple=riscv64 -mattr=+ziccrse %s -o - | FileCheck --check-prefixes=CHECK,RV64ZICCRSE %s @@ -599,6 +600,7 @@ ; RV64ZCMP: .attribute 5, "rv64i2p1_zca1p0_zcmp1p0" ; RV64ZCMT: .attribute 5, "rv64i2p1_zicsr2p0_zca1p0_zcmt1p0" ; RV64ZICCAMOA: .attribute 5, "rv64i2p1_ziccamoa1p0" +; RV64ZICCAMOC: .attribute 5, "rv64i2p1_ziccamoc1p0" ; RV64ZICCIF: .attribute 5, "rv64i2p1_ziccif1p0" ; RV64ZICCLSM: .attribute 5, "rv64i2p1_zicclsm1p0" ; RV64ZICCRSE: .attribute 5, "rv64i2p1_ziccrse1p0" diff --git a/llvm/test/MC/RISCV/attribute-arch.s b/llvm/test/MC/RISCV/attribute-arch.s index 8edd6800a125f..d8b23596d62c4 100644 --- a/llvm/test/MC/RISCV/attribute-arch.s +++ b/llvm/test/MC/RISCV/attribute-arch.s @@ -106,6 +106,9 @@ .attribute arch, "rv32iziccamoa" # CHECK: attribute 5, "rv32i2p1_ziccamoa1p0" +.attribute arch, "rv32iziccamoc" +# CHECK: attribute 5, "rv32i2p1_ziccamoc1p0" + .attribute arch, "rv32iziccif" # CHECK: attribute 5, "rv32i2p1_ziccif1p0" diff --git a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp index ff0a5e64ab3e1..e851ba280a7e4 100644 --- a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp +++ b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp @@ -972,6 +972,7 @@ R"(All available -march extensions for RISC-V zicbop 1.0 zicboz 1.0 ziccamoa 1.0 + ziccamoc 1.0 ziccif 1.0 zicclsm 1.0 ziccrse 1.0 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
