================
@@ -12,22 +16,307 @@ void b0(int a, int b) {
x = x | b;
}
-// CHECK: %{{.+}} = cir.binop(mul, %{{.+}}, %{{.+}}) nsw : !s32i
-// CHECK: %{{.+}} = cir.binop(div, %{{.+}}, %{{.+}}) : !s32i
-// CHECK: %{{.+}} = cir.binop(rem, %{{.+}}, %{{.+}}) : !s32i
-// CHECK: %{{.+}} = cir.binop(add, %{{.+}}, %{{.+}}) nsw : !s32i
-// CHECK: %{{.+}} = cir.binop(sub, %{{.+}}, %{{.+}}) nsw : !s32i
-// CHECK: %{{.+}} = cir.binop(and, %{{.+}}, %{{.+}}) : !s32i
-// CHECK: %{{.+}} = cir.binop(xor, %{{.+}}, %{{.+}}) : !s32i
-// CHECK: %{{.+}} = cir.binop(or, %{{.+}}, %{{.+}}) : !s32i
+// CIR-LABEL: cir.func @b0(
+// CIR: %{{.+}} = cir.binop(mul, %{{.+}}, %{{.+}}) nsw : !s32i
+// CIR: %{{.+}} = cir.binop(div, %{{.+}}, %{{.+}}) : !s32i
+// CIR: %{{.+}} = cir.binop(rem, %{{.+}}, %{{.+}}) : !s32i
+// CIR: %{{.+}} = cir.binop(add, %{{.+}}, %{{.+}}) nsw : !s32i
+// CIR: %{{.+}} = cir.binop(sub, %{{.+}}, %{{.+}}) nsw : !s32i
+// CIR: %{{.+}} = cir.binop(and, %{{.+}}, %{{.+}}) : !s32i
+// CIR: %{{.+}} = cir.binop(xor, %{{.+}}, %{{.+}}) : !s32i
+// CIR: %{{.+}} = cir.binop(or, %{{.+}}, %{{.+}}) : !s32i
+// CIR: cir.return
+
+// LLVM-LABEL: define void @b0(
+// LLVM-SAME: i32 %[[A:.*]], i32 %[[B:.*]])
+// LLVM: %[[A_ADDR:.*]] = alloca i32
+// LLVM: %[[B_ADDR:.*]] = alloca i32
+// LLVM: %[[X:.*]] = alloca i32
+// LLVM: store i32 %[[A]], ptr %[[A_ADDR]]
+// LLVM: store i32 %[[B]], ptr %[[B_ADDR]]
+
+// LLVM: %[[A:.*]] = load i32, ptr %[[A_ADDR]]
+// LLVM: %[[B:.*]] = load i32, ptr %[[B_ADDR]]
+// LLVM: %[[MUL:.*]] = mul nsw i32 %[[A]], %[[B]]
+// LLVM: store i32 %[[MUL]], ptr %[[X]]
+
+// LLVM: %[[X1:.*]] = load i32, ptr %[[X]]
+// LLVM: %[[B1:.*]] = load i32, ptr %[[B_ADDR]]
+// LLVM: %[[DIV:.*]] = sdiv i32 %[[X1]], %[[B1]]
+// LLVM: store i32 %[[DIV]], ptr %[[X]]
+
+// LLVM: %[[X2:.*]] = load i32, ptr %[[X]]
+// LLVM: %[[B2:.*]] = load i32, ptr %[[B_ADDR]]
+// LLVM: %[[REM:.*]] = srem i32 %[[X2]], %[[B2]]
+// LLVM: store i32 %[[REM]], ptr %[[X]]
+
+// LLVM: %[[X3:.*]] = load i32, ptr %[[X]]
+// LLVM: %[[B3:.*]] = load i32, ptr %[[B_ADDR]]
+// LLVM: %[[ADD:.*]] = add nsw i32 %[[X3]], %[[B3]]
+// LLVM: store i32 %[[ADD]], ptr %[[X]]
+
+// LLVM: %[[X4:.*]] = load i32, ptr %[[X]]
+// LLVM: %[[B4:.*]] = load i32, ptr %[[B_ADDR]]
+// LLVM: %[[SUB:.*]] = sub nsw i32 %[[X4]], %[[B4]]
+// LLVM: store i32 %[[SUB]], ptr %[[X]]
+
+// LLVM: %[[X5:.*]] = load i32, ptr %[[X]]
+// LLVM: %[[B5:.*]] = load i32, ptr %[[B_ADDR]]
+// LLVM: %[[AND:.*]] = and i32 %[[X5]], %[[B5]]
+// LLVM: store i32 %[[AND]], ptr %[[X]]
+
+// LLVM: %[[X6:.*]] = load i32, ptr %[[X]]
+// LLVM: %[[B6:.*]] = load i32, ptr %[[B_ADDR]]
+// LLVM: %[[XOR:.*]] = xor i32 %[[X6]], %[[B6]]
+// LLVM: store i32 %[[XOR]], ptr %[[X]]
+
+// LLVM: %[[X7:.*]] = load i32, ptr %[[X]]
+// LLVM: %[[B7:.*]] = load i32, ptr %[[B_ADDR]]
+// LLVM: %[[OR:.*]] = or i32 %[[X7]], %[[B7]]
+// LLVM: store i32 %[[OR]], ptr %[[X]]
+
+// LLVM: ret void
+
+// OGCG-LABEL: define dso_local void @_Z2b0ii(i32 {{.*}} %a, i32 {{.*}} %b)
{{.*}} {
+// OGCG: %[[A_ADDR:.*]] = alloca i32
+// OGCG: %[[B_ADDR:.*]] = alloca i32
+// OGCG: %[[X:.*]] = alloca i32
+// OGCG: store i32 %a, ptr %[[A_ADDR]]
+// OGCG: store i32 %b, ptr %[[B_ADDR]]
+
+// OGCG: %[[A:.*]] = load i32, ptr %[[A_ADDR]]
+// OGCG: %[[B:.*]] = load i32, ptr %[[B_ADDR]]
+// OGCG: %[[MUL:.*]] = mul nsw i32 %[[A]], %[[B]]
+// OGCG: store i32 %[[MUL]], ptr %[[X]]
+
+// OGCG: %[[X1:.*]] = load i32, ptr %[[X]]
+// OGCG: %[[B1:.*]] = load i32, ptr %[[B_ADDR]]
+// OGCG: %[[DIV:.*]] = sdiv i32 %[[X1]], %[[B1]]
+// OGCG: store i32 %[[DIV]], ptr %[[X]]
+
+// OGCG: %[[X2:.*]] = load i32, ptr %[[X]]
+// OGCG: %[[B2:.*]] = load i32, ptr %[[B_ADDR]]
+// OGCG: %[[REM:.*]] = srem i32 %[[X2]], %[[B2]]
+// OGCG: store i32 %[[REM]], ptr %[[X]]
+
+// OGCG: %[[X3:.*]] = load i32, ptr %[[X]]
+// OGCG: %[[B3:.*]] = load i32, ptr %[[B_ADDR]]
+// OGCG: %[[ADD:.*]] = add nsw i32 %[[X3]], %[[B3]]
+// OGCG: store i32 %[[ADD]], ptr %[[X]]
+
+// OGCG: %[[X4:.*]] = load i32, ptr %[[X]]
+// OGCG: %[[B4:.*]] = load i32, ptr %[[B_ADDR]]
+// OGCG: %[[SUB:.*]] = sub nsw i32 %[[X4]], %[[B4]]
+// OGCG: store i32 %[[SUB]], ptr %[[X]]
+
+// OGCG: %[[X5:.*]] = load i32, ptr %[[X]]
+// OGCG: %[[B5:.*]] = load i32, ptr %[[B_ADDR]]
+// OGCG: %[[AND:.*]] = and i32 %[[X5]], %[[B5]]
+// OGCG: store i32 %[[AND]], ptr %[[X]]
+
+// OGCG: %[[X6:.*]] = load i32, ptr %[[X]]
+// OGCG: %[[B6:.*]] = load i32, ptr %[[B_ADDR]]
+// OGCG: %[[XOR:.*]] = xor i32 %[[X6]], %[[B6]]
+// OGCG: store i32 %[[XOR]], ptr %[[X]]
+
+// OGCG: %[[X7:.*]] = load i32, ptr %[[X]]
+// OGCG: %[[B7:.*]] = load i32, ptr %[[B_ADDR]]
+// OGCG: %[[OR:.*]] = or i32 %[[X7]], %[[B7]]
+// OGCG: store i32 %[[OR]], ptr %[[X]]
+
+// OGCG: ret void
void testFloatingPointBinOps(float a, float b) {
a * b;
- // CHECK: cir.binop(mul, %{{.+}}, %{{.+}}) : !cir.float
a / b;
- // CHECK: cir.binop(div, %{{.+}}, %{{.+}}) : !cir.float
a + b;
- // CHECK: cir.binop(add, %{{.+}}, %{{.+}}) : !cir.float
a - b;
- // CHECK: cir.binop(sub, %{{.+}}, %{{.+}}) : !cir.float
}
+
+// CIR-LABEL: cir.func @testFloatingPointBinOps(
+// CIR: cir.binop(mul, %{{.+}}, %{{.+}}) : !cir.float
+// CIR: cir.binop(div, %{{.+}}, %{{.+}}) : !cir.float
+// CIR: cir.binop(add, %{{.+}}, %{{.+}}) : !cir.float
+// CIR: cir.binop(sub, %{{.+}}, %{{.+}}) : !cir.float
+// CIR: cir.return
+
+// LLVM-LABEL: define void @testFloatingPointBinOps(
+// LLVM-SAME: float %[[A:.*]], float %[[B:.*]])
+// LLVM: %[[A_ADDR:.*]] = alloca float, i64 1
+// LLVM: %[[B_ADDR:.*]] = alloca float, i64 1
+// LLVM: store float %[[A]], ptr %[[A_ADDR]]
+// LLVM: store float %[[B]], ptr %[[B_ADDR]]
+
+// LLVM: %[[A1:.*]] = load float, ptr %[[A_ADDR]]
+// LLVM: %[[B1:.*]] = load float, ptr %[[B_ADDR]]
+// LLVM: fmul float %[[A1]], %[[B1]]
+
+// LLVM: %[[A2:.*]] = load float, ptr %[[A_ADDR]]
+// LLVM: %[[B2:.*]] = load float, ptr %[[B_ADDR]]
+// LLVM: fdiv float %[[A2]], %[[B2]]
+
+// LLVM: %[[A3:.*]] = load float, ptr %[[A_ADDR]]
+// LLVM: %[[B3:.*]] = load float, ptr %[[B_ADDR]]
+// LLVM: fadd float %[[A3]], %[[B3]]
+
+// LLVM: %[[A4:.*]] = load float, ptr %[[A_ADDR]]
+// LLVM: %[[B4:.*]] = load float, ptr %[[B_ADDR]]
+// LLVM: fsub float %[[A4]], %[[B4]]
+
+// LLVM: ret void
+
+// OGCG-LABEL: define dso_local void @_Z23testFloatingPointBinOpsff(float
{{.*}} %a, float {{.*}} %b)
+// OGCG: %a.addr = alloca float
+// OGCG: %b.addr = alloca float
+// OGCG: store float %a, ptr %a.addr
+// OGCG: store float %b, ptr %b.addr
+
+// OGCG: %[[A1:.*]] = load float, ptr %a.addr
+// OGCG: %[[B1:.*]] = load float, ptr %b.addr
+// OGCG: fmul float %[[A1]], %[[B1]]
+
+// OGCG: %[[A2:.*]] = load float, ptr %a.addr
+// OGCG: %[[B2:.*]] = load float, ptr %b.addr
+// OGCG: fdiv float %[[A2]], %[[B2]]
+
+// OGCG: %[[A3:.*]] = load float, ptr %a.addr
+// OGCG: %[[B3:.*]] = load float, ptr %b.addr
+// OGCG: fadd float %[[A3]], %[[B3]]
+
+// OGCG: %[[A4:.*]] = load float, ptr %a.addr
+// OGCG: %[[B4:.*]] = load float, ptr %b.addr
+// OGCG: fsub float %[[A4]], %[[B4]]
+
+// OGCG: ret void
+
+void signed_shift(int a, int b) {
----------------
andykaylor wrote:
Can you add cases where the shift value needs `zext` and `sext`?
https://github.com/llvm/llvm-project/pull/133405
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