Author: Craig Topper Date: 2025-03-24T09:46:51-07:00 New Revision: 2b82555ef44c158c2bd1c26176ac2b5b953817a2
URL: https://github.com/llvm/llvm-project/commit/2b82555ef44c158c2bd1c26176ac2b5b953817a2 DIFF: https://github.com/llvm/llvm-project/commit/2b82555ef44c158c2bd1c26176ac2b5b953817a2.diff LOG: [RISCV] Remove experimental from Sdext and Sdtrig which are ratified. (#132529) They were ratified in February 2025. Added: Modified: clang/test/Driver/print-supported-extensions-riscv.c llvm/lib/Target/RISCV/RISCVFeatures.td llvm/test/CodeGen/RISCV/attributes.ll llvm/test/CodeGen/RISCV/features-info.ll llvm/unittests/TargetParser/RISCVISAInfoTest.cpp Removed: ################################################################################ diff --git a/clang/test/Driver/print-supported-extensions-riscv.c b/clang/test/Driver/print-supported-extensions-riscv.c index b5533b54347b9..7e201b1149ec3 100644 --- a/clang/test/Driver/print-supported-extensions-riscv.c +++ b/clang/test/Driver/print-supported-extensions-riscv.c @@ -112,6 +112,8 @@ // CHECK-NEXT: zvl8192b 1.0 'Zvl8192b' (Minimum Vector Length 8192) // CHECK-NEXT: zhinx 1.0 'Zhinx' (Half Float in Integer) // CHECK-NEXT: zhinxmin 1.0 'Zhinxmin' (Half Float in Integer Minimal) +// CHECK-NEXT: sdext 1.0 'Sdext' (External debugger) +// CHECK-NEXT: sdtrig 1.0 'Sdtrig' (Debugger triggers) // CHECK-NEXT: sha 1.0 'Sha' (Augmented Hypervisor) // CHECK-NEXT: shcounterenw 1.0 'Shcounterenw' (Support writeable hcounteren enable bit for any hpmcounter that is not read-only zero) // CHECK-NEXT: shgatpa 1.0 'Shgatpa' (SvNNx4 mode supported for all modes supported by satp, as well as Bare) @@ -191,8 +193,6 @@ // CHECK-NEXT: zvbc32e 0.7 'Zvbc32e' (Vector Carryless Multiplication with 32-bits elements) // CHECK-NEXT: zvkgs 0.7 'Zvkgs' (Vector-Scalar GCM instructions for Cryptography) // CHECK-NEXT: zvqdotq 0.0 'Zvqdotq' (Vector quad widening 4D Dot Product) -// CHECK-NEXT: sdext 1.0 'Sdext' (External debugger) -// CHECK-NEXT: sdtrig 1.0 'Sdtrig' (Debugger triggers) // CHECK-NEXT: smctr 1.0 'Smctr' (Control Transfer Records Machine Level) // CHECK-NEXT: ssctr 1.0 'Ssctr' (Control Transfer Records Supervisor Level) // CHECK-NEXT: svukte 0.3 'Svukte' (Address-Independent Latency of User-Mode Faults to Supervisor Addresses) diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td index 85e3675beb80e..5ed3ed917aa4c 100644 --- a/llvm/lib/Target/RISCV/RISCVFeatures.td +++ b/llvm/lib/Target/RISCV/RISCVFeatures.td @@ -869,9 +869,9 @@ def HasStdExtH : Predicate<"Subtarget->hasStdExtH()">, // Supervisor extensions -def FeatureStdExtSdext : RISCVExperimentalExtension<1, 0, "External debugger">; +def FeatureStdExtSdext : RISCVExtension<1, 0, "External debugger">; -def FeatureStdExtSdtrig : RISCVExperimentalExtension<1, 0, "Debugger triggers">; +def FeatureStdExtSdtrig : RISCVExtension<1, 0, "Debugger triggers">; def FeatureStdExtShgatpa : RISCVExtension<1, 0, diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll index b1793233339de..6d85e6c60d708 100644 --- a/llvm/test/CodeGen/RISCV/attributes.ll +++ b/llvm/test/CodeGen/RISCV/attributes.ll @@ -316,8 +316,8 @@ ; RUN: llc -mtriple=riscv64 -mattr=+supm %s -o - | FileCheck --check-prefix=RV64SUPM %s ; RUN: llc -mtriple=riscv64 -mattr=+experimental-smctr %s -o - | FileCheck --check-prefix=RV64SMCTR %s ; RUN: llc -mtriple=riscv64 -mattr=+experimental-ssctr %s -o - | FileCheck --check-prefix=RV64SSCTR %s -; RUN: llc -mtriple=riscv64 -mattr=+experimental-sdext %s -o - | FileCheck --check-prefix=RV64SDEXT %s -; RUN: llc -mtriple=riscv64 -mattr=+experimental-sdtrig %s -o - | FileCheck --check-prefix=RV64SDTRIG %s +; RUN: llc -mtriple=riscv64 -mattr=+sdext %s -o - | FileCheck --check-prefix=RV64SDEXT %s +; RUN: llc -mtriple=riscv64 -mattr=+sdtrig %s -o - | FileCheck --check-prefix=RV64SDTRIG %s ; RUN: llc -mtriple=riscv64 -mattr=+experimental-xqccmp %s -o - | FileCheck --check-prefix=RV64XQCCMP %s diff --git a/llvm/test/CodeGen/RISCV/features-info.ll b/llvm/test/CodeGen/RISCV/features-info.ll index 659201bf6d672..e8b46b8d78523 100644 --- a/llvm/test/CodeGen/RISCV/features-info.ll +++ b/llvm/test/CodeGen/RISCV/features-info.ll @@ -17,8 +17,6 @@ ; CHECK-NEXT: experimental - Experimental intrinsics. ; CHECK-NEXT: experimental-p - 'P' ('Base P' (Packed SIMD)). ; CHECK-NEXT: experimental-rvm23u32 - RISC-V experimental-rvm23u32 profile. -; CHECK-NEXT: experimental-sdext - 'Sdext' (External debugger). -; CHECK-NEXT: experimental-sdtrig - 'Sdtrig' (Debugger triggers). ; CHECK-NEXT: experimental-smctr - 'Smctr' (Control Transfer Records Machine Level). ; CHECK-NEXT: experimental-ssctr - 'Ssctr' (Control Transfer Records Supervisor Level). ; CHECK-NEXT: experimental-svukte - 'Svukte' (Address-Independent Latency of User-Mode Faults to Supervisor Addresses). @@ -115,6 +113,8 @@ ; CHECK-NEXT: rvi20u32 - RISC-V rvi20u32 profile. ; CHECK-NEXT: rvi20u64 - RISC-V rvi20u64 profile. ; CHECK-NEXT: save-restore - Enable save/restore.. +; CHECK-NEXT: sdext - 'Sdext' (External debugger). +; CHECK-NEXT: sdtrig - 'Sdtrig' (Debugger triggers). ; CHECK-NEXT: sha - 'Sha' (Augmented Hypervisor). ; CHECK-NEXT: shcounterenw - 'Shcounterenw' (Support writeable hcounteren enable bit for any hpmcounter that is not read-only zero). ; CHECK-NEXT: shgatpa - 'Shgatpa' (SvNNx4 mode supported for all modes supported by satp, as well as Bare). diff --git a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp index cf510995afa07..b3808a3511d96 100644 --- a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp +++ b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp @@ -1065,6 +1065,8 @@ R"(All available -march extensions for RISC-V zvl8192b 1.0 zhinx 1.0 zhinxmin 1.0 + sdext 1.0 + sdtrig 1.0 sha 1.0 shcounterenw 1.0 shgatpa 1.0 @@ -1144,8 +1146,6 @@ Experimental extensions zvbc32e 0.7 zvkgs 0.7 zvqdotq 0.0 - sdext 1.0 - sdtrig 1.0 smctr 1.0 ssctr 1.0 svukte 0.3 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
