Author: Alexandros Lamprineas Date: 2025-03-24T11:39:51Z New Revision: bf2d30e0927b6b137bf4cc7bf32cd74d8092b0ee
URL: https://github.com/llvm/llvm-project/commit/bf2d30e0927b6b137bf4cc7bf32cd74d8092b0ee DIFF: https://github.com/llvm/llvm-project/commit/bf2d30e0927b6b137bf4cc7bf32cd74d8092b0ee.diff LOG: [NFC][FMV][AArch64] Tidy up codegen tests. (#132273) Removes attr-target-version.c which doesn't have a clear purpose. Introduces AArch64/fmv-detection.c to check detection bitmasks. Adds coverage in AArch64/fmv-resolver-emission.c Added: clang/test/CodeGen/AArch64/fmv-detection.c Modified: clang/test/CodeGen/AArch64/fmv-mix-explicit-implicit-default.c clang/test/CodeGen/AArch64/fmv-resolver-emission.c Removed: clang/test/CodeGen/attr-target-version.c ################################################################################ diff --git a/clang/test/CodeGen/AArch64/fmv-detection.c b/clang/test/CodeGen/AArch64/fmv-detection.c new file mode 100644 index 0000000000000..56de8136e55dd --- /dev/null +++ b/clang/test/CodeGen/AArch64/fmv-detection.c @@ -0,0 +1,801 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --check-attributes --check-globals --include-generated-funcs --global-value-regex ".*" + +// Test all of the AArch64 feature detection bitmasks in the resolver. +// Use -target-feature +fp-armv8 on the command line to show that features +// specified on cmd are not exempt from runtime detection. + +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -emit-llvm -o - %s | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +fp-armv8 -emit-llvm -o - %s | FileCheck %s + +__attribute__((target_clones("aes", "bf16"))) int fmv(void) { return 0; } + +__attribute__((target_version("bti"))) int fmv(void) { return 0; } + +__attribute__((target_version("crc"))) int fmv(void) { return 0; } + +__attribute__((target_version("dit"))) int fmv(void) { return 0; } + +__attribute__((target_version("dotprod"))) int fmv(void) { return 0; } + +__attribute__((target_version("dpb"))) int fmv(void) { return 0; } + +__attribute__((target_version("dpb2"))) int fmv(void) { return 0; } + +__attribute__((target_version("f32mm"))) int fmv(void) { return 0; } + +__attribute__((target_version("f64mm"))) int fmv(void) { return 0; } + +__attribute__((target_version("fcma"))) int fmv(void) { return 0; } + +__attribute__((target_version("flagm"))) int fmv(void) { return 0; } + +__attribute__((target_version("flagm2"))) int fmv(void) { return 0; } + +__attribute__((target_version("fp"))) int fmv(void) { return 0; } + +__attribute__((target_version("fp16"))) int fmv(void) { return 0; } + +__attribute__((target_version("fp16fml"))) int fmv(void) { return 0; } + +__attribute__((target_version("frintts"))) int fmv(void) { return 0; } + +__attribute__((target_version("i8mm"))) int fmv(void) { return 0; } + +__attribute__((target_version("jscvt"))) int fmv(void) { return 0; } + +__attribute__((target_version("lse"))) int fmv(void) { return 0; } + +__attribute__((target_version("memtag"))) int fmv(void) { return 0; } + +__attribute__((target_version("mops"))) int fmv(void) { return 0; } + +__attribute__((target_version("rcpc"))) int fmv(void) { return 0; } + +__attribute__((target_version("rcpc2"))) int fmv(void) { return 0; } + +__attribute__((target_version("rcpc3"))) int fmv(void) { return 0; } + +__attribute__((target_version("rdm"))) int fmv(void) { return 0; } + +__attribute__((target_version("rng"))) int fmv(void) { return 0; } + +__attribute__((target_version("sb"))) int fmv(void) { return 0; } + +__attribute__((target_version("sha2"))) int fmv(void) { return 0; } + +__attribute__((target_version("sha3"))) int fmv(void) { return 0; } + +__attribute__((target_version("simd"))) int fmv(void) { return 0; } + +__attribute__((target_version("sm4"))) int fmv(void) { return 0; } + +__attribute__((target_version("sme"))) int fmv(void) { return 0; } + +__attribute__((target_version("sme-f64f64"))) int fmv(void) { return 0; } + +__attribute__((target_version("sme-i16i64"))) int fmv(void) { return 0; } + +__attribute__((target_version("sme2"))) int fmv(void) { return 0; } + +__attribute__((target_version("ssbs"))) int fmv(void) { return 0; } + +__attribute__((target_version("sve"))) int fmv(void) { return 0; } + +__attribute__((target_version("sve2"))) int fmv(void) { return 0; } + +__attribute__((target_version("sve2-aes"))) int fmv(void) { return 0; } + +__attribute__((target_version("sve2-bitperm"))) int fmv(void) { return 0; } + +__attribute__((target_version("sve2-sha3"))) int fmv(void) { return 0; } + +__attribute__((target_version("sve2-sm4"))) int fmv(void) { return 0; } + +__attribute__((target_version("wfxt"))) int fmv(void) { return 0; } + +// Test a version with multiple features. [Hint] Use the highest priority +// feature so that the version remains at the top of the resolver body. +__attribute__((target_version("mops+fp"))) int fmv(void); + +__attribute__((target_version("default"))) int fmv(void); + +int caller() { + return fmv(); +} + +//. +// CHECK: @__aarch64_cpu_features = external dso_local global { i64 } +// CHECK: @fmv = weak_odr ifunc i32 (), ptr @fmv.resolver +//. +// CHECK: Function Attrs: noinline nounwind optnone +// CHECK-LABEL: define {{[^@]+}}@fmv._Maes +// CHECK-SAME: () #[[ATTR0:[0-9]+]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: ret i32 0 +// +// +// CHECK: Function Attrs: noinline nounwind optnone +// CHECK-LABEL: define {{[^@]+}}@fmv._Mbf16 +// CHECK-SAME: () #[[ATTR1:[0-9]+]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: ret i32 0 +// +// +// CHECK-LABEL: define {{[^@]+}}@fmv.resolver() comdat { +// CHECK-NEXT: resolver_entry: +// CHECK-NEXT: call void @__init_cpu_features_resolver() +// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 +// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 576460752303423744 +// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 576460752303423744 +// CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]] +// CHECK-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]] +// CHECK: resolver_return: +// CHECK-NEXT: ret ptr @fmv._MfpMmops +// CHECK: resolver_else: +// CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 +// CHECK-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 576460752303423488 +// CHECK-NEXT: [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 576460752303423488 +// CHECK-NEXT: [[TMP7:%.*]] = and i1 true, [[TMP6]] +// CHECK-NEXT: br i1 [[TMP7]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]] +// CHECK: resolver_return1: +// CHECK-NEXT: ret ptr @fmv._Mmops +// CHECK: resolver_else2: +// CHECK-NEXT: [[TMP8:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 +// CHECK-NEXT: [[TMP9:%.*]] = and i64 [[TMP8]], 144119586256651008 +// CHECK-NEXT: [[TMP10:%.*]] = icmp eq i64 [[TMP9]], 144119586256651008 +// CHECK-NEXT: [[TMP11:%.*]] = and i1 true, [[TMP10]] +// CHECK-NEXT: br i1 [[TMP11]], label [[RESOLVER_RETURN3:%.*]], label [[RESOLVER_ELSE4:%.*]] +// CHECK: resolver_return3: +// CHECK-NEXT: ret ptr @fmv._Msme2 +// CHECK: resolver_else4: +// CHECK-NEXT: [[TMP12:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 +// CHECK-NEXT: [[TMP13:%.*]] = and i64 [[TMP12]], 72061992218723072 +// CHECK-NEXT: [[TMP14:%.*]] = icmp eq i64 [[TMP13]], 72061992218723072 +// CHECK-NEXT: [[TMP15:%.*]] = and i1 true, [[TMP14]] +// CHECK-NEXT: br i1 [[TMP15]], label [[RESOLVER_RETURN5:%.*]], label [[RESOLVER_ELSE6:%.*]] +// CHECK: resolver_return5: +// CHECK-NEXT: ret ptr @fmv._Msme-i16i64 +// CHECK: resolver_else6: +// CHECK-NEXT: [[TMP16:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 +// CHECK-NEXT: [[TMP17:%.*]] = and i64 [[TMP16]], 36033195199759104 +// CHECK-NEXT: [[TMP18:%.*]] = icmp eq i64 [[TMP17]], 36033195199759104 +// CHECK-NEXT: [[TMP19:%.*]] = and i1 true, [[TMP18]] +// CHECK-NEXT: br i1 [[TMP19]], label [[RESOLVER_RETURN7:%.*]], label [[RESOLVER_ELSE8:%.*]] +// CHECK: resolver_return7: +// CHECK-NEXT: ret ptr @fmv._Msme-f64f64 +// CHECK: resolver_else8: +// CHECK-NEXT: [[TMP20:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 +// CHECK-NEXT: [[TMP21:%.*]] = and i64 [[TMP20]], 18014398509481984 +// CHECK-NEXT: [[TMP22:%.*]] = icmp eq i64 [[TMP21]], 18014398509481984 +// CHECK-NEXT: [[TMP23:%.*]] = and i1 true, [[TMP22]] +// CHECK-NEXT: br i1 [[TMP23]], label [[RESOLVER_RETURN9:%.*]], label [[RESOLVER_ELSE10:%.*]] +// CHECK: resolver_return9: +// CHECK-NEXT: ret ptr @fmv._Mwfxt +// CHECK: resolver_else10: +// CHECK-NEXT: [[TMP24:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 +// CHECK-NEXT: [[TMP25:%.*]] = and i64 [[TMP24]], 1125899906842624 +// CHECK-NEXT: [[TMP26:%.*]] = icmp eq i64 [[TMP25]], 1125899906842624 +// CHECK-NEXT: [[TMP27:%.*]] = and i1 true, [[TMP26]] +// CHECK-NEXT: br i1 [[TMP27]], label [[RESOLVER_RETURN11:%.*]], label [[RESOLVER_ELSE12:%.*]] +// CHECK: resolver_return11: +// CHECK-NEXT: ret ptr @fmv._Mbti +// CHECK: resolver_else12: +// CHECK-NEXT: [[TMP28:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 +// CHECK-NEXT: [[TMP29:%.*]] = and i64 [[TMP28]], 562949953421312 +// CHECK-NEXT: [[TMP30:%.*]] = icmp eq i64 [[TMP29]], 562949953421312 +// CHECK-NEXT: [[TMP31:%.*]] = and i1 true, [[TMP30]] +// CHECK-NEXT: br i1 [[TMP31]], label [[RESOLVER_RETURN13:%.*]], label [[RESOLVER_ELSE14:%.*]] +// CHECK: resolver_return13: +// CHECK-NEXT: ret ptr @fmv._Mssbs +// CHECK: resolver_else14: +// CHECK-NEXT: [[TMP32:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 +// CHECK-NEXT: [[TMP33:%.*]] = and i64 [[TMP32]], 70368744177664 +// CHECK-NEXT: [[TMP34:%.*]] = icmp eq i64 [[TMP33]], 70368744177664 +// CHECK-NEXT: [[TMP35:%.*]] = and i1 true, [[TMP34]] +// CHECK-NEXT: br i1 [[TMP35]], label [[RESOLVER_RETURN15:%.*]], label [[RESOLVER_ELSE16:%.*]] +// CHECK: resolver_return15: +// CHECK-NEXT: ret ptr @fmv._Msb +// CHECK: resolver_else16: +// CHECK-NEXT: [[TMP36:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 +// CHECK-NEXT: [[TMP37:%.*]] = and i64 [[TMP36]], 17592186044416 +// CHECK-NEXT: [[TMP38:%.*]] = icmp eq i64 [[TMP37]], 17592186044416 +// CHECK-NEXT: [[TMP39:%.*]] = and i1 true, [[TMP38]] +// CHECK-NEXT: br i1 [[TMP39]], label [[RESOLVER_RETURN17:%.*]], label [[RESOLVER_ELSE18:%.*]] +// CHECK: resolver_return17: +// CHECK-NEXT: ret ptr @fmv._Mmemtag +// CHECK: resolver_else18: +// CHECK-NEXT: [[TMP40:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 +// CHECK-NEXT: [[TMP41:%.*]] = and i64 [[TMP40]], 4398180795136 +// CHECK-NEXT: [[TMP42:%.*]] = icmp eq i64 [[TMP41]], 4398180795136 +// CHECK-NEXT: [[TMP43:%.*]] = and i1 true, [[TMP42]] +// CHECK-NEXT: br i1 [[TMP43]], label [[RESOLVER_RETURN19:%.*]], label [[RESOLVER_ELSE20:%.*]] +// CHECK: resolver_return19: +// CHECK-NEXT: ret ptr @fmv._Msme +// CHECK: resolver_else20: +// CHECK-NEXT: [[TMP44:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 +// CHECK-NEXT: [[TMP45:%.*]] = and i64 [[TMP44]], 2268816540448 +// CHECK-NEXT: [[TMP46:%.*]] = icmp eq i64 [[TMP45]], 2268816540448 +// CHECK-NEXT: [[TMP47:%.*]] = and i1 true, [[TMP46]] +// CHECK-NEXT: br i1 [[TMP47]], label [[RESOLVER_RETURN21:%.*]], label [[RESOLVER_ELSE22:%.*]] +// CHECK: resolver_return21: +// CHECK-NEXT: ret ptr @fmv._Msve2-sm4 +// CHECK: resolver_else22: +// CHECK-NEXT: [[TMP48:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 +// CHECK-NEXT: [[TMP49:%.*]] = and i64 [[TMP48]], 1169304924928 +// CHECK-NEXT: [[TMP50:%.*]] = icmp eq i64 [[TMP49]], 1169304924928 +// CHECK-NEXT: [[TMP51:%.*]] = and i1 true, [[TMP50]] +// CHECK-NEXT: br i1 [[TMP51]], label [[RESOLVER_RETURN23:%.*]], label [[RESOLVER_ELSE24:%.*]] +// CHECK: resolver_return23: +// CHECK-NEXT: ret ptr @fmv._Msve2-sha3 +// CHECK: resolver_else24: +// CHECK-NEXT: [[TMP52:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 +// CHECK-NEXT: [[TMP53:%.*]] = and i64 [[TMP52]], 619549098240 +// CHECK-NEXT: [[TMP54:%.*]] = icmp eq i64 [[TMP53]], 619549098240 +// CHECK-NEXT: [[TMP55:%.*]] = and i1 true, [[TMP54]] +// CHECK-NEXT: br i1 [[TMP55]], label [[RESOLVER_RETURN25:%.*]], label [[RESOLVER_ELSE26:%.*]] +// CHECK: resolver_return25: +// CHECK-NEXT: ret ptr @fmv._Msve2-bitperm +// CHECK: resolver_else26: +// CHECK-NEXT: [[TMP56:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 +// CHECK-NEXT: [[TMP57:%.*]] = and i64 [[TMP56]], 344671224576 +// CHECK-NEXT: [[TMP58:%.*]] = icmp eq i64 [[TMP57]], 344671224576 +// CHECK-NEXT: [[TMP59:%.*]] = and i1 true, [[TMP58]] +// CHECK-NEXT: br i1 [[TMP59]], label [[RESOLVER_RETURN27:%.*]], label [[RESOLVER_ELSE28:%.*]] +// CHECK: resolver_return27: +// CHECK-NEXT: ret ptr @fmv._Msve2-aes +// CHECK: resolver_else28: +// CHECK-NEXT: [[TMP60:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 +// CHECK-NEXT: [[TMP61:%.*]] = and i64 [[TMP60]], 69793284352 +// CHECK-NEXT: [[TMP62:%.*]] = icmp eq i64 [[TMP61]], 69793284352 +// CHECK-NEXT: [[TMP63:%.*]] = and i1 true, [[TMP62]] +// CHECK-NEXT: br i1 [[TMP63]], label [[RESOLVER_RETURN29:%.*]], label [[RESOLVER_ELSE30:%.*]] +// CHECK: resolver_return29: +// CHECK-NEXT: ret ptr @fmv._Msve2 +// CHECK: resolver_else30: +// CHECK-NEXT: [[TMP64:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 +// CHECK-NEXT: [[TMP65:%.*]] = and i64 [[TMP64]], 35433545984 +// CHECK-NEXT: [[TMP66:%.*]] = icmp eq i64 [[TMP65]], 35433545984 +// CHECK-NEXT: [[TMP67:%.*]] = and i1 true, [[TMP66]] +// CHECK-NEXT: br i1 [[TMP67]], label [[RESOLVER_RETURN31:%.*]], label [[RESOLVER_ELSE32:%.*]] +// CHECK: resolver_return31: +// CHECK-NEXT: ret ptr @fmv._Mf64mm +// CHECK: resolver_else32: +// CHECK-NEXT: [[TMP68:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 +// CHECK-NEXT: [[TMP69:%.*]] = and i64 [[TMP68]], 18253676800 +// CHECK-NEXT: [[TMP70:%.*]] = icmp eq i64 [[TMP69]], 18253676800 +// CHECK-NEXT: [[TMP71:%.*]] = and i1 true, [[TMP70]] +// CHECK-NEXT: br i1 [[TMP71]], label [[RESOLVER_RETURN33:%.*]], label [[RESOLVER_ELSE34:%.*]] +// CHECK: resolver_return33: +// CHECK-NEXT: ret ptr @fmv._Mf32mm +// CHECK: resolver_else34: +// CHECK-NEXT: [[TMP72:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 +// CHECK-NEXT: [[TMP73:%.*]] = and i64 [[TMP72]], 1073807616 +// CHECK-NEXT: [[TMP74:%.*]] = icmp eq i64 [[TMP73]], 1073807616 +// CHECK-NEXT: [[TMP75:%.*]] = and i1 true, [[TMP74]] +// CHECK-NEXT: br i1 [[TMP75]], label [[RESOLVER_RETURN35:%.*]], label [[RESOLVER_ELSE36:%.*]] +// CHECK: resolver_return35: +// CHECK-NEXT: ret ptr @fmv._Msve +// CHECK: resolver_else36: +// CHECK-NEXT: [[TMP76:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 +// CHECK-NEXT: [[TMP77:%.*]] = and i64 [[TMP76]], 134218496 +// CHECK-NEXT: [[TMP78:%.*]] = icmp eq i64 [[TMP77]], 134218496 +// CHECK-NEXT: [[TMP79:%.*]] = and i1 true, [[TMP78]] +// CHECK-NEXT: br i1 [[TMP79]], label [[RESOLVER_RETURN37:%.*]], label [[RESOLVER_ELSE38:%.*]] +// CHECK: resolver_return37: +// CHECK-NEXT: ret ptr @fmv._Mbf16 +// CHECK: resolver_else38: +// CHECK-NEXT: [[TMP80:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 +// CHECK-NEXT: [[TMP81:%.*]] = and i64 [[TMP80]], 67109632 +// CHECK-NEXT: [[TMP82:%.*]] = icmp eq i64 [[TMP81]], 67109632 +// CHECK-NEXT: [[TMP83:%.*]] = and i1 true, [[TMP82]] +// CHECK-NEXT: br i1 [[TMP83]], label [[RESOLVER_RETURN39:%.*]], label [[RESOLVER_ELSE40:%.*]] +// CHECK: resolver_return39: +// CHECK-NEXT: ret ptr @fmv._Mi8mm +// CHECK: resolver_else40: +// CHECK-NEXT: [[TMP84:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 +// CHECK-NEXT: [[TMP85:%.*]] = and i64 [[TMP84]], 16777472 +// CHECK-NEXT: [[TMP86:%.*]] = icmp eq i64 [[TMP85]], 16777472 +// CHECK-NEXT: [[TMP87:%.*]] = and i1 true, [[TMP86]] +// CHECK-NEXT: br i1 [[TMP87]], label [[RESOLVER_RETURN41:%.*]], label [[RESOLVER_ELSE42:%.*]] +// CHECK: resolver_return41: +// CHECK-NEXT: ret ptr @fmv._Mfrintts +// CHECK: resolver_else42: +// CHECK-NEXT: [[TMP88:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 +// CHECK-NEXT: [[TMP89:%.*]] = and i64 [[TMP88]], 288230376164294656 +// CHECK-NEXT: [[TMP90:%.*]] = icmp eq i64 [[TMP89]], 288230376164294656 +// CHECK-NEXT: [[TMP91:%.*]] = and i1 true, [[TMP90]] +// CHECK-NEXT: br i1 [[TMP91]], label [[RESOLVER_RETURN43:%.*]], label [[RESOLVER_ELSE44:%.*]] +// CHECK: resolver_return43: +// CHECK-NEXT: ret ptr @fmv._Mrcpc3 +// CHECK: resolver_else44: +// CHECK-NEXT: [[TMP92:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 +// CHECK-NEXT: [[TMP93:%.*]] = and i64 [[TMP92]], 12582912 +// CHECK-NEXT: [[TMP94:%.*]] = icmp eq i64 [[TMP93]], 12582912 +// CHECK-NEXT: [[TMP95:%.*]] = and i1 true, [[TMP94]] +// CHECK-NEXT: br i1 [[TMP95]], label [[RESOLVER_RETURN45:%.*]], label [[RESOLVER_ELSE46:%.*]] +// CHECK: resolver_return45: +// CHECK-NEXT: ret ptr @fmv._Mrcpc2 +// CHECK: resolver_else46: +// CHECK-NEXT: [[TMP96:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 +// CHECK-NEXT: [[TMP97:%.*]] = and i64 [[TMP96]], 4194304 +// CHECK-NEXT: [[TMP98:%.*]] = icmp eq i64 [[TMP97]], 4194304 +// CHECK-NEXT: [[TMP99:%.*]] = and i1 true, [[TMP98]] +// CHECK-NEXT: br i1 [[TMP99]], label [[RESOLVER_RETURN47:%.*]], label [[RESOLVER_ELSE48:%.*]] +// CHECK: resolver_return47: +// CHECK-NEXT: ret ptr @fmv._Mrcpc +// CHECK: resolver_else48: +// CHECK-NEXT: [[TMP100:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 +// CHECK-NEXT: [[TMP101:%.*]] = and i64 [[TMP100]], 2097920 +// CHECK-NEXT: [[TMP102:%.*]] = icmp eq i64 [[TMP101]], 2097920 +// CHECK-NEXT: [[TMP103:%.*]] = and i1 true, [[TMP102]] +// CHECK-NEXT: br i1 [[TMP103]], label [[RESOLVER_RETURN49:%.*]], label [[RESOLVER_ELSE50:%.*]] +// CHECK: resolver_return49: +// CHECK-NEXT: ret ptr @fmv._Mfcma +// CHECK: resolver_else50: +// CHECK-NEXT: [[TMP104:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 +// CHECK-NEXT: [[TMP105:%.*]] = and i64 [[TMP104]], 1048832 +// CHECK-NEXT: [[TMP106:%.*]] = icmp eq i64 [[TMP105]], 1048832 +// CHECK-NEXT: [[TMP107:%.*]] = and i1 true, [[TMP106]] +// CHECK-NEXT: br i1 [[TMP107]], label [[RESOLVER_RETURN51:%.*]], label [[RESOLVER_ELSE52:%.*]] +// CHECK: resolver_return51: +// CHECK-NEXT: ret ptr @fmv._Mjscvt +// CHECK: resolver_else52: +// CHECK-NEXT: [[TMP108:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 +// CHECK-NEXT: [[TMP109:%.*]] = and i64 [[TMP108]], 786432 +// CHECK-NEXT: [[TMP110:%.*]] = icmp eq i64 [[TMP109]], 786432 +// CHECK-NEXT: [[TMP111:%.*]] = and i1 true, [[TMP110]] +// CHECK-NEXT: br i1 [[TMP111]], label [[RESOLVER_RETURN53:%.*]], label [[RESOLVER_ELSE54:%.*]] +// CHECK: resolver_return53: +// CHECK-NEXT: ret ptr @fmv._Mdpb2 +// CHECK: resolver_else54: +// CHECK-NEXT: [[TMP112:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 +// CHECK-NEXT: [[TMP113:%.*]] = and i64 [[TMP112]], 262144 +// CHECK-NEXT: [[TMP114:%.*]] = icmp eq i64 [[TMP113]], 262144 +// CHECK-NEXT: [[TMP115:%.*]] = and i1 true, [[TMP114]] +// CHECK-NEXT: br i1 [[TMP115]], label [[RESOLVER_RETURN55:%.*]], label [[RESOLVER_ELSE56:%.*]] +// CHECK: resolver_return55: +// CHECK-NEXT: ret ptr @fmv._Mdpb +// CHECK: resolver_else56: +// CHECK-NEXT: [[TMP116:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 +// CHECK-NEXT: [[TMP117:%.*]] = and i64 [[TMP116]], 131072 +// CHECK-NEXT: [[TMP118:%.*]] = icmp eq i64 [[TMP117]], 131072 +// CHECK-NEXT: [[TMP119:%.*]] = and i1 true, [[TMP118]] +// CHECK-NEXT: br i1 [[TMP119]], label [[RESOLVER_RETURN57:%.*]], label [[RESOLVER_ELSE58:%.*]] +// CHECK: resolver_return57: +// CHECK-NEXT: ret ptr @fmv._Mdit +// CHECK: resolver_else58: +// CHECK-NEXT: [[TMP120:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 +// CHECK-NEXT: [[TMP121:%.*]] = and i64 [[TMP120]], 66312 +// CHECK-NEXT: [[TMP122:%.*]] = icmp eq i64 [[TMP121]], 66312 +// CHECK-NEXT: [[TMP123:%.*]] = and i1 true, [[TMP122]] +// CHECK-NEXT: br i1 [[TMP123]], label [[RESOLVER_RETURN59:%.*]], label [[RESOLVER_ELSE60:%.*]] +// CHECK: resolver_return59: +// CHECK-NEXT: ret ptr @fmv._Mfp16fml +// CHECK: resolver_else60: +// CHECK-NEXT: [[TMP124:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 +// CHECK-NEXT: [[TMP125:%.*]] = and i64 [[TMP124]], 65792 +// CHECK-NEXT: [[TMP126:%.*]] = icmp eq i64 [[TMP125]], 65792 +// CHECK-NEXT: [[TMP127:%.*]] = and i1 true, [[TMP126]] +// CHECK-NEXT: br i1 [[TMP127]], label [[RESOLVER_RETURN61:%.*]], label [[RESOLVER_ELSE62:%.*]] +// CHECK: resolver_return61: +// CHECK-NEXT: ret ptr @fmv._Mfp16 +// CHECK: resolver_else62: +// CHECK-NEXT: [[TMP128:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 +// CHECK-NEXT: [[TMP129:%.*]] = and i64 [[TMP128]], 33536 +// CHECK-NEXT: [[TMP130:%.*]] = icmp eq i64 [[TMP129]], 33536 +// CHECK-NEXT: [[TMP131:%.*]] = and i1 true, [[TMP130]] +// CHECK-NEXT: br i1 [[TMP131]], label [[RESOLVER_RETURN63:%.*]], label [[RESOLVER_ELSE64:%.*]] +// CHECK: resolver_return63: +// CHECK-NEXT: ret ptr @fmv._Maes +// CHECK: resolver_else64: +// CHECK-NEXT: [[TMP132:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 +// CHECK-NEXT: [[TMP133:%.*]] = and i64 [[TMP132]], 13056 +// CHECK-NEXT: [[TMP134:%.*]] = icmp eq i64 [[TMP133]], 13056 +// CHECK-NEXT: [[TMP135:%.*]] = and i1 true, [[TMP134]] +// CHECK-NEXT: br i1 [[TMP135]], label [[RESOLVER_RETURN65:%.*]], label [[RESOLVER_ELSE66:%.*]] +// CHECK: resolver_return65: +// CHECK-NEXT: ret ptr @fmv._Msha3 +// CHECK: resolver_else66: +// CHECK-NEXT: [[TMP136:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 +// CHECK-NEXT: [[TMP137:%.*]] = and i64 [[TMP136]], 4864 +// CHECK-NEXT: [[TMP138:%.*]] = icmp eq i64 [[TMP137]], 4864 +// CHECK-NEXT: [[TMP139:%.*]] = and i1 true, [[TMP138]] +// CHECK-NEXT: br i1 [[TMP139]], label [[RESOLVER_RETURN67:%.*]], label [[RESOLVER_ELSE68:%.*]] +// CHECK: resolver_return67: +// CHECK-NEXT: ret ptr @fmv._Msha2 +// CHECK: resolver_else68: +// CHECK-NEXT: [[TMP140:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 +// CHECK-NEXT: [[TMP141:%.*]] = and i64 [[TMP140]], 1024 +// CHECK-NEXT: [[TMP142:%.*]] = icmp eq i64 [[TMP141]], 1024 +// CHECK-NEXT: [[TMP143:%.*]] = and i1 true, [[TMP142]] +// CHECK-NEXT: br i1 [[TMP143]], label [[RESOLVER_RETURN69:%.*]], label [[RESOLVER_ELSE70:%.*]] +// CHECK: resolver_return69: +// CHECK-NEXT: ret ptr @fmv._Mcrc +// CHECK: resolver_else70: +// CHECK-NEXT: [[TMP144:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 +// CHECK-NEXT: [[TMP145:%.*]] = and i64 [[TMP144]], 832 +// CHECK-NEXT: [[TMP146:%.*]] = icmp eq i64 [[TMP145]], 832 +// CHECK-NEXT: [[TMP147:%.*]] = and i1 true, [[TMP146]] +// CHECK-NEXT: br i1 [[TMP147]], label [[RESOLVER_RETURN71:%.*]], label [[RESOLVER_ELSE72:%.*]] +// CHECK: resolver_return71: +// CHECK-NEXT: ret ptr @fmv._Mrdm +// CHECK: resolver_else72: +// CHECK-NEXT: [[TMP148:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 +// CHECK-NEXT: [[TMP149:%.*]] = and i64 [[TMP148]], 800 +// CHECK-NEXT: [[TMP150:%.*]] = icmp eq i64 [[TMP149]], 800 +// CHECK-NEXT: [[TMP151:%.*]] = and i1 true, [[TMP150]] +// CHECK-NEXT: br i1 [[TMP151]], label [[RESOLVER_RETURN73:%.*]], label [[RESOLVER_ELSE74:%.*]] +// CHECK: resolver_return73: +// CHECK-NEXT: ret ptr @fmv._Msm4 +// CHECK: resolver_else74: +// CHECK-NEXT: [[TMP152:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 +// CHECK-NEXT: [[TMP153:%.*]] = and i64 [[TMP152]], 784 +// CHECK-NEXT: [[TMP154:%.*]] = icmp eq i64 [[TMP153]], 784 +// CHECK-NEXT: [[TMP155:%.*]] = and i1 true, [[TMP154]] +// CHECK-NEXT: br i1 [[TMP155]], label [[RESOLVER_RETURN75:%.*]], label [[RESOLVER_ELSE76:%.*]] +// CHECK: resolver_return75: +// CHECK-NEXT: ret ptr @fmv._Mdotprod +// CHECK: resolver_else76: +// CHECK-NEXT: [[TMP156:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 +// CHECK-NEXT: [[TMP157:%.*]] = and i64 [[TMP156]], 768 +// CHECK-NEXT: [[TMP158:%.*]] = icmp eq i64 [[TMP157]], 768 +// CHECK-NEXT: [[TMP159:%.*]] = and i1 true, [[TMP158]] +// CHECK-NEXT: br i1 [[TMP159]], label [[RESOLVER_RETURN77:%.*]], label [[RESOLVER_ELSE78:%.*]] +// CHECK: resolver_return77: +// CHECK-NEXT: ret ptr @fmv._Msimd +// CHECK: resolver_else78: +// CHECK-NEXT: [[TMP160:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 +// CHECK-NEXT: [[TMP161:%.*]] = and i64 [[TMP160]], 256 +// CHECK-NEXT: [[TMP162:%.*]] = icmp eq i64 [[TMP161]], 256 +// CHECK-NEXT: [[TMP163:%.*]] = and i1 true, [[TMP162]] +// CHECK-NEXT: br i1 [[TMP163]], label [[RESOLVER_RETURN79:%.*]], label [[RESOLVER_ELSE80:%.*]] +// CHECK: resolver_return79: +// CHECK-NEXT: ret ptr @fmv._Mfp +// CHECK: resolver_else80: +// CHECK-NEXT: [[TMP164:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 +// CHECK-NEXT: [[TMP165:%.*]] = and i64 [[TMP164]], 128 +// CHECK-NEXT: [[TMP166:%.*]] = icmp eq i64 [[TMP165]], 128 +// CHECK-NEXT: [[TMP167:%.*]] = and i1 true, [[TMP166]] +// CHECK-NEXT: br i1 [[TMP167]], label [[RESOLVER_RETURN81:%.*]], label [[RESOLVER_ELSE82:%.*]] +// CHECK: resolver_return81: +// CHECK-NEXT: ret ptr @fmv._Mlse +// CHECK: resolver_else82: +// CHECK-NEXT: [[TMP168:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 +// CHECK-NEXT: [[TMP169:%.*]] = and i64 [[TMP168]], 6 +// CHECK-NEXT: [[TMP170:%.*]] = icmp eq i64 [[TMP169]], 6 +// CHECK-NEXT: [[TMP171:%.*]] = and i1 true, [[TMP170]] +// CHECK-NEXT: br i1 [[TMP171]], label [[RESOLVER_RETURN83:%.*]], label [[RESOLVER_ELSE84:%.*]] +// CHECK: resolver_return83: +// CHECK-NEXT: ret ptr @fmv._Mflagm2 +// CHECK: resolver_else84: +// CHECK-NEXT: [[TMP172:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 +// CHECK-NEXT: [[TMP173:%.*]] = and i64 [[TMP172]], 2 +// CHECK-NEXT: [[TMP174:%.*]] = icmp eq i64 [[TMP173]], 2 +// CHECK-NEXT: [[TMP175:%.*]] = and i1 true, [[TMP174]] +// CHECK-NEXT: br i1 [[TMP175]], label [[RESOLVER_RETURN85:%.*]], label [[RESOLVER_ELSE86:%.*]] +// CHECK: resolver_return85: +// CHECK-NEXT: ret ptr @fmv._Mflagm +// CHECK: resolver_else86: +// CHECK-NEXT: [[TMP176:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 +// CHECK-NEXT: [[TMP177:%.*]] = and i64 [[TMP176]], 1 +// CHECK-NEXT: [[TMP178:%.*]] = icmp eq i64 [[TMP177]], 1 +// CHECK-NEXT: [[TMP179:%.*]] = and i1 true, [[TMP178]] +// CHECK-NEXT: br i1 [[TMP179]], label [[RESOLVER_RETURN87:%.*]], label [[RESOLVER_ELSE88:%.*]] +// CHECK: resolver_return87: +// CHECK-NEXT: ret ptr @fmv._Mrng +// CHECK: resolver_else88: +// CHECK-NEXT: ret ptr @fmv.default +// +// +// CHECK: Function Attrs: noinline nounwind optnone +// CHECK-LABEL: define {{[^@]+}}@fmv._Mbti +// CHECK-SAME: () #[[ATTR2:[0-9]+]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: ret i32 0 +// +// +// CHECK: Function Attrs: noinline nounwind optnone +// CHECK-LABEL: define {{[^@]+}}@fmv._Mcrc +// CHECK-SAME: () #[[ATTR3:[0-9]+]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: ret i32 0 +// +// +// CHECK: Function Attrs: noinline nounwind optnone +// CHECK-LABEL: define {{[^@]+}}@fmv._Mdit +// CHECK-SAME: () #[[ATTR4:[0-9]+]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: ret i32 0 +// +// +// CHECK: Function Attrs: noinline nounwind optnone +// CHECK-LABEL: define {{[^@]+}}@fmv._Mdotprod +// CHECK-SAME: () #[[ATTR5:[0-9]+]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: ret i32 0 +// +// +// CHECK: Function Attrs: noinline nounwind optnone +// CHECK-LABEL: define {{[^@]+}}@fmv._Mdpb +// CHECK-SAME: () #[[ATTR6:[0-9]+]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: ret i32 0 +// +// +// CHECK: Function Attrs: noinline nounwind optnone +// CHECK-LABEL: define {{[^@]+}}@fmv._Mdpb2 +// CHECK-SAME: () #[[ATTR7:[0-9]+]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: ret i32 0 +// +// +// CHECK: Function Attrs: noinline nounwind optnone +// CHECK-LABEL: define {{[^@]+}}@fmv._Mf32mm +// CHECK-SAME: () #[[ATTR8:[0-9]+]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: ret i32 0 +// +// +// CHECK: Function Attrs: noinline nounwind optnone +// CHECK-LABEL: define {{[^@]+}}@fmv._Mf64mm +// CHECK-SAME: () #[[ATTR9:[0-9]+]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: ret i32 0 +// +// +// CHECK: Function Attrs: noinline nounwind optnone +// CHECK-LABEL: define {{[^@]+}}@fmv._Mfcma +// CHECK-SAME: () #[[ATTR10:[0-9]+]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: ret i32 0 +// +// +// CHECK: Function Attrs: noinline nounwind optnone +// CHECK-LABEL: define {{[^@]+}}@fmv._Mflagm +// CHECK-SAME: () #[[ATTR11:[0-9]+]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: ret i32 0 +// +// +// CHECK: Function Attrs: noinline nounwind optnone +// CHECK-LABEL: define {{[^@]+}}@fmv._Mflagm2 +// CHECK-SAME: () #[[ATTR12:[0-9]+]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: ret i32 0 +// +// +// CHECK: Function Attrs: noinline nounwind optnone +// CHECK-LABEL: define {{[^@]+}}@fmv._Mfp +// CHECK-SAME: () #[[ATTR13:[0-9]+]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: ret i32 0 +// +// +// CHECK: Function Attrs: noinline nounwind optnone +// CHECK-LABEL: define {{[^@]+}}@fmv._Mfp16 +// CHECK-SAME: () #[[ATTR14:[0-9]+]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: ret i32 0 +// +// +// CHECK: Function Attrs: noinline nounwind optnone +// CHECK-LABEL: define {{[^@]+}}@fmv._Mfp16fml +// CHECK-SAME: () #[[ATTR15:[0-9]+]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: ret i32 0 +// +// +// CHECK: Function Attrs: noinline nounwind optnone +// CHECK-LABEL: define {{[^@]+}}@fmv._Mfrintts +// CHECK-SAME: () #[[ATTR16:[0-9]+]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: ret i32 0 +// +// +// CHECK: Function Attrs: noinline nounwind optnone +// CHECK-LABEL: define {{[^@]+}}@fmv._Mi8mm +// CHECK-SAME: () #[[ATTR17:[0-9]+]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: ret i32 0 +// +// +// CHECK: Function Attrs: noinline nounwind optnone +// CHECK-LABEL: define {{[^@]+}}@fmv._Mjscvt +// CHECK-SAME: () #[[ATTR18:[0-9]+]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: ret i32 0 +// +// +// CHECK: Function Attrs: noinline nounwind optnone +// CHECK-LABEL: define {{[^@]+}}@fmv._Mlse +// CHECK-SAME: () #[[ATTR19:[0-9]+]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: ret i32 0 +// +// +// CHECK: Function Attrs: noinline nounwind optnone +// CHECK-LABEL: define {{[^@]+}}@fmv._Mmemtag +// CHECK-SAME: () #[[ATTR20:[0-9]+]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: ret i32 0 +// +// +// CHECK: Function Attrs: noinline nounwind optnone +// CHECK-LABEL: define {{[^@]+}}@fmv._Mmops +// CHECK-SAME: () #[[ATTR21:[0-9]+]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: ret i32 0 +// +// +// CHECK: Function Attrs: noinline nounwind optnone +// CHECK-LABEL: define {{[^@]+}}@fmv._Mrcpc +// CHECK-SAME: () #[[ATTR22:[0-9]+]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: ret i32 0 +// +// +// CHECK: Function Attrs: noinline nounwind optnone +// CHECK-LABEL: define {{[^@]+}}@fmv._Mrcpc2 +// CHECK-SAME: () #[[ATTR23:[0-9]+]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: ret i32 0 +// +// +// CHECK: Function Attrs: noinline nounwind optnone +// CHECK-LABEL: define {{[^@]+}}@fmv._Mrcpc3 +// CHECK-SAME: () #[[ATTR24:[0-9]+]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: ret i32 0 +// +// +// CHECK: Function Attrs: noinline nounwind optnone +// CHECK-LABEL: define {{[^@]+}}@fmv._Mrdm +// CHECK-SAME: () #[[ATTR25:[0-9]+]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: ret i32 0 +// +// +// CHECK: Function Attrs: noinline nounwind optnone +// CHECK-LABEL: define {{[^@]+}}@fmv._Mrng +// CHECK-SAME: () #[[ATTR26:[0-9]+]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: ret i32 0 +// +// +// CHECK: Function Attrs: noinline nounwind optnone +// CHECK-LABEL: define {{[^@]+}}@fmv._Msb +// CHECK-SAME: () #[[ATTR27:[0-9]+]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: ret i32 0 +// +// +// CHECK: Function Attrs: noinline nounwind optnone +// CHECK-LABEL: define {{[^@]+}}@fmv._Msha2 +// CHECK-SAME: () #[[ATTR28:[0-9]+]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: ret i32 0 +// +// +// CHECK: Function Attrs: noinline nounwind optnone +// CHECK-LABEL: define {{[^@]+}}@fmv._Msha3 +// CHECK-SAME: () #[[ATTR29:[0-9]+]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: ret i32 0 +// +// +// CHECK: Function Attrs: noinline nounwind optnone +// CHECK-LABEL: define {{[^@]+}}@fmv._Msimd +// CHECK-SAME: () #[[ATTR30:[0-9]+]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: ret i32 0 +// +// +// CHECK: Function Attrs: noinline nounwind optnone +// CHECK-LABEL: define {{[^@]+}}@fmv._Msm4 +// CHECK-SAME: () #[[ATTR31:[0-9]+]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: ret i32 0 +// +// +// CHECK: Function Attrs: noinline nounwind optnone +// CHECK-LABEL: define {{[^@]+}}@fmv._Msme +// CHECK-SAME: () #[[ATTR32:[0-9]+]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: ret i32 0 +// +// +// CHECK: Function Attrs: noinline nounwind optnone +// CHECK-LABEL: define {{[^@]+}}@fmv._Msme-f64f64 +// CHECK-SAME: () #[[ATTR33:[0-9]+]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: ret i32 0 +// +// +// CHECK: Function Attrs: noinline nounwind optnone +// CHECK-LABEL: define {{[^@]+}}@fmv._Msme-i16i64 +// CHECK-SAME: () #[[ATTR34:[0-9]+]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: ret i32 0 +// +// +// CHECK: Function Attrs: noinline nounwind optnone +// CHECK-LABEL: define {{[^@]+}}@fmv._Msme2 +// CHECK-SAME: () #[[ATTR35:[0-9]+]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: ret i32 0 +// +// +// CHECK: Function Attrs: noinline nounwind optnone +// CHECK-LABEL: define {{[^@]+}}@fmv._Mssbs +// CHECK-SAME: () #[[ATTR36:[0-9]+]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: ret i32 0 +// +// +// CHECK: Function Attrs: noinline nounwind optnone +// CHECK-LABEL: define {{[^@]+}}@fmv._Msve +// CHECK-SAME: () #[[ATTR37:[0-9]+]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: ret i32 0 +// +// +// CHECK: Function Attrs: noinline nounwind optnone +// CHECK-LABEL: define {{[^@]+}}@fmv._Msve2 +// CHECK-SAME: () #[[ATTR38:[0-9]+]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: ret i32 0 +// +// +// CHECK: Function Attrs: noinline nounwind optnone +// CHECK-LABEL: define {{[^@]+}}@fmv._Msve2-aes +// CHECK-SAME: () #[[ATTR39:[0-9]+]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: ret i32 0 +// +// +// CHECK: Function Attrs: noinline nounwind optnone +// CHECK-LABEL: define {{[^@]+}}@fmv._Msve2-bitperm +// CHECK-SAME: () #[[ATTR40:[0-9]+]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: ret i32 0 +// +// +// CHECK: Function Attrs: noinline nounwind optnone +// CHECK-LABEL: define {{[^@]+}}@fmv._Msve2-sha3 +// CHECK-SAME: () #[[ATTR41:[0-9]+]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: ret i32 0 +// +// +// CHECK: Function Attrs: noinline nounwind optnone +// CHECK-LABEL: define {{[^@]+}}@fmv._Msve2-sm4 +// CHECK-SAME: () #[[ATTR42:[0-9]+]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: ret i32 0 +// +// +// CHECK: Function Attrs: noinline nounwind optnone +// CHECK-LABEL: define {{[^@]+}}@fmv._Mwfxt +// CHECK-SAME: () #[[ATTR43:[0-9]+]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: ret i32 0 +// +// +// CHECK: Function Attrs: noinline nounwind optnone +// CHECK-LABEL: define {{[^@]+}}@caller +// CHECK-SAME: () #[[ATTR44:[0-9]+]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[CALL:%.*]] = call i32 @fmv() +// CHECK-NEXT: ret i32 [[CALL]] +// +// +// CHECK: Function Attrs: noinline nounwind optnone +// CHECK-LABEL: define {{[^@]+}}@fmv.default +// CHECK-SAME: () #[[ATTR45:[0-9]+]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: ret i32 0 +// +//. +// CHECK: [[META0:![0-9]+]] = !{i32 1, !"wchar_size", i32 4} +// CHECK: [[META1:![0-9]+]] = !{!"{{.*}}clang version {{.*}}"} +//. diff --git a/clang/test/CodeGen/AArch64/fmv-mix-explicit-implicit-default.c b/clang/test/CodeGen/AArch64/fmv-mix-explicit-implicit-default.c index 032738fb9664d..dcc5e1c5886e2 100644 --- a/clang/test/CodeGen/AArch64/fmv-mix-explicit-implicit-default.c +++ b/clang/test/CodeGen/AArch64/fmv-mix-explicit-implicit-default.c @@ -1,3 +1,4 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --check-attributes --check-globals --include-generated-funcs --global-value-regex ".*" // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -emit-llvm -o - %s | FileCheck %s // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature -fmv -emit-llvm -o - %s | FileCheck %s -check-prefix=CHECK-NOFMV @@ -90,9 +91,6 @@ int caller6(void) { return no_def_explicit_default_first(); } // CHECK-NEXT: ret i32 [[CALL]] // // -// CHECK: declare i32 @no_def_implicit_default_first() #[[ATTR2:[0-9]+]] -// -// // CHECK: Function Attrs: noinline nounwind optnone // CHECK-LABEL: define {{[^@]+}}@caller5 // CHECK-SAME: () #[[ATTR1]] { @@ -101,9 +99,6 @@ int caller6(void) { return no_def_explicit_default_first(); } // CHECK-NEXT: ret i32 [[CALL]] // // -// CHECK: declare i32 @no_def_explicit_default_first() #[[ATTR2]] -// -// // CHECK: Function Attrs: noinline nounwind optnone // CHECK-LABEL: define {{[^@]+}}@caller6 // CHECK-SAME: () #[[ATTR1]] { @@ -132,12 +127,6 @@ int caller6(void) { return no_def_explicit_default_first(); } // CHECK-NEXT: ret ptr @explicit_default_decl_first.default // // -// CHECK: declare i32 @no_def_implicit_default_first.default() #[[ATTR2]] -// -// -// CHECK: declare i32 @no_def_explicit_default_first.default() #[[ATTR2]] -// -// // CHECK-NOFMV: Function Attrs: noinline nounwind optnone // CHECK-NOFMV-LABEL: define {{[^@]+}}@caller1 // CHECK-NOFMV-SAME: () #[[ATTR0:[0-9]+]] { @@ -206,9 +195,6 @@ int caller6(void) { return no_def_explicit_default_first(); } // CHECK-NOFMV-NEXT: ret i32 [[CALL]] // // -// CHECK-NOFMV: declare i32 @no_def_implicit_default_first() #[[ATTR2:[0-9]+]] -// -// // CHECK-NOFMV: Function Attrs: noinline nounwind optnone // CHECK-NOFMV-LABEL: define {{[^@]+}}@caller6 // CHECK-NOFMV-SAME: () #[[ATTR0]] { @@ -216,6 +202,10 @@ int caller6(void) { return no_def_explicit_default_first(); } // CHECK-NOFMV-NEXT: [[CALL:%.*]] = call i32 @no_def_explicit_default_first() // CHECK-NOFMV-NEXT: ret i32 [[CALL]] // -// -// CHECK-NOFMV: declare i32 @no_def_explicit_default_first() #[[ATTR2]] +//. +// CHECK: [[META0:![0-9]+]] = !{i32 1, !"wchar_size", i32 4} +// CHECK: [[META1:![0-9]+]] = !{!"{{.*}}clang version {{.*}}"} +//. +// CHECK-NOFMV: [[META0:![0-9]+]] = !{i32 1, !"wchar_size", i32 4} +// CHECK-NOFMV: [[META1:![0-9]+]] = !{!"{{.*}}clang version {{.*}}"} //. diff --git a/clang/test/CodeGen/AArch64/fmv-resolver-emission.c b/clang/test/CodeGen/AArch64/fmv-resolver-emission.c index eeafb3d41860d..84667910c6e53 100644 --- a/clang/test/CodeGen/AArch64/fmv-resolver-emission.c +++ b/clang/test/CodeGen/AArch64/fmv-resolver-emission.c @@ -1,111 +1,345 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --check-attributes --check-globals --include-generated-funcs --global-value-regex ".*" // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -emit-llvm -o - %s | FileCheck %s -// CHECK: @used_before_default_def = weak_odr ifunc void (), ptr @used_before_default_def.resolver -// CHECK: @used_after_default_def = weak_odr ifunc void (), ptr @used_after_default_def.resolver -// CHECK-NOT: @used_before_default_decl = weak_odr ifunc void (), ptr @used_before_default_decl.resolver -// CHECK-NOT: @used_after_default_decl = weak_odr ifunc void (), ptr @used_after_default_decl.resolver -// CHECK-NOT: @used_no_default = weak_odr ifunc void (), ptr @used_no_default.resolver -// CHECK-NOT: @not_used_no_default = weak_odr ifunc void (), ptr @not_used_no_default.resolver -// CHECK: @not_used_with_default = weak_odr ifunc void (), ptr @not_used_with_default.resolver - // Test that an ifunc is generated and used when the default // version is defined after the first use of the function. -// __attribute__((target_version("aes"))) void used_before_default_def(void) {} -// CHECK-LABEL: define dso_local void @used_before_default_def._Maes( -// void call_before_def(void) { used_before_default_def(); } -// CHECK-LABEL: define dso_local void @call_before_def( -// CHECK: call void @used_before_default_def() -// __attribute__((target_version("default"))) void used_before_default_def(void) {} -// CHECK-LABEL: define dso_local void @used_before_default_def.default( -// -// CHECK-NOT: declare void @used_before_default_def( // Test that an ifunc is generated and used when the default // version is defined before the first use of the function. -// __attribute__((target_version("aes"))) void used_after_default_def(void) {} -// CHECK-LABEL: define dso_local void @used_after_default_def._Maes( -// __attribute__((target_version("default"))) void used_after_default_def(void) {} -// CHECK-LABEL: define dso_local void @used_after_default_def.default( -// void call_after_def(void) { used_after_default_def(); } -// CHECK-LABEL: define dso_local void @call_after_def( -// CHECK: call void @used_after_default_def() -// -// CHECK-NOT: declare void @used_after_default_def( // Test that an unmagled declaration is generated and used when the // default version is declared after the first use of the function. -// __attribute__((target_version("aes"))) void used_before_default_decl(void) {} -// CHECK-LABEL: define dso_local void @used_before_default_decl._Maes( -// void call_before_decl(void) { used_before_default_decl(); } -// CHECK-LABEL: define dso_local void @call_before_decl( -// CHECK: call void @used_before_default_decl() -// __attribute__((target_version("default"))) void used_before_default_decl(void); -// CHECK: declare void @used_before_default_decl() // Test that an unmagled declaration is generated and used when the // default version is declared before the first use of the function. -// __attribute__((target_version("aes"))) void used_after_default_decl(void) {} -// CHECK-LABEL: define dso_local void @used_after_default_decl._Maes( -// __attribute__((target_version("default"))) void used_after_default_decl(void); -// CHECK: declare void @used_after_default_decl() -// void call_after_decl(void) { used_after_default_decl(); } -// CHECK-LABEL: define dso_local void @call_after_decl( -// CHECK: call void @used_after_default_decl() // Test that an unmagled declaration is generated and used when // the default version is not present. -// __attribute__((target_version("aes"))) void used_no_default(void) {} -// CHECK-LABEL: define dso_local void @used_no_default._Maes( -// void call_no_default(void) { used_no_default(); } -// CHECK-LABEL: define dso_local void @call_no_default( -// CHECK: call void @used_no_default() -// -// CHECK: declare void @used_no_default() // Test that neither an ifunc nor a declaration is generated if the default // definition is missing since the versioned function is not used. -// __attribute__((target_version("aes"))) void not_used_no_default(void) {} -// CHECK-LABEL: define dso_local void @not_used_no_default._Maes( -// -// CHECK-NOT: declare void @not_used_no_default( // Test that an ifunc is generated if the default version is defined but not used. -// __attribute__((target_version("aes"))) void not_used_with_default(void) {} -// CHECK-LABEL: define dso_local void @not_used_with_default._Maes( -// __attribute__((target_version("default"))) void not_used_with_default(void) {} -// CHECK-LABEL: define dso_local void @not_used_with_default.default( -// -// CHECK-NOT: declare void @not_used_with_default( -// CHECK: define weak_odr ptr @used_before_default_def.resolver() -// CHECK: define weak_odr ptr @used_after_default_def.resolver() -// CHECK-NOT: define weak_odr ptr @used_before_default_decl.resolver( -// CHECK-NOT: define weak_odr ptr @used_after_default_decl.resolver( -// CHECK-NOT: define weak_odr ptr @used_no_default.resolver( -// CHECK-NOT: define weak_odr ptr @not_used_no_default.resolver( -// CHECK: define weak_odr ptr @not_used_with_default.resolver() +// Test that the ifunc symbol can be used for indirect calls. +__attribute__((target_version("aes"))) void indirect_use(void) {} +__attribute__((target_version("default"))) void indirect_use(void) {} +typedef void (*fptr)(void); +void call_indirectly(void) { + fptr fn = indirect_use; + fn(); +} + + +// Test that an internal ifunc is generated if the versions are annotated with static inline. +static inline __attribute__((target_version("aes"))) void internal_func(void) {} +static inline __attribute__((target_version("default"))) void internal_func(void) {} +void call_internal(void) { internal_func(); } + + +// Test that an ifunc is generated with if the versions are annotated with inline. +inline __attribute__((target_version("aes"))) void linkonce_func(void) {} +inline __attribute__((target_version("default"))) void linkonce_func(void) {} +void call_linkonce(void) { linkonce_func(); } + + +//. +// CHECK: @__aarch64_cpu_features = external dso_local global { i64 } +// CHECK: @used_before_default_def = weak_odr ifunc void (), ptr @used_before_default_def.resolver +// CHECK: @used_after_default_def = weak_odr ifunc void (), ptr @used_after_default_def.resolver +// CHECK: @not_used_with_default = weak_odr ifunc void (), ptr @not_used_with_default.resolver +// CHECK: @indirect_use = weak_odr ifunc void (), ptr @indirect_use.resolver +// CHECK: @internal_func = internal ifunc void (), ptr @internal_func.resolver +// CHECK: @linkonce_func = weak_odr ifunc void (), ptr @linkonce_func.resolver +//. +// CHECK: Function Attrs: noinline nounwind optnone +// CHECK-LABEL: define {{[^@]+}}@used_before_default_def._Maes +// CHECK-SAME: () #[[ATTR0:[0-9]+]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: ret void +// +// +// CHECK: Function Attrs: noinline nounwind optnone +// CHECK-LABEL: define {{[^@]+}}@call_before_def +// CHECK-SAME: () #[[ATTR1:[0-9]+]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: call void @used_before_default_def() +// CHECK-NEXT: ret void +// +// +// CHECK: Function Attrs: noinline nounwind optnone +// CHECK-LABEL: define {{[^@]+}}@used_before_default_def.default +// CHECK-SAME: () #[[ATTR2:[0-9]+]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: ret void +// +// +// CHECK: Function Attrs: noinline nounwind optnone +// CHECK-LABEL: define {{[^@]+}}@used_after_default_def._Maes +// CHECK-SAME: () #[[ATTR0]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: ret void +// +// +// CHECK: Function Attrs: noinline nounwind optnone +// CHECK-LABEL: define {{[^@]+}}@used_after_default_def.default +// CHECK-SAME: () #[[ATTR2]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: ret void +// +// +// CHECK: Function Attrs: noinline nounwind optnone +// CHECK-LABEL: define {{[^@]+}}@call_after_def +// CHECK-SAME: () #[[ATTR1]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: call void @used_after_default_def() +// CHECK-NEXT: ret void +// +// +// CHECK: Function Attrs: noinline nounwind optnone +// CHECK-LABEL: define {{[^@]+}}@used_before_default_decl._Maes +// CHECK-SAME: () #[[ATTR0]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: ret void +// +// +// CHECK: Function Attrs: noinline nounwind optnone +// CHECK-LABEL: define {{[^@]+}}@call_before_decl +// CHECK-SAME: () #[[ATTR1]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: call void @used_before_default_decl() +// CHECK-NEXT: ret void +// +// +// CHECK: Function Attrs: noinline nounwind optnone +// CHECK-LABEL: define {{[^@]+}}@used_after_default_decl._Maes +// CHECK-SAME: () #[[ATTR0]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: ret void +// +// +// CHECK: Function Attrs: noinline nounwind optnone +// CHECK-LABEL: define {{[^@]+}}@call_after_decl +// CHECK-SAME: () #[[ATTR1]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: call void @used_after_default_decl() +// CHECK-NEXT: ret void +// +// +// CHECK: Function Attrs: noinline nounwind optnone +// CHECK-LABEL: define {{[^@]+}}@used_no_default._Maes +// CHECK-SAME: () #[[ATTR0]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: ret void +// +// +// CHECK: Function Attrs: noinline nounwind optnone +// CHECK-LABEL: define {{[^@]+}}@call_no_default +// CHECK-SAME: () #[[ATTR1]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: call void @used_no_default() +// CHECK-NEXT: ret void +// +// +// CHECK: Function Attrs: noinline nounwind optnone +// CHECK-LABEL: define {{[^@]+}}@not_used_no_default._Maes +// CHECK-SAME: () #[[ATTR0]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: ret void +// +// +// CHECK: Function Attrs: noinline nounwind optnone +// CHECK-LABEL: define {{[^@]+}}@not_used_with_default._Maes +// CHECK-SAME: () #[[ATTR0]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: ret void +// +// +// CHECK: Function Attrs: noinline nounwind optnone +// CHECK-LABEL: define {{[^@]+}}@not_used_with_default.default +// CHECK-SAME: () #[[ATTR2]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: ret void +// +// +// CHECK: Function Attrs: noinline nounwind optnone +// CHECK-LABEL: define {{[^@]+}}@indirect_use._Maes +// CHECK-SAME: () #[[ATTR0]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: ret void +// +// +// CHECK: Function Attrs: noinline nounwind optnone +// CHECK-LABEL: define {{[^@]+}}@indirect_use.default +// CHECK-SAME: () #[[ATTR2]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: ret void +// +// +// CHECK: Function Attrs: noinline nounwind optnone +// CHECK-LABEL: define {{[^@]+}}@call_indirectly +// CHECK-SAME: () #[[ATTR1]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[FN:%.*]] = alloca ptr, align 8 +// CHECK-NEXT: store ptr @indirect_use, ptr [[FN]], align 8 +// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[FN]], align 8 +// CHECK-NEXT: call void [[TMP0]]() +// CHECK-NEXT: ret void +// +// +// CHECK: Function Attrs: noinline nounwind optnone +// CHECK-LABEL: define {{[^@]+}}@call_internal +// CHECK-SAME: () #[[ATTR1]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: call void @internal_func() +// CHECK-NEXT: ret void +// +// +// CHECK: Function Attrs: noinline nounwind optnone +// CHECK-LABEL: define {{[^@]+}}@call_linkonce +// CHECK-SAME: () #[[ATTR1]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: call void @linkonce_func() +// CHECK-NEXT: ret void +// +// +// CHECK-LABEL: define {{[^@]+}}@used_before_default_def.resolver() comdat { +// CHECK-NEXT: resolver_entry: +// CHECK-NEXT: call void @__init_cpu_features_resolver() +// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 +// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 33536 +// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 33536 +// CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]] +// CHECK-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]] +// CHECK: resolver_return: +// CHECK-NEXT: ret ptr @used_before_default_def._Maes +// CHECK: resolver_else: +// CHECK-NEXT: ret ptr @used_before_default_def.default +// +// +// CHECK-LABEL: define {{[^@]+}}@used_after_default_def.resolver() comdat { +// CHECK-NEXT: resolver_entry: +// CHECK-NEXT: call void @__init_cpu_features_resolver() +// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 +// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 33536 +// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 33536 +// CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]] +// CHECK-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]] +// CHECK: resolver_return: +// CHECK-NEXT: ret ptr @used_after_default_def._Maes +// CHECK: resolver_else: +// CHECK-NEXT: ret ptr @used_after_default_def.default +// +// +// CHECK-LABEL: define {{[^@]+}}@not_used_with_default.resolver() comdat { +// CHECK-NEXT: resolver_entry: +// CHECK-NEXT: call void @__init_cpu_features_resolver() +// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 +// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 33536 +// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 33536 +// CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]] +// CHECK-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]] +// CHECK: resolver_return: +// CHECK-NEXT: ret ptr @not_used_with_default._Maes +// CHECK: resolver_else: +// CHECK-NEXT: ret ptr @not_used_with_default.default +// +// +// CHECK-LABEL: define {{[^@]+}}@indirect_use.resolver() comdat { +// CHECK-NEXT: resolver_entry: +// CHECK-NEXT: call void @__init_cpu_features_resolver() +// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 +// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 33536 +// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 33536 +// CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]] +// CHECK-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]] +// CHECK: resolver_return: +// CHECK-NEXT: ret ptr @indirect_use._Maes +// CHECK: resolver_else: +// CHECK-NEXT: ret ptr @indirect_use.default +// +// +// CHECK: Function Attrs: noinline nounwind optnone +// CHECK-LABEL: define {{[^@]+}}@internal_func._Maes +// CHECK-SAME: () #[[ATTR0]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: ret void +// +// +// CHECK: Function Attrs: noinline nounwind optnone +// CHECK-LABEL: define {{[^@]+}}@internal_func.default +// CHECK-SAME: () #[[ATTR2]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: ret void +// +// +// CHECK-LABEL: define {{[^@]+}}@internal_func.resolver() { +// CHECK-NEXT: resolver_entry: +// CHECK-NEXT: call void @__init_cpu_features_resolver() +// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 +// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 33536 +// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 33536 +// CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]] +// CHECK-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]] +// CHECK: resolver_return: +// CHECK-NEXT: ret ptr @internal_func._Maes +// CHECK: resolver_else: +// CHECK-NEXT: ret ptr @internal_func.default +// +// +// CHECK: Function Attrs: noinline nounwind optnone +// CHECK-LABEL: define {{[^@]+}}@linkonce_func._Maes +// CHECK-SAME: () #[[ATTR0]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: ret void +// +// +// CHECK: Function Attrs: noinline nounwind optnone +// CHECK-LABEL: define {{[^@]+}}@linkonce_func.default +// CHECK-SAME: () #[[ATTR2]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: ret void +// +// +// CHECK-LABEL: define {{[^@]+}}@linkonce_func.resolver() comdat { +// CHECK-NEXT: resolver_entry: +// CHECK-NEXT: call void @__init_cpu_features_resolver() +// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 +// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 33536 +// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 33536 +// CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]] +// CHECK-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]] +// CHECK: resolver_return: +// CHECK-NEXT: ret ptr @linkonce_func._Maes +// CHECK: resolver_else: +// CHECK-NEXT: ret ptr @linkonce_func.default +// +//. +// CHECK: [[META0:![0-9]+]] = !{i32 1, !"wchar_size", i32 4} +// CHECK: [[META1:![0-9]+]] = !{!"{{.*}}clang version {{.*}}"} +//. diff --git a/clang/test/CodeGen/attr-target-version.c b/clang/test/CodeGen/attr-target-version.c deleted file mode 100644 index 11655b2efcd84..0000000000000 --- a/clang/test/CodeGen/attr-target-version.c +++ /dev/null @@ -1,1145 +0,0 @@ -// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --check-attributes --check-globals --include-generated-funcs --global-value-regex ".*" -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -emit-llvm -o - %s | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature -fmv -emit-llvm -o - %s | FileCheck %s -check-prefix=CHECK-NOFMV - -int __attribute__((target_version("rng+flagm+fp16fml"))) fmv(void) { return 1; } -int __attribute__((target_version("flagm2+sme-i16i64"))) fmv(void) { return 2; } -int __attribute__((target_version("lse+sha2"))) fmv(void) { return 3; } -int __attribute__((target_version("dotprod+wfxt"))) fmv(void) { return 4; } -int __attribute__((target_version("fp16fml+memtag"))) fmv(void) { return 5; } -int __attribute__((target_version("fp+aes"))) fmv(void) { return 6; } -int __attribute__((target_version("crc+wfxt"))) fmv(void) { return 7; } -int __attribute__((target_version("bti"))) fmv(void) { return 8; } -int __attribute__((target_version("sme2"))) fmv(void) { return 9; } -int __attribute__((target_version("default"))) fmv(void) { return 0; } -int __attribute__((target_version("wfxt+simd"))) fmv_one(void) { return 1; } -int __attribute__((target_version("dpb"))) fmv_one(void) { return 2; } -int __attribute__((target_version("default"))) fmv_one(void) { return 0; } -int __attribute__((target_version("fp"))) fmv_two(void) { return 1; } -int __attribute__((target_version("simd"))) fmv_two(void) { return 2; } -int __attribute__((target_version("fp16+simd"))) fmv_two(void) { return 4; } -int __attribute__((target_version("default"))) fmv_two(void) { return 0; } -int foo() { - return fmv()+fmv_one()+fmv_two(); -} - -inline int __attribute__((target_version("sha2+aes+f64mm"))) fmv_inline(void) { return 1; } -inline int __attribute__((target_version("fp16+fcma+rdma+sme+ fp16 "))) fmv_inline(void) { return 2; } -inline int __attribute__((target_version("sha3+i8mm+f32mm"))) fmv_inline(void) { return 12; } -inline int __attribute__((target_version("dit+bf16"))) fmv_inline(void) { return 8; } -inline int __attribute__((target_version("dpb+rcpc2 "))) fmv_inline(void) { return 6; } -inline int __attribute__((target_version(" dpb2 + jscvt"))) fmv_inline(void) { return 7; } -inline int __attribute__((target_version("rcpc+frintts"))) fmv_inline(void) { return 3; } -inline int __attribute__((target_version("sve+bf16"))) fmv_inline(void) { return 4; } -inline int __attribute__((target_version("sve2-aes+sve2-sha3"))) fmv_inline(void) { return 5; } -inline int __attribute__((target_version("sve2+sve2-aes+sve2-bitperm"))) fmv_inline(void) { return 9; } -inline int __attribute__((target_version("sve2-sm4+memtag"))) fmv_inline(void) { return 10; } -inline int __attribute__((target_version("memtag+rcpc3+mops"))) fmv_inline(void) { return 11; } -inline int __attribute__((target_version("aes+dotprod"))) fmv_inline(void) { return 13; } -inline int __attribute__((target_version("simd+fp16fml"))) fmv_inline(void) { return 14; } -inline int __attribute__((target_version("fp+sm4"))) fmv_inline(void) { return 15; } -inline int __attribute__((target_version("lse+rdm"))) fmv_inline(void) { return 16; } -inline int __attribute__((target_version("default"))) fmv_inline(void) { return 3; } - -__attribute__((target_version("wfxt"))) int fmv_e(void); -int fmv_e(void) { return 20; } - -static __attribute__((target_version("sb"))) inline int fmv_d(void); -static __attribute__((target_version("default"))) inline int fmv_d(void); - -int __attribute__((target_version("default"))) fmv_default(void) { return 111; } -int fmv_default(void); - -void fmv_c(void); -void __attribute__((target_version("ssbs"))) fmv_c(void){}; -void __attribute__((target_version("default"))) fmv_c(void){}; - -int goo() { - fmv_inline(); - fmv_e(); - fmv_d(); - fmv_c(); - return fmv_default(); -} -static inline int __attribute__((target_version("sb"))) fmv_d(void) { return 0; } -static inline int __attribute__((target_version(" default "))) fmv_d(void) { return 1; } - -static void func(void) {} -inline __attribute__((target_version("default"))) void recb(void) { func(); } -inline __attribute__((target_version("default"))) void reca(void) { recb(); } -void recur(void) { reca(); } - -int __attribute__((target_version("default"))) main(void) { - recur(); - return goo(); -} - -typedef int (*Fptr)(); -void f(Fptr); -int hoo(void) { - f(fmv); - Fptr fp1 = &fmv; - Fptr fp2 = fmv; - return fp1() + fp2(); -} - -// This should generate one target version but no resolver. -__attribute__((target_version("default"))) int unused_with_forward_default_decl(void); -__attribute__((target_version("mops"))) int unused_with_forward_default_decl(void) { return 0; } - -// This should also generate one target version but no resolver. -extern int unused_with_implicit_extern_forward_default_decl(void); -__attribute__((target_version("dotprod"))) -int unused_with_implicit_extern_forward_default_decl(void) { return 0; } - -// This should also generate one target version but no resolver. -__attribute__((target_version("aes"))) int unused_with_default_decl(void) { return 0; } -__attribute__((target_version("default"))) int unused_with_default_decl(void); - -// This should generate two target versions and the resolver. -__attribute__((target_version("sve"))) int unused_with_default_def(void) { return 0; } -__attribute__((target_version("default"))) int unused_with_default_def(void) { return 1; } - -// This should also generate two target versions and the resolver. -__attribute__((target_version("fp16"))) int unused_with_implicit_default_def(void) { return 0; } -int unused_with_implicit_default_def(void) { return 1; } - -// This should also generate two target versions and the resolver. -int unused_with_implicit_forward_default_def(void) { return 0; } -__attribute__((target_version("lse"))) int unused_with_implicit_forward_default_def(void) { return 1; } - -// This should generate a target version despite the default not being declared. -__attribute__((target_version("rdm"))) int unused_without_default(void) { return 0; } - -// These shouldn't generate anything. -int unused_version_declarations(void); -__attribute__((target_version("jscvt"))) int unused_version_declarations(void); -__attribute__((target_version("rdma"))) int unused_version_declarations(void); - -// These should generate the default (mangled) version and the resolver. -int default_def_with_version_decls(void) { return 0; } -__attribute__((target_version("jscvt"))) int default_def_with_version_decls(void); -__attribute__((target_version("rdma"))) int default_def_with_version_decls(void); - -// The following is guarded because in NOFMV we get errors for calling undeclared functions. -#ifdef __HAVE_FUNCTION_MULTI_VERSIONING -// This should generate a default declaration, two target versions but no resolver. -__attribute__((target_version("jscvt"))) int used_def_without_default_decl(void) { return 1; } -__attribute__((target_version("rdma"))) int used_def_without_default_decl(void) { return 2; } - -// This should generate a default declaration but no resolver. -__attribute__((target_version("jscvt"))) int used_decl_without_default_decl(void); -__attribute__((target_version("rdma"))) int used_decl_without_default_decl(void); - -int caller(void) { return used_def_without_default_decl() + used_decl_without_default_decl(); } -#endif - -//. -// CHECK: @__aarch64_cpu_features = external dso_local global { i64 } -// CHECK: @fmv = weak_odr ifunc i32 (), ptr @fmv.resolver -// CHECK: @fmv_one = weak_odr ifunc i32 (), ptr @fmv_one.resolver -// CHECK: @fmv_two = weak_odr ifunc i32 (), ptr @fmv_two.resolver -// CHECK: @fmv_e = weak_odr ifunc i32 (), ptr @fmv_e.resolver -// CHECK: @fmv_d = internal ifunc i32 (), ptr @fmv_d.resolver -// CHECK: @fmv_default = weak_odr ifunc i32 (), ptr @fmv_default.resolver -// CHECK: @fmv_c = weak_odr ifunc void (), ptr @fmv_c.resolver -// CHECK: @fmv_inline = weak_odr ifunc i32 (), ptr @fmv_inline.resolver -// CHECK: @reca = weak_odr ifunc void (), ptr @reca.resolver -// CHECK: @unused_with_default_def = weak_odr ifunc i32 (), ptr @unused_with_default_def.resolver -// CHECK: @unused_with_implicit_default_def = weak_odr ifunc i32 (), ptr @unused_with_implicit_default_def.resolver -// CHECK: @unused_with_implicit_forward_default_def = weak_odr ifunc i32 (), ptr @unused_with_implicit_forward_default_def.resolver -// CHECK: @default_def_with_version_decls = weak_odr ifunc i32 (), ptr @default_def_with_version_decls.resolver -// CHECK: @recb = weak_odr ifunc void (), ptr @recb.resolver -//. -// CHECK: Function Attrs: noinline nounwind optnone -// CHECK-LABEL: define {{[^@]+}}@fmv._MflagmMfp16fmlMrng -// CHECK-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK-NEXT: entry: -// CHECK-NEXT: ret i32 1 -// -// -// CHECK: Function Attrs: noinline nounwind optnone -// CHECK-LABEL: define {{[^@]+}}@fmv._Mflagm2Msme-i16i64 -// CHECK-SAME: () #[[ATTR1:[0-9]+]] { -// CHECK-NEXT: entry: -// CHECK-NEXT: ret i32 2 -// -// -// CHECK: Function Attrs: noinline nounwind optnone -// CHECK-LABEL: define {{[^@]+}}@fmv._MlseMsha2 -// CHECK-SAME: () #[[ATTR2:[0-9]+]] { -// CHECK-NEXT: entry: -// CHECK-NEXT: ret i32 3 -// -// -// CHECK: Function Attrs: noinline nounwind optnone -// CHECK-LABEL: define {{[^@]+}}@fmv._MdotprodMwfxt -// CHECK-SAME: () #[[ATTR3:[0-9]+]] { -// CHECK-NEXT: entry: -// CHECK-NEXT: ret i32 4 -// -// -// CHECK: Function Attrs: noinline nounwind optnone -// CHECK-LABEL: define {{[^@]+}}@fmv._Mfp16fmlMmemtag -// CHECK-SAME: () #[[ATTR4:[0-9]+]] { -// CHECK-NEXT: entry: -// CHECK-NEXT: ret i32 5 -// -// -// CHECK: Function Attrs: noinline nounwind optnone -// CHECK-LABEL: define {{[^@]+}}@fmv._MaesMfp -// CHECK-SAME: () #[[ATTR5:[0-9]+]] { -// CHECK-NEXT: entry: -// CHECK-NEXT: ret i32 6 -// -// -// CHECK: Function Attrs: noinline nounwind optnone -// CHECK-LABEL: define {{[^@]+}}@fmv._McrcMwfxt -// CHECK-SAME: () #[[ATTR6:[0-9]+]] { -// CHECK-NEXT: entry: -// CHECK-NEXT: ret i32 7 -// -// -// CHECK: Function Attrs: noinline nounwind optnone -// CHECK-LABEL: define {{[^@]+}}@fmv._Mbti -// CHECK-SAME: () #[[ATTR7:[0-9]+]] { -// CHECK-NEXT: entry: -// CHECK-NEXT: ret i32 8 -// -// -// CHECK: Function Attrs: noinline nounwind optnone -// CHECK-LABEL: define {{[^@]+}}@fmv._Msme2 -// CHECK-SAME: () #[[ATTR8:[0-9]+]] { -// CHECK-NEXT: entry: -// CHECK-NEXT: ret i32 9 -// -// -// CHECK: Function Attrs: noinline nounwind optnone -// CHECK-LABEL: define {{[^@]+}}@fmv.default -// CHECK-SAME: () #[[ATTR9:[0-9]+]] { -// CHECK-NEXT: entry: -// CHECK-NEXT: ret i32 0 -// -// -// CHECK: Function Attrs: noinline nounwind optnone -// CHECK-LABEL: define {{[^@]+}}@fmv_one._MsimdMwfxt -// CHECK-SAME: () #[[ATTR10:[0-9]+]] { -// CHECK-NEXT: entry: -// CHECK-NEXT: ret i32 1 -// -// -// CHECK: Function Attrs: noinline nounwind optnone -// CHECK-LABEL: define {{[^@]+}}@fmv_one._Mdpb -// CHECK-SAME: () #[[ATTR11:[0-9]+]] { -// CHECK-NEXT: entry: -// CHECK-NEXT: ret i32 2 -// -// -// CHECK: Function Attrs: noinline nounwind optnone -// CHECK-LABEL: define {{[^@]+}}@fmv_one.default -// CHECK-SAME: () #[[ATTR9]] { -// CHECK-NEXT: entry: -// CHECK-NEXT: ret i32 0 -// -// -// CHECK: Function Attrs: noinline nounwind optnone -// CHECK-LABEL: define {{[^@]+}}@fmv_two._Mfp -// CHECK-SAME: () #[[ATTR12:[0-9]+]] { -// CHECK-NEXT: entry: -// CHECK-NEXT: ret i32 1 -// -// -// CHECK: Function Attrs: noinline nounwind optnone -// CHECK-LABEL: define {{[^@]+}}@fmv_two._Msimd -// CHECK-SAME: () #[[ATTR13:[0-9]+]] { -// CHECK-NEXT: entry: -// CHECK-NEXT: ret i32 2 -// -// -// CHECK: Function Attrs: noinline nounwind optnone -// CHECK-LABEL: define {{[^@]+}}@fmv_two._Mfp16Msimd -// CHECK-SAME: () #[[ATTR14:[0-9]+]] { -// CHECK-NEXT: entry: -// CHECK-NEXT: ret i32 4 -// -// -// CHECK: Function Attrs: noinline nounwind optnone -// CHECK-LABEL: define {{[^@]+}}@fmv_two.default -// CHECK-SAME: () #[[ATTR9]] { -// CHECK-NEXT: entry: -// CHECK-NEXT: ret i32 0 -// -// -// CHECK: Function Attrs: noinline nounwind optnone -// CHECK-LABEL: define {{[^@]+}}@foo -// CHECK-SAME: () #[[ATTR15:[0-9]+]] { -// CHECK-NEXT: entry: -// CHECK-NEXT: [[CALL:%.*]] = call i32 @fmv() -// CHECK-NEXT: [[CALL1:%.*]] = call i32 @fmv_one() -// CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[CALL]], [[CALL1]] -// CHECK-NEXT: [[CALL2:%.*]] = call i32 @fmv_two() -// CHECK-NEXT: [[ADD3:%.*]] = add nsw i32 [[ADD]], [[CALL2]] -// CHECK-NEXT: ret i32 [[ADD3]] -// -// -// CHECK: Function Attrs: noinline nounwind optnone -// CHECK-LABEL: define {{[^@]+}}@fmv_e.default -// CHECK-SAME: () #[[ATTR9]] { -// CHECK-NEXT: entry: -// CHECK-NEXT: ret i32 20 -// -// -// CHECK: Function Attrs: noinline nounwind optnone -// CHECK-LABEL: define {{[^@]+}}@fmv_default.default -// CHECK-SAME: () #[[ATTR9]] { -// CHECK-NEXT: entry: -// CHECK-NEXT: ret i32 111 -// -// -// CHECK: Function Attrs: noinline nounwind optnone -// CHECK-LABEL: define {{[^@]+}}@fmv_c._Mssbs -// CHECK-SAME: () #[[ATTR16:[0-9]+]] { -// CHECK-NEXT: entry: -// CHECK-NEXT: ret void -// -// -// CHECK: Function Attrs: noinline nounwind optnone -// CHECK-LABEL: define {{[^@]+}}@fmv_c.default -// CHECK-SAME: () #[[ATTR9]] { -// CHECK-NEXT: entry: -// CHECK-NEXT: ret void -// -// -// CHECK: Function Attrs: noinline nounwind optnone -// CHECK-LABEL: define {{[^@]+}}@goo -// CHECK-SAME: () #[[ATTR15]] { -// CHECK-NEXT: entry: -// CHECK-NEXT: [[CALL:%.*]] = call i32 @fmv_inline() -// CHECK-NEXT: [[CALL1:%.*]] = call i32 @fmv_e() -// CHECK-NEXT: [[CALL2:%.*]] = call i32 @fmv_d() -// CHECK-NEXT: call void @fmv_c() -// CHECK-NEXT: [[CALL3:%.*]] = call i32 @fmv_default() -// CHECK-NEXT: ret i32 [[CALL3]] -// -// -// CHECK: Function Attrs: noinline nounwind optnone -// CHECK-LABEL: define {{[^@]+}}@recur -// CHECK-SAME: () #[[ATTR15]] { -// CHECK-NEXT: entry: -// CHECK-NEXT: call void @reca() -// CHECK-NEXT: ret void -// -// -// CHECK: Function Attrs: noinline nounwind optnone -// CHECK-LABEL: define {{[^@]+}}@hoo -// CHECK-SAME: () #[[ATTR15]] { -// CHECK-NEXT: entry: -// CHECK-NEXT: [[FP1:%.*]] = alloca ptr, align 8 -// CHECK-NEXT: [[FP2:%.*]] = alloca ptr, align 8 -// CHECK-NEXT: call void @f(ptr noundef @fmv) -// CHECK-NEXT: store ptr @fmv, ptr [[FP1]], align 8 -// CHECK-NEXT: store ptr @fmv, ptr [[FP2]], align 8 -// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[FP1]], align 8 -// CHECK-NEXT: [[CALL:%.*]] = call i32 [[TMP0]]() -// CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr [[FP2]], align 8 -// CHECK-NEXT: [[CALL1:%.*]] = call i32 [[TMP1]]() -// CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[CALL]], [[CALL1]] -// CHECK-NEXT: ret i32 [[ADD]] -// -// -// CHECK: Function Attrs: noinline nounwind optnone -// CHECK-LABEL: define {{[^@]+}}@unused_with_forward_default_decl._Mmops -// CHECK-SAME: () #[[ATTR19:[0-9]+]] { -// CHECK-NEXT: entry: -// CHECK-NEXT: ret i32 0 -// -// -// CHECK: Function Attrs: noinline nounwind optnone -// CHECK-LABEL: define {{[^@]+}}@unused_with_implicit_extern_forward_default_decl._Mdotprod -// CHECK-SAME: () #[[ATTR20:[0-9]+]] { -// CHECK-NEXT: entry: -// CHECK-NEXT: ret i32 0 -// -// -// CHECK: Function Attrs: noinline nounwind optnone -// CHECK-LABEL: define {{[^@]+}}@unused_with_default_decl._Maes -// CHECK-SAME: () #[[ATTR21:[0-9]+]] { -// CHECK-NEXT: entry: -// CHECK-NEXT: ret i32 0 -// -// -// CHECK: Function Attrs: noinline nounwind optnone -// CHECK-LABEL: define {{[^@]+}}@unused_with_default_def._Msve -// CHECK-SAME: () #[[ATTR22:[0-9]+]] { -// CHECK-NEXT: entry: -// CHECK-NEXT: ret i32 0 -// -// -// CHECK: Function Attrs: noinline nounwind optnone -// CHECK-LABEL: define {{[^@]+}}@unused_with_default_def.default -// CHECK-SAME: () #[[ATTR9]] { -// CHECK-NEXT: entry: -// CHECK-NEXT: ret i32 1 -// -// -// CHECK: Function Attrs: noinline nounwind optnone -// CHECK-LABEL: define {{[^@]+}}@unused_with_implicit_default_def._Mfp16 -// CHECK-SAME: () #[[ATTR23:[0-9]+]] { -// CHECK-NEXT: entry: -// CHECK-NEXT: ret i32 0 -// -// -// CHECK: Function Attrs: noinline nounwind optnone -// CHECK-LABEL: define {{[^@]+}}@unused_with_implicit_default_def.default -// CHECK-SAME: () #[[ATTR9]] { -// CHECK-NEXT: entry: -// CHECK-NEXT: ret i32 1 -// -// -// CHECK: Function Attrs: noinline nounwind optnone -// CHECK-LABEL: define {{[^@]+}}@unused_with_implicit_forward_default_def.default -// CHECK-SAME: () #[[ATTR15]] { -// CHECK-NEXT: entry: -// CHECK-NEXT: ret i32 0 -// -// -// CHECK: Function Attrs: noinline nounwind optnone -// CHECK-LABEL: define {{[^@]+}}@unused_with_implicit_forward_default_def._Mlse -// CHECK-SAME: () #[[ATTR24:[0-9]+]] { -// CHECK-NEXT: entry: -// CHECK-NEXT: ret i32 1 -// -// -// CHECK: Function Attrs: noinline nounwind optnone -// CHECK-LABEL: define {{[^@]+}}@unused_without_default._Mrdm -// CHECK-SAME: () #[[ATTR25:[0-9]+]] { -// CHECK-NEXT: entry: -// CHECK-NEXT: ret i32 0 -// -// -// CHECK: Function Attrs: noinline nounwind optnone -// CHECK-LABEL: define {{[^@]+}}@default_def_with_version_decls.default -// CHECK-SAME: () #[[ATTR15]] { -// CHECK-NEXT: entry: -// CHECK-NEXT: ret i32 0 -// -// -// CHECK: Function Attrs: noinline nounwind optnone -// CHECK-LABEL: define {{[^@]+}}@used_def_without_default_decl._Mjscvt -// CHECK-SAME: () #[[ATTR27:[0-9]+]] { -// CHECK-NEXT: entry: -// CHECK-NEXT: ret i32 1 -// -// -// CHECK: Function Attrs: noinline nounwind optnone -// CHECK-LABEL: define {{[^@]+}}@used_def_without_default_decl._Mrdm -// CHECK-SAME: () #[[ATTR28:[0-9]+]] { -// CHECK-NEXT: entry: -// CHECK-NEXT: ret i32 2 -// -// -// CHECK: Function Attrs: noinline nounwind optnone -// CHECK-LABEL: define {{[^@]+}}@caller -// CHECK-SAME: () #[[ATTR15]] { -// CHECK-NEXT: entry: -// CHECK-NEXT: [[CALL:%.*]] = call i32 @used_def_without_default_decl() -// CHECK-NEXT: [[CALL1:%.*]] = call i32 @used_decl_without_default_decl() -// CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[CALL]], [[CALL1]] -// CHECK-NEXT: ret i32 [[ADD]] -// -// -// CHECK: Function Attrs: noinline nounwind optnone -// CHECK-LABEL: define {{[^@]+}}@main -// CHECK-SAME: () #[[ATTR9]] { -// CHECK-NEXT: entry: -// CHECK-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK-NEXT: store i32 0, ptr [[RETVAL]], align 4 -// CHECK-NEXT: call void @recur() -// CHECK-NEXT: [[CALL:%.*]] = call i32 @goo() -// CHECK-NEXT: ret i32 [[CALL]] -// -// -// CHECK-LABEL: define {{[^@]+}}@fmv.resolver() comdat { -// CHECK-NEXT: resolver_entry: -// CHECK-NEXT: call void @__init_cpu_features_resolver() -// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 -// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 144119586256651008 -// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 144119586256651008 -// CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]] -// CHECK-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]] -// CHECK: resolver_return: -// CHECK-NEXT: ret ptr @fmv._Msme2 -// CHECK: resolver_else: -// CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 -// CHECK-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 72061992218723078 -// CHECK-NEXT: [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 72061992218723078 -// CHECK-NEXT: [[TMP7:%.*]] = and i1 true, [[TMP6]] -// CHECK-NEXT: br i1 [[TMP7]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]] -// CHECK: resolver_return1: -// CHECK-NEXT: ret ptr @fmv._Mflagm2Msme-i16i64 -// CHECK: resolver_else2: -// CHECK-NEXT: [[TMP8:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 -// CHECK-NEXT: [[TMP9:%.*]] = and i64 [[TMP8]], 18014398509483008 -// CHECK-NEXT: [[TMP10:%.*]] = icmp eq i64 [[TMP9]], 18014398509483008 -// CHECK-NEXT: [[TMP11:%.*]] = and i1 true, [[TMP10]] -// CHECK-NEXT: br i1 [[TMP11]], label [[RESOLVER_RETURN3:%.*]], label [[RESOLVER_ELSE4:%.*]] -// CHECK: resolver_return3: -// CHECK-NEXT: ret ptr @fmv._McrcMwfxt -// CHECK: resolver_else4: -// CHECK-NEXT: [[TMP12:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 -// CHECK-NEXT: [[TMP13:%.*]] = and i64 [[TMP12]], 18014398509482768 -// CHECK-NEXT: [[TMP14:%.*]] = icmp eq i64 [[TMP13]], 18014398509482768 -// CHECK-NEXT: [[TMP15:%.*]] = and i1 true, [[TMP14]] -// CHECK-NEXT: br i1 [[TMP15]], label [[RESOLVER_RETURN5:%.*]], label [[RESOLVER_ELSE6:%.*]] -// CHECK: resolver_return5: -// CHECK-NEXT: ret ptr @fmv._MdotprodMwfxt -// CHECK: resolver_else6: -// CHECK-NEXT: [[TMP16:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 -// CHECK-NEXT: [[TMP17:%.*]] = and i64 [[TMP16]], 1125899906842624 -// CHECK-NEXT: [[TMP18:%.*]] = icmp eq i64 [[TMP17]], 1125899906842624 -// CHECK-NEXT: [[TMP19:%.*]] = and i1 true, [[TMP18]] -// CHECK-NEXT: br i1 [[TMP19]], label [[RESOLVER_RETURN7:%.*]], label [[RESOLVER_ELSE8:%.*]] -// CHECK: resolver_return7: -// CHECK-NEXT: ret ptr @fmv._Mbti -// CHECK: resolver_else8: -// CHECK-NEXT: [[TMP20:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 -// CHECK-NEXT: [[TMP21:%.*]] = and i64 [[TMP20]], 17592186110728 -// CHECK-NEXT: [[TMP22:%.*]] = icmp eq i64 [[TMP21]], 17592186110728 -// CHECK-NEXT: [[TMP23:%.*]] = and i1 true, [[TMP22]] -// CHECK-NEXT: br i1 [[TMP23]], label [[RESOLVER_RETURN9:%.*]], label [[RESOLVER_ELSE10:%.*]] -// CHECK: resolver_return9: -// CHECK-NEXT: ret ptr @fmv._Mfp16fmlMmemtag -// CHECK: resolver_else10: -// CHECK-NEXT: [[TMP24:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 -// CHECK-NEXT: [[TMP25:%.*]] = and i64 [[TMP24]], 66315 -// CHECK-NEXT: [[TMP26:%.*]] = icmp eq i64 [[TMP25]], 66315 -// CHECK-NEXT: [[TMP27:%.*]] = and i1 true, [[TMP26]] -// CHECK-NEXT: br i1 [[TMP27]], label [[RESOLVER_RETURN11:%.*]], label [[RESOLVER_ELSE12:%.*]] -// CHECK: resolver_return11: -// CHECK-NEXT: ret ptr @fmv._MflagmMfp16fmlMrng -// CHECK: resolver_else12: -// CHECK-NEXT: [[TMP28:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 -// CHECK-NEXT: [[TMP29:%.*]] = and i64 [[TMP28]], 33536 -// CHECK-NEXT: [[TMP30:%.*]] = icmp eq i64 [[TMP29]], 33536 -// CHECK-NEXT: [[TMP31:%.*]] = and i1 true, [[TMP30]] -// CHECK-NEXT: br i1 [[TMP31]], label [[RESOLVER_RETURN13:%.*]], label [[RESOLVER_ELSE14:%.*]] -// CHECK: resolver_return13: -// CHECK-NEXT: ret ptr @fmv._MaesMfp -// CHECK: resolver_else14: -// CHECK-NEXT: [[TMP32:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 -// CHECK-NEXT: [[TMP33:%.*]] = and i64 [[TMP32]], 4992 -// CHECK-NEXT: [[TMP34:%.*]] = icmp eq i64 [[TMP33]], 4992 -// CHECK-NEXT: [[TMP35:%.*]] = and i1 true, [[TMP34]] -// CHECK-NEXT: br i1 [[TMP35]], label [[RESOLVER_RETURN15:%.*]], label [[RESOLVER_ELSE16:%.*]] -// CHECK: resolver_return15: -// CHECK-NEXT: ret ptr @fmv._MlseMsha2 -// CHECK: resolver_else16: -// CHECK-NEXT: ret ptr @fmv.default -// -// -// CHECK-LABEL: define {{[^@]+}}@fmv_one.resolver() comdat { -// CHECK-NEXT: resolver_entry: -// CHECK-NEXT: call void @__init_cpu_features_resolver() -// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 -// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 18014398509482752 -// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 18014398509482752 -// CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]] -// CHECK-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]] -// CHECK: resolver_return: -// CHECK-NEXT: ret ptr @fmv_one._MsimdMwfxt -// CHECK: resolver_else: -// CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 -// CHECK-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 262144 -// CHECK-NEXT: [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 262144 -// CHECK-NEXT: [[TMP7:%.*]] = and i1 true, [[TMP6]] -// CHECK-NEXT: br i1 [[TMP7]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]] -// CHECK: resolver_return1: -// CHECK-NEXT: ret ptr @fmv_one._Mdpb -// CHECK: resolver_else2: -// CHECK-NEXT: ret ptr @fmv_one.default -// -// -// CHECK-LABEL: define {{[^@]+}}@fmv_two.resolver() comdat { -// CHECK-NEXT: resolver_entry: -// CHECK-NEXT: call void @__init_cpu_features_resolver() -// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 -// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 66304 -// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 66304 -// CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]] -// CHECK-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]] -// CHECK: resolver_return: -// CHECK-NEXT: ret ptr @fmv_two._Mfp16Msimd -// CHECK: resolver_else: -// CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 -// CHECK-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 768 -// CHECK-NEXT: [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 768 -// CHECK-NEXT: [[TMP7:%.*]] = and i1 true, [[TMP6]] -// CHECK-NEXT: br i1 [[TMP7]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]] -// CHECK: resolver_return1: -// CHECK-NEXT: ret ptr @fmv_two._Msimd -// CHECK: resolver_else2: -// CHECK-NEXT: [[TMP8:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 -// CHECK-NEXT: [[TMP9:%.*]] = and i64 [[TMP8]], 256 -// CHECK-NEXT: [[TMP10:%.*]] = icmp eq i64 [[TMP9]], 256 -// CHECK-NEXT: [[TMP11:%.*]] = and i1 true, [[TMP10]] -// CHECK-NEXT: br i1 [[TMP11]], label [[RESOLVER_RETURN3:%.*]], label [[RESOLVER_ELSE4:%.*]] -// CHECK: resolver_return3: -// CHECK-NEXT: ret ptr @fmv_two._Mfp -// CHECK: resolver_else4: -// CHECK-NEXT: ret ptr @fmv_two.default -// -// -// CHECK-LABEL: define {{[^@]+}}@fmv_e.resolver() comdat { -// CHECK-NEXT: resolver_entry: -// CHECK-NEXT: call void @__init_cpu_features_resolver() -// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 -// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 18014398509481984 -// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 18014398509481984 -// CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]] -// CHECK-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]] -// CHECK: resolver_return: -// CHECK-NEXT: ret ptr @fmv_e._Mwfxt -// CHECK: resolver_else: -// CHECK-NEXT: ret ptr @fmv_e.default -// -// -// CHECK: Function Attrs: noinline nounwind optnone -// CHECK-LABEL: define {{[^@]+}}@fmv_d._Msb -// CHECK-SAME: () #[[ATTR30:[0-9]+]] { -// CHECK-NEXT: entry: -// CHECK-NEXT: ret i32 0 -// -// -// CHECK: Function Attrs: noinline nounwind optnone -// CHECK-LABEL: define {{[^@]+}}@fmv_d.default -// CHECK-SAME: () #[[ATTR9]] { -// CHECK-NEXT: entry: -// CHECK-NEXT: ret i32 1 -// -// -// CHECK-LABEL: define {{[^@]+}}@fmv_d.resolver() { -// CHECK-NEXT: resolver_entry: -// CHECK-NEXT: call void @__init_cpu_features_resolver() -// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 -// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 70368744177664 -// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 70368744177664 -// CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]] -// CHECK-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]] -// CHECK: resolver_return: -// CHECK-NEXT: ret ptr @fmv_d._Msb -// CHECK: resolver_else: -// CHECK-NEXT: ret ptr @fmv_d.default -// -// -// CHECK-LABEL: define {{[^@]+}}@fmv_default.resolver() comdat { -// CHECK-NEXT: resolver_entry: -// CHECK-NEXT: ret ptr @fmv_default.default -// -// -// CHECK-LABEL: define {{[^@]+}}@fmv_c.resolver() comdat { -// CHECK-NEXT: resolver_entry: -// CHECK-NEXT: call void @__init_cpu_features_resolver() -// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 -// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 562949953421312 -// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 562949953421312 -// CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]] -// CHECK-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]] -// CHECK: resolver_return: -// CHECK-NEXT: ret ptr @fmv_c._Mssbs -// CHECK: resolver_else: -// CHECK-NEXT: ret ptr @fmv_c.default -// -// -// CHECK: Function Attrs: noinline nounwind optnone -// CHECK-LABEL: define {{[^@]+}}@fmv_inline._MaesMf64mmMsha2 -// CHECK-SAME: () #[[ATTR31:[0-9]+]] { -// CHECK-NEXT: entry: -// CHECK-NEXT: ret i32 1 -// -// -// CHECK: Function Attrs: noinline nounwind optnone -// CHECK-LABEL: define {{[^@]+}}@fmv_inline._MfcmaMfp16MrdmMsme -// CHECK-SAME: () #[[ATTR32:[0-9]+]] { -// CHECK-NEXT: entry: -// CHECK-NEXT: ret i32 2 -// -// -// CHECK: Function Attrs: noinline nounwind optnone -// CHECK-LABEL: define {{[^@]+}}@fmv_inline._Mf32mmMi8mmMsha3 -// CHECK-SAME: () #[[ATTR33:[0-9]+]] { -// CHECK-NEXT: entry: -// CHECK-NEXT: ret i32 12 -// -// -// CHECK: Function Attrs: noinline nounwind optnone -// CHECK-LABEL: define {{[^@]+}}@fmv_inline._Mbf16Mdit -// CHECK-SAME: () #[[ATTR34:[0-9]+]] { -// CHECK-NEXT: entry: -// CHECK-NEXT: ret i32 8 -// -// -// CHECK: Function Attrs: noinline nounwind optnone -// CHECK-LABEL: define {{[^@]+}}@fmv_inline._MdpbMrcpc2 -// CHECK-SAME: () #[[ATTR35:[0-9]+]] { -// CHECK-NEXT: entry: -// CHECK-NEXT: ret i32 6 -// -// -// CHECK: Function Attrs: noinline nounwind optnone -// CHECK-LABEL: define {{[^@]+}}@fmv_inline._Mdpb2Mjscvt -// CHECK-SAME: () #[[ATTR36:[0-9]+]] { -// CHECK-NEXT: entry: -// CHECK-NEXT: ret i32 7 -// -// -// CHECK: Function Attrs: noinline nounwind optnone -// CHECK-LABEL: define {{[^@]+}}@fmv_inline._MfrinttsMrcpc -// CHECK-SAME: () #[[ATTR37:[0-9]+]] { -// CHECK-NEXT: entry: -// CHECK-NEXT: ret i32 3 -// -// -// CHECK: Function Attrs: noinline nounwind optnone -// CHECK-LABEL: define {{[^@]+}}@fmv_inline._Mbf16Msve -// CHECK-SAME: () #[[ATTR38:[0-9]+]] { -// CHECK-NEXT: entry: -// CHECK-NEXT: ret i32 4 -// -// -// CHECK: Function Attrs: noinline nounwind optnone -// CHECK-LABEL: define {{[^@]+}}@fmv_inline._Msve2-aesMsve2-sha3 -// CHECK-SAME: () #[[ATTR39:[0-9]+]] { -// CHECK-NEXT: entry: -// CHECK-NEXT: ret i32 5 -// -// -// CHECK: Function Attrs: noinline nounwind optnone -// CHECK-LABEL: define {{[^@]+}}@fmv_inline._Msve2Msve2-aesMsve2-bitperm -// CHECK-SAME: () #[[ATTR40:[0-9]+]] { -// CHECK-NEXT: entry: -// CHECK-NEXT: ret i32 9 -// -// -// CHECK: Function Attrs: noinline nounwind optnone -// CHECK-LABEL: define {{[^@]+}}@fmv_inline._MmemtagMsve2-sm4 -// CHECK-SAME: () #[[ATTR41:[0-9]+]] { -// CHECK-NEXT: entry: -// CHECK-NEXT: ret i32 10 -// -// -// CHECK: Function Attrs: noinline nounwind optnone -// CHECK-LABEL: define {{[^@]+}}@fmv_inline._MmemtagMmopsMrcpc3 -// CHECK-SAME: () #[[ATTR42:[0-9]+]] { -// CHECK-NEXT: entry: -// CHECK-NEXT: ret i32 11 -// -// -// CHECK: Function Attrs: noinline nounwind optnone -// CHECK-LABEL: define {{[^@]+}}@fmv_inline._MaesMdotprod -// CHECK-SAME: () #[[ATTR43:[0-9]+]] { -// CHECK-NEXT: entry: -// CHECK-NEXT: ret i32 13 -// -// -// CHECK: Function Attrs: noinline nounwind optnone -// CHECK-LABEL: define {{[^@]+}}@fmv_inline._Mfp16fmlMsimd -// CHECK-SAME: () #[[ATTR44:[0-9]+]] { -// CHECK-NEXT: entry: -// CHECK-NEXT: ret i32 14 -// -// -// CHECK: Function Attrs: noinline nounwind optnone -// CHECK-LABEL: define {{[^@]+}}@fmv_inline._MfpMsm4 -// CHECK-SAME: () #[[ATTR45:[0-9]+]] { -// CHECK-NEXT: entry: -// CHECK-NEXT: ret i32 15 -// -// -// CHECK: Function Attrs: noinline nounwind optnone -// CHECK-LABEL: define {{[^@]+}}@fmv_inline._MlseMrdm -// CHECK-SAME: () #[[ATTR46:[0-9]+]] { -// CHECK-NEXT: entry: -// CHECK-NEXT: ret i32 16 -// -// -// CHECK: Function Attrs: noinline nounwind optnone -// CHECK-LABEL: define {{[^@]+}}@fmv_inline.default -// CHECK-SAME: () #[[ATTR9]] { -// CHECK-NEXT: entry: -// CHECK-NEXT: ret i32 3 -// -// -// CHECK-LABEL: define {{[^@]+}}@fmv_inline.resolver() comdat { -// CHECK-NEXT: resolver_entry: -// CHECK-NEXT: call void @__init_cpu_features_resolver() -// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 -// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 864708720653762560 -// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 864708720653762560 -// CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]] -// CHECK-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]] -// CHECK: resolver_return: -// CHECK-NEXT: ret ptr @fmv_inline._MmemtagMmopsMrcpc3 -// CHECK: resolver_else: -// CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 -// CHECK-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 19861002584864 -// CHECK-NEXT: [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 19861002584864 -// CHECK-NEXT: [[TMP7:%.*]] = and i1 true, [[TMP6]] -// CHECK-NEXT: br i1 [[TMP7]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]] -// CHECK: resolver_return1: -// CHECK-NEXT: ret ptr @fmv_inline._MmemtagMsve2-sm4 -// CHECK: resolver_else2: -// CHECK-NEXT: [[TMP8:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 -// CHECK-NEXT: [[TMP9:%.*]] = and i64 [[TMP8]], 4398182892352 -// CHECK-NEXT: [[TMP10:%.*]] = icmp eq i64 [[TMP9]], 4398182892352 -// CHECK-NEXT: [[TMP11:%.*]] = and i1 true, [[TMP10]] -// CHECK-NEXT: br i1 [[TMP11]], label [[RESOLVER_RETURN3:%.*]], label [[RESOLVER_ELSE4:%.*]] -// CHECK: resolver_return3: -// CHECK-NEXT: ret ptr @fmv_inline._MfcmaMfp16MrdmMsme -// CHECK: resolver_else4: -// CHECK-NEXT: [[TMP12:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 -// CHECK-NEXT: [[TMP13:%.*]] = and i64 [[TMP12]], 1444182864640 -// CHECK-NEXT: [[TMP14:%.*]] = icmp eq i64 [[TMP13]], 1444182864640 -// CHECK-NEXT: [[TMP15:%.*]] = and i1 true, [[TMP14]] -// CHECK-NEXT: br i1 [[TMP15]], label [[RESOLVER_RETURN5:%.*]], label [[RESOLVER_ELSE6:%.*]] -// CHECK: resolver_return5: -// CHECK-NEXT: ret ptr @fmv_inline._Msve2-aesMsve2-sha3 -// CHECK: resolver_else6: -// CHECK-NEXT: [[TMP16:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 -// CHECK-NEXT: [[TMP17:%.*]] = and i64 [[TMP16]], 894427038464 -// CHECK-NEXT: [[TMP18:%.*]] = icmp eq i64 [[TMP17]], 894427038464 -// CHECK-NEXT: [[TMP19:%.*]] = and i1 true, [[TMP18]] -// CHECK-NEXT: br i1 [[TMP19]], label [[RESOLVER_RETURN7:%.*]], label [[RESOLVER_ELSE8:%.*]] -// CHECK: resolver_return7: -// CHECK-NEXT: ret ptr @fmv_inline._Msve2Msve2-aesMsve2-bitperm -// CHECK: resolver_else8: -// CHECK-NEXT: [[TMP20:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 -// CHECK-NEXT: [[TMP21:%.*]] = and i64 [[TMP20]], 35433583360 -// CHECK-NEXT: [[TMP22:%.*]] = icmp eq i64 [[TMP21]], 35433583360 -// CHECK-NEXT: [[TMP23:%.*]] = and i1 true, [[TMP22]] -// CHECK-NEXT: br i1 [[TMP23]], label [[RESOLVER_RETURN9:%.*]], label [[RESOLVER_ELSE10:%.*]] -// CHECK: resolver_return9: -// CHECK-NEXT: ret ptr @fmv_inline._MaesMf64mmMsha2 -// CHECK: resolver_else10: -// CHECK-NEXT: [[TMP24:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 -// CHECK-NEXT: [[TMP25:%.*]] = and i64 [[TMP24]], 18320798464 -// CHECK-NEXT: [[TMP26:%.*]] = icmp eq i64 [[TMP25]], 18320798464 -// CHECK-NEXT: [[TMP27:%.*]] = and i1 true, [[TMP26]] -// CHECK-NEXT: br i1 [[TMP27]], label [[RESOLVER_RETURN11:%.*]], label [[RESOLVER_ELSE12:%.*]] -// CHECK: resolver_return11: -// CHECK-NEXT: ret ptr @fmv_inline._Mf32mmMi8mmMsha3 -// CHECK: resolver_else12: -// CHECK-NEXT: [[TMP28:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 -// CHECK-NEXT: [[TMP29:%.*]] = and i64 [[TMP28]], 1208025856 -// CHECK-NEXT: [[TMP30:%.*]] = icmp eq i64 [[TMP29]], 1208025856 -// CHECK-NEXT: [[TMP31:%.*]] = and i1 true, [[TMP30]] -// CHECK-NEXT: br i1 [[TMP31]], label [[RESOLVER_RETURN13:%.*]], label [[RESOLVER_ELSE14:%.*]] -// CHECK: resolver_return13: -// CHECK-NEXT: ret ptr @fmv_inline._Mbf16Msve -// CHECK: resolver_else14: -// CHECK-NEXT: [[TMP32:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 -// CHECK-NEXT: [[TMP33:%.*]] = and i64 [[TMP32]], 134349568 -// CHECK-NEXT: [[TMP34:%.*]] = icmp eq i64 [[TMP33]], 134349568 -// CHECK-NEXT: [[TMP35:%.*]] = and i1 true, [[TMP34]] -// CHECK-NEXT: br i1 [[TMP35]], label [[RESOLVER_RETURN15:%.*]], label [[RESOLVER_ELSE16:%.*]] -// CHECK: resolver_return15: -// CHECK-NEXT: ret ptr @fmv_inline._Mbf16Mdit -// CHECK: resolver_else16: -// CHECK-NEXT: [[TMP36:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 -// CHECK-NEXT: [[TMP37:%.*]] = and i64 [[TMP36]], 20971776 -// CHECK-NEXT: [[TMP38:%.*]] = icmp eq i64 [[TMP37]], 20971776 -// CHECK-NEXT: [[TMP39:%.*]] = and i1 true, [[TMP38]] -// CHECK-NEXT: br i1 [[TMP39]], label [[RESOLVER_RETURN17:%.*]], label [[RESOLVER_ELSE18:%.*]] -// CHECK: resolver_return17: -// CHECK-NEXT: ret ptr @fmv_inline._MfrinttsMrcpc -// CHECK: resolver_else18: -// CHECK-NEXT: [[TMP40:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 -// CHECK-NEXT: [[TMP41:%.*]] = and i64 [[TMP40]], 12845056 -// CHECK-NEXT: [[TMP42:%.*]] = icmp eq i64 [[TMP41]], 12845056 -// CHECK-NEXT: [[TMP43:%.*]] = and i1 true, [[TMP42]] -// CHECK-NEXT: br i1 [[TMP43]], label [[RESOLVER_RETURN19:%.*]], label [[RESOLVER_ELSE20:%.*]] -// CHECK: resolver_return19: -// CHECK-NEXT: ret ptr @fmv_inline._MdpbMrcpc2 -// CHECK: resolver_else20: -// CHECK-NEXT: [[TMP44:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 -// CHECK-NEXT: [[TMP45:%.*]] = and i64 [[TMP44]], 1835264 -// CHECK-NEXT: [[TMP46:%.*]] = icmp eq i64 [[TMP45]], 1835264 -// CHECK-NEXT: [[TMP47:%.*]] = and i1 true, [[TMP46]] -// CHECK-NEXT: br i1 [[TMP47]], label [[RESOLVER_RETURN21:%.*]], label [[RESOLVER_ELSE22:%.*]] -// CHECK: resolver_return21: -// CHECK-NEXT: ret ptr @fmv_inline._Mdpb2Mjscvt -// CHECK: resolver_else22: -// CHECK-NEXT: [[TMP48:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 -// CHECK-NEXT: [[TMP49:%.*]] = and i64 [[TMP48]], 66312 -// CHECK-NEXT: [[TMP50:%.*]] = icmp eq i64 [[TMP49]], 66312 -// CHECK-NEXT: [[TMP51:%.*]] = and i1 true, [[TMP50]] -// CHECK-NEXT: br i1 [[TMP51]], label [[RESOLVER_RETURN23:%.*]], label [[RESOLVER_ELSE24:%.*]] -// CHECK: resolver_return23: -// CHECK-NEXT: ret ptr @fmv_inline._Mfp16fmlMsimd -// CHECK: resolver_else24: -// CHECK-NEXT: [[TMP52:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 -// CHECK-NEXT: [[TMP53:%.*]] = and i64 [[TMP52]], 33552 -// CHECK-NEXT: [[TMP54:%.*]] = icmp eq i64 [[TMP53]], 33552 -// CHECK-NEXT: [[TMP55:%.*]] = and i1 true, [[TMP54]] -// CHECK-NEXT: br i1 [[TMP55]], label [[RESOLVER_RETURN25:%.*]], label [[RESOLVER_ELSE26:%.*]] -// CHECK: resolver_return25: -// CHECK-NEXT: ret ptr @fmv_inline._MaesMdotprod -// CHECK: resolver_else26: -// CHECK-NEXT: [[TMP56:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 -// CHECK-NEXT: [[TMP57:%.*]] = and i64 [[TMP56]], 960 -// CHECK-NEXT: [[TMP58:%.*]] = icmp eq i64 [[TMP57]], 960 -// CHECK-NEXT: [[TMP59:%.*]] = and i1 true, [[TMP58]] -// CHECK-NEXT: br i1 [[TMP59]], label [[RESOLVER_RETURN27:%.*]], label [[RESOLVER_ELSE28:%.*]] -// CHECK: resolver_return27: -// CHECK-NEXT: ret ptr @fmv_inline._MlseMrdm -// CHECK: resolver_else28: -// CHECK-NEXT: [[TMP60:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 -// CHECK-NEXT: [[TMP61:%.*]] = and i64 [[TMP60]], 800 -// CHECK-NEXT: [[TMP62:%.*]] = icmp eq i64 [[TMP61]], 800 -// CHECK-NEXT: [[TMP63:%.*]] = and i1 true, [[TMP62]] -// CHECK-NEXT: br i1 [[TMP63]], label [[RESOLVER_RETURN29:%.*]], label [[RESOLVER_ELSE30:%.*]] -// CHECK: resolver_return29: -// CHECK-NEXT: ret ptr @fmv_inline._MfpMsm4 -// CHECK: resolver_else30: -// CHECK-NEXT: ret ptr @fmv_inline.default -// -// -// CHECK: Function Attrs: noinline nounwind optnone -// CHECK-LABEL: define {{[^@]+}}@reca.default -// CHECK-SAME: () #[[ATTR9]] { -// CHECK-NEXT: entry: -// CHECK-NEXT: call void @recb() -// CHECK-NEXT: ret void -// -// -// CHECK-LABEL: define {{[^@]+}}@reca.resolver() comdat { -// CHECK-NEXT: resolver_entry: -// CHECK-NEXT: ret ptr @reca.default -// -// -// CHECK-LABEL: define {{[^@]+}}@unused_with_default_def.resolver() comdat { -// CHECK-NEXT: resolver_entry: -// CHECK-NEXT: call void @__init_cpu_features_resolver() -// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 -// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 1073807616 -// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 1073807616 -// CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]] -// CHECK-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]] -// CHECK: resolver_return: -// CHECK-NEXT: ret ptr @unused_with_default_def._Msve -// CHECK: resolver_else: -// CHECK-NEXT: ret ptr @unused_with_default_def.default -// -// -// CHECK-LABEL: define {{[^@]+}}@unused_with_implicit_default_def.resolver() comdat { -// CHECK-NEXT: resolver_entry: -// CHECK-NEXT: call void @__init_cpu_features_resolver() -// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 -// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 65792 -// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 65792 -// CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]] -// CHECK-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]] -// CHECK: resolver_return: -// CHECK-NEXT: ret ptr @unused_with_implicit_default_def._Mfp16 -// CHECK: resolver_else: -// CHECK-NEXT: ret ptr @unused_with_implicit_default_def.default -// -// -// CHECK-LABEL: define {{[^@]+}}@unused_with_implicit_forward_default_def.resolver() comdat { -// CHECK-NEXT: resolver_entry: -// CHECK-NEXT: call void @__init_cpu_features_resolver() -// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 -// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 128 -// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 128 -// CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]] -// CHECK-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]] -// CHECK: resolver_return: -// CHECK-NEXT: ret ptr @unused_with_implicit_forward_default_def._Mlse -// CHECK: resolver_else: -// CHECK-NEXT: ret ptr @unused_with_implicit_forward_default_def.default -// -// -// CHECK-LABEL: define {{[^@]+}}@default_def_with_version_decls.resolver() comdat { -// CHECK-NEXT: resolver_entry: -// CHECK-NEXT: call void @__init_cpu_features_resolver() -// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 -// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 1048832 -// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 1048832 -// CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]] -// CHECK-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]] -// CHECK: resolver_return: -// CHECK-NEXT: ret ptr @default_def_with_version_decls._Mjscvt -// CHECK: resolver_else: -// CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 -// CHECK-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 832 -// CHECK-NEXT: [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 832 -// CHECK-NEXT: [[TMP7:%.*]] = and i1 true, [[TMP6]] -// CHECK-NEXT: br i1 [[TMP7]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]] -// CHECK: resolver_return1: -// CHECK-NEXT: ret ptr @default_def_with_version_decls._Mrdm -// CHECK: resolver_else2: -// CHECK-NEXT: ret ptr @default_def_with_version_decls.default -// -// -// CHECK: Function Attrs: noinline nounwind optnone -// CHECK-LABEL: define {{[^@]+}}@recb.default -// CHECK-SAME: () #[[ATTR9]] { -// CHECK-NEXT: entry: -// CHECK-NEXT: call void @func() -// CHECK-NEXT: ret void -// -// -// CHECK: Function Attrs: noinline nounwind optnone -// CHECK-LABEL: define {{[^@]+}}@func -// CHECK-SAME: () #[[ATTR15]] { -// CHECK-NEXT: entry: -// CHECK-NEXT: ret void -// -// -// CHECK-LABEL: define {{[^@]+}}@recb.resolver() comdat { -// CHECK-NEXT: resolver_entry: -// CHECK-NEXT: ret ptr @recb.default -// -// -// CHECK-NOFMV: Function Attrs: noinline nounwind optnone -// CHECK-NOFMV-LABEL: define {{[^@]+}}@foo -// CHECK-NOFMV-SAME: () #[[ATTR0:[0-9]+]] { -// CHECK-NOFMV-NEXT: entry: -// CHECK-NOFMV-NEXT: [[CALL:%.*]] = call i32 @fmv() -// CHECK-NOFMV-NEXT: [[CALL1:%.*]] = call i32 @fmv_one() -// CHECK-NOFMV-NEXT: [[ADD:%.*]] = add nsw i32 [[CALL]], [[CALL1]] -// CHECK-NOFMV-NEXT: [[CALL2:%.*]] = call i32 @fmv_two() -// CHECK-NOFMV-NEXT: [[ADD3:%.*]] = add nsw i32 [[ADD]], [[CALL2]] -// CHECK-NOFMV-NEXT: ret i32 [[ADD3]] -// -// -// CHECK-NOFMV: Function Attrs: noinline nounwind optnone -// CHECK-NOFMV-LABEL: define {{[^@]+}}@fmv -// CHECK-NOFMV-SAME: () #[[ATTR1:[0-9]+]] { -// CHECK-NOFMV-NEXT: entry: -// CHECK-NOFMV-NEXT: ret i32 0 -// -// -// CHECK-NOFMV: Function Attrs: noinline nounwind optnone -// CHECK-NOFMV-LABEL: define {{[^@]+}}@fmv_one -// CHECK-NOFMV-SAME: () #[[ATTR1]] { -// CHECK-NOFMV-NEXT: entry: -// CHECK-NOFMV-NEXT: ret i32 0 -// -// -// CHECK-NOFMV: Function Attrs: noinline nounwind optnone -// CHECK-NOFMV-LABEL: define {{[^@]+}}@fmv_two -// CHECK-NOFMV-SAME: () #[[ATTR1]] { -// CHECK-NOFMV-NEXT: entry: -// CHECK-NOFMV-NEXT: ret i32 0 -// -// -// CHECK-NOFMV: Function Attrs: noinline nounwind optnone -// CHECK-NOFMV-LABEL: define {{[^@]+}}@fmv_e -// CHECK-NOFMV-SAME: () #[[ATTR0]] { -// CHECK-NOFMV-NEXT: entry: -// CHECK-NOFMV-NEXT: ret i32 20 -// -// -// CHECK-NOFMV: Function Attrs: noinline nounwind optnone -// CHECK-NOFMV-LABEL: define {{[^@]+}}@goo -// CHECK-NOFMV-SAME: () #[[ATTR0]] { -// CHECK-NOFMV-NEXT: entry: -// CHECK-NOFMV-NEXT: [[CALL:%.*]] = call i32 @fmv_inline() -// CHECK-NOFMV-NEXT: [[CALL1:%.*]] = call i32 @fmv_e() -// CHECK-NOFMV-NEXT: [[CALL2:%.*]] = call i32 @fmv_d() -// CHECK-NOFMV-NEXT: call void @fmv_c() -// CHECK-NOFMV-NEXT: [[CALL3:%.*]] = call i32 @fmv_default() -// CHECK-NOFMV-NEXT: ret i32 [[CALL3]] -// -// -// CHECK-NOFMV: Function Attrs: noinline nounwind optnone -// CHECK-NOFMV-LABEL: define {{[^@]+}}@fmv_d -// CHECK-NOFMV-SAME: () #[[ATTR1]] { -// CHECK-NOFMV-NEXT: entry: -// CHECK-NOFMV-NEXT: ret i32 1 -// -// -// CHECK-NOFMV: Function Attrs: noinline nounwind optnone -// CHECK-NOFMV-LABEL: define {{[^@]+}}@fmv_c -// CHECK-NOFMV-SAME: () #[[ATTR1]] { -// CHECK-NOFMV-NEXT: entry: -// CHECK-NOFMV-NEXT: ret void -// -// -// CHECK-NOFMV: Function Attrs: noinline nounwind optnone -// CHECK-NOFMV-LABEL: define {{[^@]+}}@fmv_default -// CHECK-NOFMV-SAME: () #[[ATTR1]] { -// CHECK-NOFMV-NEXT: entry: -// CHECK-NOFMV-NEXT: ret i32 111 -// -// -// CHECK-NOFMV: Function Attrs: noinline nounwind optnone -// CHECK-NOFMV-LABEL: define {{[^@]+}}@recur -// CHECK-NOFMV-SAME: () #[[ATTR0]] { -// CHECK-NOFMV-NEXT: entry: -// CHECK-NOFMV-NEXT: call void @reca() -// CHECK-NOFMV-NEXT: ret void -// -// -// CHECK-NOFMV: Function Attrs: noinline nounwind optnone -// CHECK-NOFMV-LABEL: define {{[^@]+}}@hoo -// CHECK-NOFMV-SAME: () #[[ATTR0]] { -// CHECK-NOFMV-NEXT: entry: -// CHECK-NOFMV-NEXT: [[FP1:%.*]] = alloca ptr, align 8 -// CHECK-NOFMV-NEXT: [[FP2:%.*]] = alloca ptr, align 8 -// CHECK-NOFMV-NEXT: call void @f(ptr noundef @fmv) -// CHECK-NOFMV-NEXT: store ptr @fmv, ptr [[FP1]], align 8 -// CHECK-NOFMV-NEXT: store ptr @fmv, ptr [[FP2]], align 8 -// CHECK-NOFMV-NEXT: [[TMP0:%.*]] = load ptr, ptr [[FP1]], align 8 -// CHECK-NOFMV-NEXT: [[CALL:%.*]] = call i32 [[TMP0]]() -// CHECK-NOFMV-NEXT: [[TMP1:%.*]] = load ptr, ptr [[FP2]], align 8 -// CHECK-NOFMV-NEXT: [[CALL1:%.*]] = call i32 [[TMP1]]() -// CHECK-NOFMV-NEXT: [[ADD:%.*]] = add nsw i32 [[CALL]], [[CALL1]] -// CHECK-NOFMV-NEXT: ret i32 [[ADD]] -// -// -// CHECK-NOFMV: Function Attrs: noinline nounwind optnone -// CHECK-NOFMV-LABEL: define {{[^@]+}}@unused_with_implicit_default_def -// CHECK-NOFMV-SAME: () #[[ATTR0]] { -// CHECK-NOFMV-NEXT: entry: -// CHECK-NOFMV-NEXT: ret i32 1 -// -// -// CHECK-NOFMV: Function Attrs: noinline nounwind optnone -// CHECK-NOFMV-LABEL: define {{[^@]+}}@unused_with_implicit_forward_default_def -// CHECK-NOFMV-SAME: () #[[ATTR0]] { -// CHECK-NOFMV-NEXT: entry: -// CHECK-NOFMV-NEXT: ret i32 0 -// -// -// CHECK-NOFMV: Function Attrs: noinline nounwind optnone -// CHECK-NOFMV-LABEL: define {{[^@]+}}@default_def_with_version_decls -// CHECK-NOFMV-SAME: () #[[ATTR0]] { -// CHECK-NOFMV-NEXT: entry: -// CHECK-NOFMV-NEXT: ret i32 0 -// -// -// CHECK-NOFMV: Function Attrs: noinline nounwind optnone -// CHECK-NOFMV-LABEL: define {{[^@]+}}@main -// CHECK-NOFMV-SAME: () #[[ATTR1]] { -// CHECK-NOFMV-NEXT: entry: -// CHECK-NOFMV-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK-NOFMV-NEXT: store i32 0, ptr [[RETVAL]], align 4 -// CHECK-NOFMV-NEXT: call void @recur() -// CHECK-NOFMV-NEXT: [[CALL:%.*]] = call i32 @goo() -// CHECK-NOFMV-NEXT: ret i32 [[CALL]] -// -// -// CHECK-NOFMV: Function Attrs: noinline nounwind optnone -// CHECK-NOFMV-LABEL: define {{[^@]+}}@unused_with_default_def -// CHECK-NOFMV-SAME: () #[[ATTR1]] { -// CHECK-NOFMV-NEXT: entry: -// CHECK-NOFMV-NEXT: ret i32 1 -// -//. -// CHECK: [[META0:![0-9]+]] = !{i32 1, !"wchar_size", i32 4} -// CHECK: [[META1:![0-9]+]] = !{!"{{.*}}clang version {{.*}}"} -//. -// CHECK-NOFMV: [[META0:![0-9]+]] = !{i32 1, !"wchar_size", i32 4} -// CHECK-NOFMV: [[META1:![0-9]+]] = !{!"{{.*}}clang version {{.*}}"} -//. _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
