Author: Sam Elliott Date: 2025-02-26T20:03:02-08:00 New Revision: 5066d7b60186fe0d557223493a17c3aa9a06f58f
URL: https://github.com/llvm/llvm-project/commit/5066d7b60186fe0d557223493a17c3aa9a06f58f DIFF: https://github.com/llvm/llvm-project/commit/5066d7b60186fe0d557223493a17c3aa9a06f58f.diff LOG: [RISCV] Add Xqccmp 0.1 Assembly Support (#128731) Xqccmp is a new spec by Qualcomm that makes a vendor-specific effort to solve the push/pop + frame pointers issue. Broadly, it takes the Zcmp instructions and reverse the order they push/pop registers in, which ends up matching the frame pointer convention. This extension adds a new instruction not present in Zcmp, `qc.cm.pushfp`, which will set `fp` to the incoming `sp` value after it has pushed the registers. This change duplicates the Zcmp implementation, with minor changes to mnemonics (for the `qc.` prefix), predicates, and the addition of `qc.cm.pushfp`. There is also new logic to prevent combining Xqccmp and Zcmp. Xqccmp is kept separate to Xqci for decoding/encoding etc, as the specs are separate today. Specification: https://github.com/quic/riscv-unified-db/releases/tag/Xqccmp_extension-0.1.0 Added: llvm/lib/Target/RISCV/RISCVInstrInfoXqccmp.td llvm/test/MC/RISCV/rv32xqccmp-invalid.s llvm/test/MC/RISCV/rv32xqccmp-valid.s llvm/test/MC/RISCV/rv64e-xqccmp-valid.s llvm/test/MC/RISCV/rv64xqccmp-invalid.s llvm/test/MC/RISCV/rv64xqccmp-valid.s Modified: clang/test/Driver/print-supported-extensions-riscv.c llvm/docs/RISCVUsage.rst llvm/docs/ReleaseNotes.md llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp llvm/lib/Target/RISCV/RISCVFeatures.td llvm/lib/Target/RISCV/RISCVInstrInfo.td llvm/lib/Target/RISCV/RISCVInstrInfoZc.td llvm/lib/TargetParser/RISCVISAInfo.cpp llvm/test/CodeGen/RISCV/attributes.ll llvm/unittests/TargetParser/RISCVISAInfoTest.cpp Removed: ################################################################################ diff --git a/clang/test/Driver/print-supported-extensions-riscv.c b/clang/test/Driver/print-supported-extensions-riscv.c index 40f4ee8d2c89a..4d6e112f4e387 100644 --- a/clang/test/Driver/print-supported-extensions-riscv.c +++ b/clang/test/Driver/print-supported-extensions-riscv.c @@ -193,6 +193,7 @@ // CHECK-NEXT: smctr 1.0 'Smctr' (Control Transfer Records Machine Level) // CHECK-NEXT: ssctr 1.0 'Ssctr' (Control Transfer Records Supervisor Level) // CHECK-NEXT: svukte 0.3 'Svukte' (Address-Independent Latency of User-Mode Faults to Supervisor Addresses) +// CHECK-NEXT: xqccmp 0.1 'Xqccmp' (Qualcomm 16-bit Push/Pop and Double Moves) // CHECK-NEXT: xqcia 0.4 'Xqcia' (Qualcomm uC Arithmetic Extension) // CHECK-NEXT: xqciac 0.3 'Xqciac' (Qualcomm uC Load-Store Address Calculation Extension) // CHECK-NEXT: xqcicli 0.2 'Xqcicli' (Qualcomm uC Conditional Load Immediate Extension) diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst index 50d642e841185..63185fe67440c 100644 --- a/llvm/docs/RISCVUsage.rst +++ b/llvm/docs/RISCVUsage.rst @@ -429,6 +429,9 @@ The current vendor extensions supported are: ``Xwchc`` LLVM implements `the custom compressed opcodes present in some QingKe cores` by WCH / Nanjing Qinheng Microelectronics. The vendor refers to these opcodes by the name "XW". +``experimental-Xqccmp`` + LLVM implements `version 0.1 of the 16-bit Push/Pop instructions and double-moves extension specification <https://github.com/quic/riscv-unified-db/releases/tag/Xqccmp_extension-0.1.0>`__ by Qualcomm. All instructions are prefixed with `qc.` as described in the specification. + ``experimental-Xqcia`` LLVM implements `version 0.4 of the Qualcomm uC Arithmetic extension specification <https://github.com/quic/riscv-unified-db/releases/latest>`__ by Qualcomm. All instructions are prefixed with `qc.` as described in the specification. These instructions are only available for riscv32. diff --git a/llvm/docs/ReleaseNotes.md b/llvm/docs/ReleaseNotes.md index 2a617901a1146..12dd09ad41135 100644 --- a/llvm/docs/ReleaseNotes.md +++ b/llvm/docs/ReleaseNotes.md @@ -109,6 +109,8 @@ Changes to the RISC-V Backend * Adds experimental assembler support for the Qualcomm uC 'Xqcilia` (Large Immediate Arithmetic) extension. +* Adds experimental assembler support for the Qualcomm 'Xqccmp' extension, which + is a frame-pointer convention compatible version of Zcmp. Changes to the WebAssembly Backend ---------------------------------- diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp index 650ad48e50de0..36e2fa0262f9d 100644 --- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp +++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp @@ -1682,6 +1682,17 @@ bool RISCVAsmParser::matchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, case Match_InvalidRnumArg: { return generateImmOutOfRangeError(Operands, ErrorInfo, 0, 10); } + case Match_InvalidStackAdj: { + SMLoc ErrorLoc = ((RISCVOperand &)*Operands[ErrorInfo]).getStartLoc(); + StringRef SpecName = "Zc"; + if (getSTI().hasFeature(RISCV::FeatureVendorXqccmp)) + SpecName = "Xqccmp"; + + return Error(ErrorLoc, + Twine("stack adjustment is invalid for this instruction") + + " and register list; refer to " + SpecName + + " spec for a detailed range of stack adjustment"); + } } if (const char *MatchDiag = getMatchKindDiag((RISCVMatchResultTy)Result)) { @@ -3640,7 +3651,7 @@ bool RISCVAsmParser::validateInstruction(MCInst &Inst, } } - if (Opcode == RISCV::CM_MVSA01) { + if (Opcode == RISCV::CM_MVSA01 || Opcode == RISCV::QC_CM_MVSA01) { MCRegister Rd1 = Inst.getOperand(0).getReg(); MCRegister Rd2 = Inst.getOperand(1).getReg(); if (Rd1 == Rd2) { diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp index 08e0cfee809bc..e99df34908d6e 100644 --- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp +++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp @@ -748,7 +748,9 @@ DecodeStatus RISCVDisassembler::getInstruction16(MCInst &MI, uint64_t &Size, TRY_TO_DECODE_FEATURE_ANY(XqciFeatureGroup, DecoderTableXqci16, "Qualcomm uC 16bit"); - + TRY_TO_DECODE_FEATURE( + RISCV::FeatureVendorXqccmp, DecoderTableXqccmp16, + "Xqccmp (Qualcomm 16-bit Push/Pop & Double Move Instructions)"); TRY_TO_DECODE_AND_ADD_SP(STI.hasFeature(RISCV::FeatureVendorXwchc), DecoderTableXwchc16, "WCH QingKe XW"); TRY_TO_DECODE_AND_ADD_SP(true, DecoderTable16, diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td index a8c36052da2d0..24828cde28079 100644 --- a/llvm/lib/Target/RISCV/RISCVFeatures.td +++ b/llvm/lib/Target/RISCV/RISCVFeatures.td @@ -1374,6 +1374,14 @@ def HasVendorXqcilo AssemblerPredicate<(all_of FeatureVendorXqcilo), "'Xqcilo' (Qualcomm uC Large Offset Load Store Extension)">; +def FeatureVendorXqccmp + : RISCVExperimentalExtension<0, 1, + "Qualcomm 16-bit Push/Pop and Double Moves", + [FeatureStdExtZca]>; +def HasVendorXqccmp : Predicate<"Subtarget->hasVendorXqccmp()">, + AssemblerPredicate<(all_of FeatureVendorXqccmp), + "'Xqccmp' (Qualcomm 16-bit Push/Pop and Double Moves)">; + // Rivos Extension(s) def FeatureVendorXRivosVisni diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td index c775561dd2d2d..a4e420ed8fcf3 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td @@ -2153,6 +2153,7 @@ include "RISCVInstrInfoSFB.td" include "RISCVInstrInfoXCV.td" include "RISCVInstrInfoXwch.td" include "RISCVInstrInfoXqci.td" +include "RISCVInstrInfoXqccmp.td" include "RISCVInstrInfoXMips.td" include "RISCVInstrInfoXRivos.td" diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXqccmp.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXqccmp.td new file mode 100644 index 0000000000000..5bb9c1e4b228b --- /dev/null +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXqccmp.td @@ -0,0 +1,95 @@ +//===---------------- RISCVInstrInfoXqccmp.td --------------*- tablegen -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// This file describes Qualcomm's Xqccmp extension. +// +// Xqccmp is broadly equivalent to (and incompatible with) Zcmp except the +// following changes: +// +// - The registers are pushed in the opposite order, so `ra` and `fp` are +// closest to the incoming stack pointer (to be compatible with the +// frame-pointer convention), and +// +// - There is a new `qc.cm.pushfp` instruction which is `qc.cm.push` but it sets +// `fp` to the incoming stack pointer value, as expected by the frame-pointer +// convention. +// +//===----------------------------------------------------------------------===// + +//===----------------------------------------------------------------------===// +// Operand and SDNode transformation definitions. +//===----------------------------------------------------------------------===// + +//===----------------------------------------------------------------------===// +// Instruction Formats +//===----------------------------------------------------------------------===// + +//===----------------------------------------------------------------------===// +// Instruction Class Templates +//===----------------------------------------------------------------------===// + +//===----------------------------------------------------------------------===// +// Instructions +//===----------------------------------------------------------------------===// + +let DecoderNamespace = "Xqccmp", Predicates = [HasVendorXqccmp] in { + +let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in { +let Defs = [X10, X11] in +def QC_CM_MVA01S : RVInst16CA<0b101011, 0b11, 0b10, (outs), + (ins SR07:$rs1, SR07:$rs2), "qc.cm.mva01s", "$rs1, $rs2">, + Sched<[WriteIALU, WriteIALU, ReadIALU, ReadIALU]>; + +let Uses = [X10, X11] in +def QC_CM_MVSA01 : RVInst16CA<0b101011, 0b01, 0b10, (outs SR07:$rs1, SR07:$rs2), + (ins), "qc.cm.mvsa01", "$rs1, $rs2">, + Sched<[WriteIALU, WriteIALU, ReadIALU, ReadIALU]>; +} // hasSideEffects = 0, mayLoad = 0, mayStore = 0 + +let hasSideEffects = 0, mayLoad = 0, mayStore = 1, Uses = [X2], Defs = [X2] in +def QC_CM_PUSH : RVInstZcCPPP<0b11000, "qc.cm.push", negstackadj>, + Sched<[WriteIALU, ReadIALU, ReadStoreData, ReadStoreData, + ReadStoreData, ReadStoreData, ReadStoreData, ReadStoreData, + ReadStoreData, ReadStoreData, ReadStoreData, ReadStoreData, + ReadStoreData, ReadStoreData, ReadStoreData]>; + +let hasSideEffects = 0, mayLoad = 0, mayStore = 1, Uses = [X2], Defs = [X2, X8] in +def QC_CM_PUSHFP : RVInstZcCPPP<0b11001, "qc.cm.pushfp", negstackadj>, + Sched<[WriteIALU, WriteIALU, ReadIALU, ReadStoreData, ReadStoreData, + ReadStoreData, ReadStoreData, ReadStoreData, ReadStoreData, + ReadStoreData, ReadStoreData, ReadStoreData, ReadStoreData, + ReadStoreData, ReadStoreData, ReadStoreData]>; + +let hasSideEffects = 0, mayLoad = 1, mayStore = 0, isReturn = 1, + Uses = [X2], Defs = [X2] in +def QC_CM_POPRET : RVInstZcCPPP<0b11110, "qc.cm.popret">, + Sched<[WriteIALU, WriteLDW, WriteLDW, WriteLDW, WriteLDW, + WriteLDW, WriteLDW, WriteLDW, WriteLDW, WriteLDW, + WriteLDW, WriteLDW, WriteLDW, WriteLDW, ReadIALU]>; + +let hasSideEffects = 0, mayLoad = 1, mayStore = 0, isReturn = 1, + Uses = [X2], Defs = [X2, X10] in +def QC_CM_POPRETZ : RVInstZcCPPP<0b11100, "qc.cm.popretz">, + Sched<[WriteIALU, WriteIALU, WriteLDW, WriteLDW, WriteLDW, + WriteLDW, WriteLDW, WriteLDW, WriteLDW, WriteLDW, + WriteLDW, WriteLDW, WriteLDW, WriteLDW, WriteLDW, + ReadIALU]>; + +let hasSideEffects = 0, mayLoad = 1, mayStore = 0, + Uses = [X2], Defs = [X2] in +def QC_CM_POP : RVInstZcCPPP<0b11010, "qc.cm.pop">, + Sched<[WriteIALU, WriteLDW, WriteLDW, WriteLDW, WriteLDW, + WriteLDW, WriteLDW, WriteLDW, WriteLDW, WriteLDW, WriteLDW, + WriteLDW, WriteLDW, WriteLDW, ReadIALU]>; + +} // DecoderNamespace = "Xqccmp", Predicates = [HasVendorXqccmp] + +//===----------------------------------------------------------------------===// +// Aliases +//===----------------------------------------------------------------------===// + diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZc.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZc.td index 1740ebb239217..b5e3e6a3a8bbf 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoZc.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZc.td @@ -46,8 +46,6 @@ def StackAdjAsmOperand : AsmOperandClass { let Name = "StackAdj"; let ParserMethod = "parseZcmpStackAdj"; let DiagnosticType = "InvalidStackAdj"; - let DiagnosticString = "stack adjustment is invalid for this instruction and register list; " - "refer to Zc spec for a detailed range of stack adjustment"; let PredicateMethod = "isSpimm"; let RenderMethod = "addSpimmOperands"; } diff --git a/llvm/lib/TargetParser/RISCVISAInfo.cpp b/llvm/lib/TargetParser/RISCVISAInfo.cpp index 132c47ca631b6..932db759cb7ac 100644 --- a/llvm/lib/TargetParser/RISCVISAInfo.cpp +++ b/llvm/lib/TargetParser/RISCVISAInfo.cpp @@ -745,6 +745,8 @@ Error RISCVISAInfo::checkDependency() { {"xqcia"}, {"xqciac"}, {"xqcicli"}, {"xqcicm"}, {"xqcics"}, {"xqcicsr"}, {"xqciint"}, {"xqcilia"}, {"xqcilo"}, {"xqcilsm"}, {"xqcisls"}}; + bool HasZcmp = Exts.count("zcmp") != 0; + bool HasXqccmp = Exts.count("xqccmp") != 0; if (HasI && HasE) return getIncompatibleError("i", "e"); @@ -779,6 +781,9 @@ Error RISCVISAInfo::checkDependency() { if (Exts.count(Ext.str()) && (XLen != 32)) return getError("'" + Twine(Ext) + "'" + " is only supported for 'rv32'"); + if (HasZcmp && HasXqccmp) + return getIncompatibleError("zcmp", "xqccmp"); + return Error::success(); } diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll index 037b9c3d06764..29f84dc79b6ae 100644 --- a/llvm/test/CodeGen/RISCV/attributes.ll +++ b/llvm/test/CodeGen/RISCV/attributes.ll @@ -81,6 +81,7 @@ ; RUN: llc -mtriple=riscv32 -mattr=+xtheadmempair %s -o - | FileCheck --check-prefix=RV32XTHEADMEMPAIR %s ; RUN: llc -mtriple=riscv32 -mattr=+xtheadsync %s -o - | FileCheck --check-prefix=RV32XTHEADSYNC %s ; RUN: llc -mtriple=riscv32 -mattr=+xwchc %s -o - | FileCheck --check-prefix=RV32XWCHC %s +; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqccmp %s -o - | FileCheck --check-prefix=RV32XQCCMP %s ; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcia %s -o - | FileCheck --check-prefix=RV32XQCIA %s ; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqciac %s -o - | FileCheck --check-prefix=RV32XQCIAC %s ; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcicli %s -o - | FileCheck --check-prefix=RV32XQCICLI %s @@ -302,6 +303,8 @@ ; RUN: llc -mtriple=riscv64 -mattr=+experimental-ssctr %s -o - | FileCheck --check-prefix=RV64SSCTR %s ; RUN: llc -mtriple=riscv64 -mattr=+experimental-sdext %s -o - | FileCheck --check-prefix=RV64SDEXT %s ; RUN: llc -mtriple=riscv64 -mattr=+experimental-sdtrig %s -o - | FileCheck --check-prefix=RV64SDTRIG %s +; RUN: llc -mtriple=riscv64 -mattr=+experimental-xqccmp %s -o - | FileCheck --check-prefix=RV64XQCCMP %s + ; Tests for profile features. ; RUN: llc -mtriple=riscv32 -mattr=+rvi20u32 %s -o - | FileCheck --check-prefix=RVI20U32 %s @@ -398,6 +401,7 @@ ; RV32XTHEADMEMPAIR: .attribute 5, "rv32i2p1_xtheadmempair1p0" ; RV32XTHEADSYNC: .attribute 5, "rv32i2p1_xtheadsync1p0" ; RV32XWCHC: .attribute 5, "rv32i2p1_xwchc2p2" +; RV32XQCCMP: .attribute 5, "rv32i2p1_zca1p0_xqccmp0p1" ; RV32XQCIA: .attribute 5, "rv32i2p1_xqcia0p4" ; RV32XQCIAC: .attribute 5, "rv32i2p1_zca1p0_xqciac0p3" ; RV32XQCICLI: .attribute 5, "rv32i2p1_xqcicli0p2" @@ -617,6 +621,7 @@ ; RV64SSCTR: .attribute 5, "rv64i2p1_sscsrind1p0_ssctr1p0" ; RV64SDEXT: .attribute 5, "rv64i2p1_sdext1p0" ; RV64SDTRIG: .attribute 5, "rv64i2p1_sdtrig1p0" +; RV64XQCCMP: .attribute 5, "rv64i2p1_zca1p0_xqccmp0p1" ; RVI20U32: .attribute 5, "rv32i2p1" ; RVI20U64: .attribute 5, "rv64i2p1" diff --git a/llvm/test/MC/RISCV/rv32xqccmp-invalid.s b/llvm/test/MC/RISCV/rv32xqccmp-invalid.s new file mode 100644 index 0000000000000..899979cb4c601 --- /dev/null +++ b/llvm/test/MC/RISCV/rv32xqccmp-invalid.s @@ -0,0 +1,35 @@ +# RUN: not llvm-mc -triple=riscv32 -mattr=+experimental-xqccmp -M no-aliases -show-encoding < %s 2>&1 \ +# RUN: | FileCheck -check-prefixes=CHECK-ERROR %s + +# CHECK-ERROR: error: invalid operand for instruction +qc.cm.mvsa01 a1, a2 + +# CHECK-ERROR: error: rs1 and rs2 must be diff erent +qc.cm.mvsa01 s0, s0 + +# CHECK-ERROR: error: invalid operand for instruction +qc.cm.mva01s a1, a2 + +# CHECK-ERROR: error: invalid register list, {ra, s0-s10} or {x1, x8-x9, x18-x26} is not supported +qc.cm.popretz {ra, s0-s10}, 112 + +# CHECK-ERROR: error: stack adjustment is invalid for this instruction and register list; refer to Xqccmp spec for a detailed range of stack adjustment +qc.cm.popretz {ra, s0-s1}, 112 + +# CHECK-ERROR: error: stack adjustment is invalid for this instruction and register list; refer to Xqccmp spec for a detailed range of stack adjustment +qc.cm.push {ra}, 16 + +# CHECK-ERROR: error: stack adjustment is invalid for this instruction and register list; refer to Xqccmp spec for a detailed range of stack adjustment +qc.cm.pushfp {ra, s0}, 16 + +# CHECK-ERROR: error: stack adjustment is invalid for this instruction and register list; refer to Xqccmp spec for a detailed range of stack adjustment +qc.cm.pop {ra, s0-s1}, -32 + +# CHECK-ERROR: error: stack adjustment is invalid for this instruction and register list; refer to Xqccmp spec for a detailed range of stack adjustment +qc.cm.push {ra}, -8 + +# CHECK-ERROR: error: stack adjustment is invalid for this instruction and register list; refer to Xqccmp spec for a detailed range of stack adjustment +qc.cm.pushfp {ra, s0}, -12 + +# CHECK-ERROR: error: stack adjustment is invalid for this instruction and register list; refer to Xqccmp spec for a detailed range of stack adjustment +qc.cm.pop {ra, s0-s1}, -40 diff --git a/llvm/test/MC/RISCV/rv32xqccmp-valid.s b/llvm/test/MC/RISCV/rv32xqccmp-valid.s new file mode 100644 index 0000000000000..5827777e524ca --- /dev/null +++ b/llvm/test/MC/RISCV/rv32xqccmp-valid.s @@ -0,0 +1,353 @@ +# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-xqccmp -M no-aliases -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s +# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-xqccmp < %s \ +# RUN: | llvm-objdump --mattr=-c,+experimental-xqccmp -M no-aliases -d -r - \ +# RUN: | FileCheck --check-prefixes=CHECK-ASM-AND-OBJ %s + +# CHECK-ASM-AND-OBJ: qc.cm.mvsa01 s1, s0 +# CHECK-ASM: encoding: [0xa2,0xac] +qc.cm.mvsa01 s1, s0 + +# CHECK-ASM-AND-OBJ: qc.cm.mva01s s1, s0 +# CHECK-ASM: encoding: [0xe2,0xac] +qc.cm.mva01s s1, s0 + +# CHECK-ASM-AND-OBJ: qc.cm.mva01s s0, s0 +# CHECK-ASM: encoding: [0x62,0xac] +qc.cm.mva01s s0, s0 + +# CHECK-ASM-AND-OBJ: qc.cm.popret {ra}, 16 +# CHECK-ASM: encoding: [0x42,0xbe] +qc.cm.popret {ra}, 16 + +# CHECK-ASM-AND-OBJ: qc.cm.popret {ra}, 16 +# CHECK-ASM: encoding: [0x42,0xbe] +qc.cm.popret {x1}, 16 + +# CHECK-ASM-AND-OBJ: qc.cm.popret {ra}, 32 +# CHECK-ASM: encoding: [0x46,0xbe] +qc.cm.popret {ra}, 32 + +# CHECK-ASM-AND-OBJ: qc.cm.popret {ra}, 32 +# CHECK-ASM: encoding: [0x46,0xbe] +qc.cm.popret {x1}, 32 + +# CHECK-ASM-AND-OBJ: qc.cm.popret {ra, s0}, 64 +# CHECK-ASM: encoding: [0x5e,0xbe] +qc.cm.popret {ra, s0}, 64 + +# CHECK-ASM-AND-OBJ: qc.cm.popret {ra, s0}, 64 +# CHECK-ASM: encoding: [0x5e,0xbe] +qc.cm.popret {x1, x8}, 64 + +# CHECK-ASM-AND-OBJ: qc.cm.popret {ra, s0-s1}, 16 +# CHECK-ASM: encoding: [0x62,0xbe] +qc.cm.popret {ra,s0-s1}, 16 + +# CHECK-ASM-AND-OBJ: qc.cm.popret {ra, s0-s1}, 16 +# CHECK-ASM: encoding: [0x62,0xbe] +qc.cm.popret {x1, x8-x9}, 16 + +# CHECK-ASM-AND-OBJ: qc.cm.popret {ra, s0-s2}, 32 +# CHECK-ASM: encoding: [0x76,0xbe] +qc.cm.popret {ra, s0-s2}, 32 + +# CHECK-ASM-AND-OBJ: qc.cm.popret {ra, s0-s2}, 32 +# CHECK-ASM: encoding: [0x76,0xbe] +qc.cm.popret {x1, x8-x9, x18}, 32 + +# CHECK-ASM-AND-OBJ: qc.cm.popret {ra, s0-s3}, 32 +# CHECK-ASM: encoding: [0x82,0xbe] +qc.cm.popret {ra, s0-s3}, 32 + +# CHECK-ASM-AND-OBJ: qc.cm.popret {ra, s0-s3}, 32 +# CHECK-ASM: encoding: [0x82,0xbe] +qc.cm.popret {x1, x8-x9, x18-x19}, 32 + +# CHECK-ASM-AND-OBJ: qc.cm.popret {ra, s0-s5}, 32 +# CHECK-ASM: encoding: [0xa2,0xbe] +qc.cm.popret {ra, s0-s5}, 32 + +# CHECK-ASM-AND-OBJ: qc.cm.popret {ra, s0-s5}, 32 +# CHECK-ASM: encoding: [0xa2,0xbe] +qc.cm.popret {x1, x8-x9, x18-x21}, 32 + +# CHECK-ASM-AND-OBJ: qc.cm.popret {ra, s0-s7}, 48 +# CHECK-ASM: encoding: [0xc2,0xbe] +qc.cm.popret {ra, s0-s7}, 48 + +# CHECK-ASM-AND-OBJ: qc.cm.popret {ra, s0-s7}, 48 +# CHECK-ASM: encoding: [0xc2,0xbe] +qc.cm.popret {x1, x8-x9, x18-x23}, 48 + +# CHECK-ASM-AND-OBJ: qc.cm.popret {ra, s0-s11}, 112 +# CHECK-ASM: encoding: [0xfe,0xbe] +qc.cm.popret {ra, s0-s11}, 112 + +# CHECK-ASM-AND-OBJ: qc.cm.popret {ra, s0-s11}, 112 +# CHECK-ASM: encoding: [0xfe,0xbe] +qc.cm.popret {x1, x8-x9, x18-x27}, 112 + +# CHECK-ASM-AND-OBJ: qc.cm.popretz {ra}, 16 +# CHECK-ASM: encoding: [0x42,0xbc] +qc.cm.popretz {ra}, 16 + +# CHECK-ASM-AND-OBJ: qc.cm.popretz {ra}, 16 +# CHECK-ASM: encoding: [0x42,0xbc] +qc.cm.popretz {x1}, 16 + +# CHECK-ASM-AND-OBJ: qc.cm.popretz {ra}, 32 +# CHECK-ASM: encoding: [0x46,0xbc] +qc.cm.popretz {ra}, 32 + +# CHECK-ASM-AND-OBJ: qc.cm.popretz {ra}, 32 +# CHECK-ASM: encoding: [0x46,0xbc] +qc.cm.popretz {x1}, 32 + +# CHECK-ASM-AND-OBJ: qc.cm.popretz {ra, s0}, 64 +# CHECK-ASM: encoding: [0x5e,0xbc] +qc.cm.popretz {ra, s0}, 64 + +# CHECK-ASM-AND-OBJ: qc.cm.popretz {ra, s0}, 64 +# CHECK-ASM: encoding: [0x5e,0xbc] +qc.cm.popretz {x1, x8}, 64 + +# CHECK-ASM-AND-OBJ: qc.cm.popretz {ra, s0-s1}, 16 +# CHECK-ASM: encoding: [0x62,0xbc] +qc.cm.popretz {ra, s0-s1}, 16 + +# CHECK-ASM-AND-OBJ: qc.cm.popretz {ra, s0-s1}, 16 +# CHECK-ASM: encoding: [0x62,0xbc] +qc.cm.popretz {x1, x8-x9}, 16 + +# CHECK-ASM-AND-OBJ: qc.cm.popretz {ra, s0-s2}, 32 +# CHECK-ASM: encoding: [0x76,0xbc] +qc.cm.popretz {ra, s0-s2}, 32 + +# CHECK-ASM-AND-OBJ: qc.cm.popretz {ra, s0-s2}, 32 +# CHECK-ASM: encoding: [0x76,0xbc] +qc.cm.popretz {x1, x8-x9, x18}, 32 + +# CHECK-ASM-AND-OBJ: qc.cm.popretz {ra, s0-s3}, 32 +# CHECK-ASM: encoding: [0x82,0xbc] +qc.cm.popretz {ra, s0-s3}, 32 + +# CHECK-ASM-AND-OBJ: qc.cm.popretz {ra, s0-s3}, 32 +# CHECK-ASM: encoding: [0x82,0xbc] +qc.cm.popretz {x1, x8-x9, x18-x19}, 32 + +# CHECK-ASM-AND-OBJ: qc.cm.popretz {ra, s0-s5}, 32 +# CHECK-ASM: encoding: [0xa2,0xbc] +qc.cm.popretz {ra, s0-s5}, 32 + +# CHECK-ASM-AND-OBJ: qc.cm.popretz {ra, s0-s5}, 32 +# CHECK-ASM: encoding: [0xa2,0xbc] +qc.cm.popretz {x1, x8-x9, x18-x21}, 32 + +# CHECK-ASM-AND-OBJ: qc.cm.popretz {ra, s0-s7}, 48 +# CHECK-ASM: encoding: [0xc2,0xbc] +qc.cm.popretz {ra, s0-s7}, 48 + +# CHECK-ASM-AND-OBJ: qc.cm.popretz {ra, s0-s7}, 48 +# CHECK-ASM: encoding: [0xc2,0xbc] +qc.cm.popretz {x1, x8-x9, x18-x23}, 48 + +# CHECK-ASM-AND-OBJ: qc.cm.popretz {ra, s0-s11}, 112 +# CHECK-ASM: encoding: [0xfe,0xbc] +qc.cm.popretz {ra, s0-s11}, 112 + +# CHECK-ASM-AND-OBJ: qc.cm.popretz {ra, s0-s11}, 112 +# CHECK-ASM: encoding: [0xfe,0xbc] +qc.cm.popretz {x1, x8-x9, x18-x27}, 112 + +# CHECK-ASM-AND-OBJ: qc.cm.pop {ra}, 16 +# CHECK-ASM: encoding: [0x42,0xba] +qc.cm.pop {ra}, 16 + +# CHECK-ASM-AND-OBJ: qc.cm.pop {ra}, 16 +# CHECK-ASM: encoding: [0x42,0xba] +qc.cm.pop {x1}, 16 + +# CHECK-ASM-AND-OBJ: qc.cm.pop {ra}, 32 +# CHECK-ASM: encoding: [0x46,0xba] +qc.cm.pop {ra}, 32 + +# CHECK-ASM-AND-OBJ: qc.cm.pop {ra}, 32 +# CHECK-ASM: encoding: [0x46,0xba] +qc.cm.pop {x1}, 32 + +# CHECK-ASM-AND-OBJ: qc.cm.pop {ra, s0}, 16 +# CHECK-ASM: encoding: [0x52,0xba] +qc.cm.pop {ra, s0}, 16 + +# CHECK-ASM-AND-OBJ: qc.cm.pop {ra, s0}, 16 +# CHECK-ASM: encoding: [0x52,0xba] +qc.cm.pop {x1, x8}, 16 + +# CHECK-ASM-AND-OBJ: qc.cm.pop {ra, s0-s1}, 32 +# CHECK-ASM: encoding: [0x66,0xba] +qc.cm.pop {ra, s0-s1}, 32 + +# CHECK-ASM-AND-OBJ: qc.cm.pop {ra, s0-s1}, 32 +# CHECK-ASM: encoding: [0x66,0xba] +qc.cm.pop {x1, x8-x9}, 32 + +# CHECK-ASM-AND-OBJ: qc.cm.pop {ra, s0-s2}, 32 +# CHECK-ASM: encoding: [0x76,0xba] +qc.cm.pop {ra, s0-s2}, 32 + +# CHECK-ASM-AND-OBJ: qc.cm.pop {ra, s0-s2}, 32 +# CHECK-ASM: encoding: [0x76,0xba] +qc.cm.pop {x1, x8-x9, x18}, 32 + +# CHECK-ASM-AND-OBJ: qc.cm.pop {ra, s0-s5}, 32 +# CHECK-ASM: encoding: [0xa2,0xba] +qc.cm.pop {ra, s0-s5}, 32 + +# CHECK-ASM-AND-OBJ: qc.cm.pop {ra, s0-s5}, 32 +# CHECK-ASM: encoding: [0xa2,0xba] +qc.cm.pop {x1, x8-x9, x18-x21}, 32 + +# CHECK-ASM-AND-OBJ: qc.cm.pop {ra, s0-s7}, 48 +# CHECK-ASM: encoding: [0xc2,0xba] +qc.cm.pop {ra, s0-s7}, 48 + +# CHECK-ASM-AND-OBJ: qc.cm.pop {ra, s0-s7}, 48 +# CHECK-ASM: encoding: [0xc2,0xba] +qc.cm.pop {x1, x8-x9, x18-x23}, 48 + +# CHECK-ASM-AND-OBJ: qc.cm.pop {ra, s0-s11}, 64 +# CHECK-ASM: encoding: [0xf2,0xba] +qc.cm.pop {ra, s0-s11}, 64 + +# CHECK-ASM-AND-OBJ: qc.cm.pop {ra, s0-s11}, 64 +# CHECK-ASM: encoding: [0xf2,0xba] +qc.cm.pop {x1, x8-x9, x18-x27}, 64 + +# CHECK-ASM-AND-OBJ: qc.cm.push {ra}, -16 +# CHECK-ASM: encoding: [0x42,0xb8] +qc.cm.push {ra}, -16 + +# CHECK-ASM-AND-OBJ: qc.cm.push {ra}, -16 +# CHECK-ASM: encoding: [0x42,0xb8] +qc.cm.push {x1}, -16 + +# CHECK-ASM-AND-OBJ: qc.cm.push {ra, s0}, -32 +# CHECK-ASM: encoding: [0x56,0xb8] +qc.cm.push {ra, s0}, -32 + +# CHECK-ASM-AND-OBJ: qc.cm.push {ra, s0}, -32 +# CHECK-ASM: encoding: [0x56,0xb8] +qc.cm.push {x1, x8}, -32 + +# CHECK-ASM-AND-OBJ: qc.cm.push {ra, s0-s1}, -16 +# CHECK-ASM: encoding: [0x62,0xb8] +qc.cm.push {ra, s0-s1}, -16 + +# CHECK-ASM-AND-OBJ: qc.cm.push {ra, s0-s1}, -16 +# CHECK-ASM: encoding: [0x62,0xb8] +qc.cm.push {x1, x8-x9}, -16 + +# CHECK-ASM-AND-OBJ: qc.cm.push {ra, s0-s3}, -32 +# CHECK-ASM: encoding: [0x82,0xb8] +qc.cm.push {ra, s0-s3}, -32 + +# CHECK-ASM-AND-OBJ: qc.cm.push {ra, s0-s3}, -32 +# CHECK-ASM: encoding: [0x82,0xb8] +qc.cm.push {x1, x8-x9, x18-x19}, -32 + +# CHECK-ASM-AND-OBJ: qc.cm.push {ra, s0-s7}, -48 +# CHECK-ASM: encoding: [0xc2,0xb8] +qc.cm.push {ra, s0-s7}, -48 + +# CHECK-ASM-AND-OBJ: qc.cm.push {ra, s0-s7}, -48 +# CHECK-ASM: encoding: [0xc2,0xb8] +qc.cm.push {x1, x8-x9, x18-x23}, -48 + +# CHECK-ASM-AND-OBJ: qc.cm.push {ra, s0-s7}, -64 +# CHECK-ASM: encoding: [0xc6,0xb8] +qc.cm.push {ra, s0-s7}, -64 + +# CHECK-ASM-AND-OBJ: qc.cm.push {ra, s0-s7}, -64 +# CHECK-ASM: encoding: [0xc6,0xb8] +qc.cm.push {x1, x8-x9, x18-x23}, -64 + +# CHECK-ASM-AND-OBJ: qc.cm.push {ra, s0-s11}, -80 +# CHECK-ASM: encoding: [0xf6,0xb8] +qc.cm.push {ra, s0-s11}, -80 + +# CHECK-ASM-AND-OBJ: qc.cm.push {ra, s0-s11}, -80 +# CHECK-ASM: encoding: [0xf6,0xb8] +qc.cm.push {x1, x8-x9, x18-x27}, -80 + +# CHECK-ASM-AND-OBJ: qc.cm.push {ra, s0-s11}, -112 +# CHECK-ASM: encoding: [0xfe,0xb8] +qc.cm.push {ra, s0-s11}, -112 + +# CHECK-ASM-AND-OBJ: qc.cm.push {ra, s0-s11}, -112 +# CHECK-ASM: encoding: [0xfe,0xb8] +qc.cm.push {x1, x8-x9, x18-x27}, -112 + +# CHECK-ASM-AND-OBJ: qc.cm.pushfp {ra}, -16 +# CHECK-ASM: encoding: [0x42,0xb9] +qc.cm.pushfp {ra}, -16 + +# CHECK-ASM-AND-OBJ: qc.cm.pushfp {ra}, -16 +# CHECK-ASM: encoding: [0x42,0xb9] +qc.cm.pushfp {x1}, -16 + +# CHECK-ASM-AND-OBJ: qc.cm.pushfp {ra, s0}, -32 +# CHECK-ASM: encoding: [0x56,0xb9] +qc.cm.pushfp {ra, s0}, -32 + +# CHECK-ASM-AND-OBJ: qc.cm.pushfp {ra, s0}, -32 +# CHECK-ASM: encoding: [0x56,0xb9] +qc.cm.pushfp {x1, x8}, -32 + +# CHECK-ASM-AND-OBJ: qc.cm.pushfp {ra, s0-s1}, -16 +# CHECK-ASM: encoding: [0x62,0xb9] +qc.cm.pushfp {ra, s0-s1}, -16 + +# CHECK-ASM-AND-OBJ: qc.cm.pushfp {ra, s0-s1}, -16 +# CHECK-ASM: encoding: [0x62,0xb9] +qc.cm.pushfp {x1, x8-x9}, -16 + +# CHECK-ASM-AND-OBJ: qc.cm.pushfp {ra, s0-s3}, -32 +# CHECK-ASM: encoding: [0x82,0xb9] +qc.cm.pushfp {ra, s0-s3}, -32 + +# CHECK-ASM-AND-OBJ: qc.cm.pushfp {ra, s0-s3}, -32 +# CHECK-ASM: encoding: [0x82,0xb9] +qc.cm.pushfp {x1, x8-x9, x18-x19}, -32 + +# CHECK-ASM-AND-OBJ: qc.cm.pushfp {ra, s0-s7}, -48 +# CHECK-ASM: encoding: [0xc2,0xb9] +qc.cm.pushfp {ra, s0-s7}, -48 + +# CHECK-ASM-AND-OBJ: qc.cm.pushfp {ra, s0-s7}, -48 +# CHECK-ASM: encoding: [0xc2,0xb9] +qc.cm.pushfp {x1, x8-x9, x18-x23}, -48 + +# CHECK-ASM-AND-OBJ: qc.cm.pushfp {ra, s0-s7}, -64 +# CHECK-ASM: encoding: [0xc6,0xb9] +qc.cm.pushfp {ra, s0-s7}, -64 + +# CHECK-ASM-AND-OBJ: qc.cm.pushfp {ra, s0-s7}, -64 +# CHECK-ASM: encoding: [0xc6,0xb9] +qc.cm.pushfp {x1, x8-x9, x18-x23}, -64 + +# CHECK-ASM-AND-OBJ: qc.cm.pushfp {ra, s0-s11}, -80 +# CHECK-ASM: encoding: [0xf6,0xb9] +qc.cm.pushfp {ra, s0-s11}, -80 + +# CHECK-ASM-AND-OBJ: qc.cm.pushfp {ra, s0-s11}, -80 +# CHECK-ASM: encoding: [0xf6,0xb9] +qc.cm.pushfp {x1, x8-x9, x18-x27}, -80 + +# CHECK-ASM-AND-OBJ: qc.cm.pushfp {ra, s0-s11}, -112 +# CHECK-ASM: encoding: [0xfe,0xb9] +qc.cm.pushfp {ra, s0-s11}, -112 + +# CHECK-ASM-AND-OBJ: qc.cm.pushfp {ra, s0-s11}, -112 +# CHECK-ASM: encoding: [0xfe,0xb9] +qc.cm.pushfp {x1, x8-x9, x18-x27}, -112 diff --git a/llvm/test/MC/RISCV/rv64e-xqccmp-valid.s b/llvm/test/MC/RISCV/rv64e-xqccmp-valid.s new file mode 100644 index 0000000000000..8f9e3ce7ee533 --- /dev/null +++ b/llvm/test/MC/RISCV/rv64e-xqccmp-valid.s @@ -0,0 +1,85 @@ +# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-xqccmp,+e -M no-aliases -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s +# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-xqccmp < %s \ +# RUN: | llvm-objdump --mattr=-c,+experimental-xqccmp -M no-aliases -d -r - \ +# RUN: | FileCheck --check-prefixes=CHECK-ASM-AND-OBJ %s + +# CHECK-ASM-AND-OBJ: qc.cm.mvsa01 s1, s0 +# CHECK-ASM: encoding: [0xa2,0xac] +qc.cm.mvsa01 s1, s0 + +# CHECK-ASM-AND-OBJ: qc.cm.mva01s s1, s0 +# CHECK-ASM: encoding: [0xe2,0xac] +qc.cm.mva01s s1, s0 + +# CHECK-ASM-AND-OBJ: qc.cm.popret {ra}, 16 +# CHECK-ASM: encoding: [0x42,0xbe] +qc.cm.popret {ra}, 16 + +# CHECK-ASM-AND-OBJ: qc.cm.popret {ra}, 32 +# CHECK-ASM: encoding: [0x46,0xbe] +qc.cm.popret {ra}, 32 + +# CHECK-ASM-AND-OBJ: qc.cm.popret {ra, s0}, 64 +# CHECK-ASM: encoding: [0x5e,0xbe] +qc.cm.popret {ra, s0}, 64 + +# CHECK-ASM-AND-OBJ: qc.cm.popret {ra, s0-s1}, 32 +# CHECK-ASM: encoding: [0x62,0xbe] +qc.cm.popret {ra,s0-s1}, 32 + +# CHECK-ASM-AND-OBJ: qc.cm.popretz {ra}, 16 +# CHECK-ASM: encoding: [0x42,0xbc] +qc.cm.popretz {ra}, 16 + +# CHECK-ASM-AND-OBJ: qc.cm.popretz {ra}, 32 +# CHECK-ASM: encoding: [0x46,0xbc] +qc.cm.popretz {ra}, 32 + +# CHECK-ASM-AND-OBJ: qc.cm.popretz {ra, s0}, 64 +# CHECK-ASM: encoding: [0x5e,0xbc] +qc.cm.popretz {ra, s0}, 64 + +# CHECK-ASM-AND-OBJ: qc.cm.popretz {ra, s0-s1}, 32 +# CHECK-ASM: encoding: [0x62,0xbc] +qc.cm.popretz {ra, s0-s1}, 32 + +# CHECK-ASM-AND-OBJ: qc.cm.pop {ra}, 16 +# CHECK-ASM: encoding: [0x42,0xba] +qc.cm.pop {ra}, 16 + +# CHECK-ASM-AND-OBJ: qc.cm.pop {ra}, 32 +# CHECK-ASM: encoding: [0x46,0xba] +qc.cm.pop {ra}, 32 + +# CHECK-ASM-AND-OBJ: qc.cm.pop {ra, s0}, 16 +# CHECK-ASM: encoding: [0x52,0xba] +qc.cm.pop {ra, s0}, 16 + +# CHECK-ASM-AND-OBJ: qc.cm.pop {ra, s0-s1}, 32 +# CHECK-ASM: encoding: [0x62,0xba] +qc.cm.pop {ra, s0-s1}, 32 + +# CHECK-ASM-AND-OBJ: qc.cm.push {ra}, -16 +# CHECK-ASM: encoding: [0x42,0xb8] +qc.cm.push {ra}, -16 + +# CHECK-ASM-AND-OBJ: qc.cm.push {ra, s0}, -32 +# CHECK-ASM: encoding: [0x56,0xb8] +qc.cm.push {ra, s0}, -32 + +# CHECK-ASM-AND-OBJ: qc.cm.push {ra, s0-s1}, -32 +# CHECK-ASM: encoding: [0x62,0xb8] +qc.cm.push {ra, s0-s1}, -32 + +# CHECK-ASM-AND-OBJ: qc.cm.pushfp {ra}, -16 +# CHECK-ASM: encoding: [0x42,0xb9] +qc.cm.pushfp {ra}, -16 + +# CHECK-ASM-AND-OBJ: qc.cm.pushfp {ra, s0}, -32 +# CHECK-ASM: encoding: [0x56,0xb9] +qc.cm.pushfp {ra, s0}, -32 + +# CHECK-ASM-AND-OBJ: qc.cm.pushfp {ra, s0-s1}, -32 +# CHECK-ASM: encoding: [0x62,0xb9] +qc.cm.pushfp {ra, s0-s1}, -32 diff --git a/llvm/test/MC/RISCV/rv64xqccmp-invalid.s b/llvm/test/MC/RISCV/rv64xqccmp-invalid.s new file mode 100644 index 0000000000000..e922572a44749 --- /dev/null +++ b/llvm/test/MC/RISCV/rv64xqccmp-invalid.s @@ -0,0 +1,35 @@ +# RUN: not llvm-mc -triple=riscv64 -mattr=experimental-xqccmp -M no-aliases -show-encoding < %s 2>&1 \ +# RUN: | FileCheck -check-prefixes=CHECK-ERROR %s + +# CHECK-ERROR: error: invalid operand for instruction +qc.cm.mvsa01 a1, a2 + +# CHECK-ERROR: error: rs1 and rs2 must be diff erent +qc.cm.mvsa01 s0, s0 + +# CHECK-ERROR: error: invalid operand for instruction +qc.cm.mva01s a1, a2 + +# CHECK-ERROR: error: invalid register list, {ra, s0-s10} or {x1, x8-x9, x18-x26} is not supported +qc.cm.popretz {ra, s0-s10}, 112 + +# CHECK-ERROR: error: stack adjustment is invalid for this instruction and register list; refer to Xqccmp spec for a detailed range of stack adjustment +qc.cm.popretz {ra, s0-s1}, 112 + +# CHECK-ERROR: error: stack adjustment is invalid for this instruction and register list; refer to Xqccmp spec for a detailed range of stack adjustment +qc.cm.push {ra}, 16 + +# CHECK-ERROR: error: stack adjustment is invalid for this instruction and register list; refer to Xqccmp spec for a detailed range of stack adjustment +qc.cm.pushfp {ra, s0}, 16 + +# CHECK-ERROR: error: stack adjustment is invalid for this instruction and register list; refer to Xqccmp spec for a detailed range of stack adjustment +qc.cm.pop {ra, s0-s1}, -32 + +# CHECK-ERROR: error: stack adjustment is invalid for this instruction and register list; refer to Xqccmp spec for a detailed range of stack adjustment +qc.cm.push {ra}, -15 + +# CHECK-ERROR: error: stack adjustment is invalid for this instruction and register list; refer to Xqccmp spec for a detailed range of stack adjustment +qc.cm.push {ra, s0}, -15 + +# CHECK-ERROR: error: stack adjustment is invalid for this instruction and register list; refer to Xqccmp spec for a detailed range of stack adjustment +qc.cm.pop {ra, s0-s1}, -33 diff --git a/llvm/test/MC/RISCV/rv64xqccmp-valid.s b/llvm/test/MC/RISCV/rv64xqccmp-valid.s new file mode 100644 index 0000000000000..06ba33fe8a495 --- /dev/null +++ b/llvm/test/MC/RISCV/rv64xqccmp-valid.s @@ -0,0 +1,181 @@ +# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-xqccmp -M no-aliases -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s +# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-xqccmp < %s \ +# RUN: | llvm-objdump --mattr=-c,+experimental-xqccmp -M no-aliases -d -r - \ +# RUN: | FileCheck --check-prefixes=CHECK-ASM-AND-OBJ %s + +# CHECK-ASM-AND-OBJ: qc.cm.mvsa01 s1, s0 +# CHECK-ASM: encoding: [0xa2,0xac] +qc.cm.mvsa01 s1, s0 + +# CHECK-ASM-AND-OBJ: qc.cm.mva01s s1, s0 +# CHECK-ASM: encoding: [0xe2,0xac] +qc.cm.mva01s s1, s0 + +# CHECK-ASM-AND-OBJ: qc.cm.popret {ra}, 16 +# CHECK-ASM: encoding: [0x42,0xbe] +qc.cm.popret {ra}, 16 + +# CHECK-ASM-AND-OBJ: qc.cm.popret {ra}, 32 +# CHECK-ASM: encoding: [0x46,0xbe] +qc.cm.popret {ra}, 32 + +# CHECK-ASM-AND-OBJ: qc.cm.popret {ra, s0}, 64 +# CHECK-ASM: encoding: [0x5e,0xbe] +qc.cm.popret {ra, s0}, 64 + +# CHECK-ASM-AND-OBJ: qc.cm.popret {ra, s0-s1}, 32 +# CHECK-ASM: encoding: [0x62,0xbe] +qc.cm.popret {ra,s0-s1}, 32 + +# CHECK-ASM-AND-OBJ: qc.cm.popret {ra, s0-s2}, 32 +# CHECK-ASM: encoding: [0x72,0xbe] +qc.cm.popret {ra, s0-s2}, 32 + +# CHECK-ASM-AND-OBJ: qc.cm.popret {ra, s0-s3}, 64 +# CHECK-ASM: encoding: [0x86,0xbe] +qc.cm.popret {ra, s0-s3}, 64 + +# CHECK-ASM-AND-OBJ: qc.cm.popret {ra, s0-s5}, 64 +# CHECK-ASM: encoding: [0xa2,0xbe] +qc.cm.popret {ra, s0-s5}, 64 + +# CHECK-ASM-AND-OBJ: qc.cm.popret {ra, s0-s7}, 80 +# CHECK-ASM: encoding: [0xc2,0xbe] +qc.cm.popret {ra, s0-s7}, 80 + +# CHECK-ASM-AND-OBJ: qc.cm.popret {ra, s0-s11}, 112 +# CHECK-ASM: encoding: [0xf2,0xbe] +qc.cm.popret {ra, s0-s11}, 112 + +# CHECK-ASM-AND-OBJ: qc.cm.popretz {ra}, 16 +# CHECK-ASM: encoding: [0x42,0xbc] +qc.cm.popretz {ra}, 16 + +# CHECK-ASM-AND-OBJ: qc.cm.popretz {ra}, 32 +# CHECK-ASM: encoding: [0x46,0xbc] +qc.cm.popretz {ra}, 32 + +# CHECK-ASM-AND-OBJ: qc.cm.popretz {ra, s0}, 64 +# CHECK-ASM: encoding: [0x5e,0xbc] +qc.cm.popretz {ra, s0}, 64 + +# CHECK-ASM-AND-OBJ: qc.cm.popretz {ra, s0-s1}, 32 +# CHECK-ASM: encoding: [0x62,0xbc] +qc.cm.popretz {ra, s0-s1}, 32 + +# CHECK-ASM-AND-OBJ: qc.cm.popretz {ra, s0-s2}, 32 +# CHECK-ASM: encoding: [0x72,0xbc] +qc.cm.popretz {ra, s0-s2}, 32 + +# CHECK-ASM-AND-OBJ: qc.cm.popretz {ra, s0-s3}, 64 +# CHECK-ASM: encoding: [0x86,0xbc] +qc.cm.popretz {ra, s0-s3}, 64 + +# CHECK-ASM-AND-OBJ: qc.cm.popretz {ra, s0-s5}, 64 +# CHECK-ASM: encoding: [0xa2,0xbc] +qc.cm.popretz {ra, s0-s5}, 64 + +# CHECK-ASM-AND-OBJ: qc.cm.popretz {ra, s0-s7}, 80 +# CHECK-ASM: encoding: [0xc2,0xbc] +qc.cm.popretz {ra, s0-s7}, 80 + +# CHECK-ASM-AND-OBJ: qc.cm.popretz {ra, s0-s11}, 112 +# CHECK-ASM: encoding: [0xf2,0xbc] +qc.cm.popretz {ra, s0-s11}, 112 + +# CHECK-ASM-AND-OBJ: qc.cm.pop {ra}, 16 +# CHECK-ASM: encoding: [0x42,0xba] +qc.cm.pop {ra}, 16 + +# CHECK-ASM-AND-OBJ: qc.cm.pop {ra}, 32 +# CHECK-ASM: encoding: [0x46,0xba] +qc.cm.pop {ra}, 32 + +# CHECK-ASM-AND-OBJ: qc.cm.pop {ra, s0}, 16 +# CHECK-ASM: encoding: [0x52,0xba] +qc.cm.pop {ra, s0}, 16 + +# CHECK-ASM-AND-OBJ: qc.cm.pop {ra, s0-s1}, 32 +# CHECK-ASM: encoding: [0x62,0xba] +qc.cm.pop {ra, s0-s1}, 32 + +# CHECK-ASM-AND-OBJ: qc.cm.pop {ra, s0-s2}, 32 +# CHECK-ASM: encoding: [0x72,0xba] +qc.cm.pop {ra, s0-s2}, 32 + +# CHECK-ASM-AND-OBJ: qc.cm.pop {ra, s0-s5}, 64 +# CHECK-ASM: encoding: [0xa2,0xba] +qc.cm.pop {ra, s0-s5}, 64 + +# CHECK-ASM-AND-OBJ: qc.cm.pop {ra, s0-s7}, 80 +# CHECK-ASM: encoding: [0xc2,0xba] +qc.cm.pop {ra, s0-s7}, 80 + +# CHECK-ASM-AND-OBJ: qc.cm.pop {ra, s0-s11}, 112 +# CHECK-ASM: encoding: [0xf2,0xba] +qc.cm.pop {ra, s0-s11}, 112 + +# CHECK-ASM-AND-OBJ: qc.cm.push {ra}, -16 +# CHECK-ASM: encoding: [0x42,0xb8] +qc.cm.push {ra}, -16 + +# CHECK-ASM-AND-OBJ: qc.cm.push {ra, s0}, -32 +# CHECK-ASM: encoding: [0x56,0xb8] +qc.cm.push {ra, s0}, -32 + +# CHECK-ASM-AND-OBJ: qc.cm.push {ra, s0-s1}, -32 +# CHECK-ASM: encoding: [0x62,0xb8] +qc.cm.push {ra, s0-s1}, -32 + +# CHECK-ASM-AND-OBJ: qc.cm.push {ra, s0-s3}, -64 +# CHECK-ASM: encoding: [0x86,0xb8] +qc.cm.push {ra, s0-s3}, -64 + +# CHECK-ASM-AND-OBJ: qc.cm.push {ra, s0-s7}, -80 +# CHECK-ASM: encoding: [0xc2,0xb8] +qc.cm.push {ra, s0-s7}, -80 + +# CHECK-ASM-AND-OBJ: qc.cm.push {ra, s0-s7}, -80 +# CHECK-ASM: encoding: [0xc2,0xb8] +qc.cm.push {ra, s0-s7}, -80 + +# CHECK-ASM-AND-OBJ: qc.cm.push {ra, s0-s11}, -112 +# CHECK-ASM: encoding: [0xf2,0xb8] +qc.cm.push {ra, s0-s11}, -112 + +# CHECK-ASM-AND-OBJ: qc.cm.push {ra, s0-s11}, -128 +# CHECK-ASM: encoding: [0xf6,0xb8] +qc.cm.push {ra, s0-s11}, -128 + +# CHECK-ASM-AND-OBJ: qc.cm.pushfp {ra}, -16 +# CHECK-ASM: encoding: [0x42,0xb9] +qc.cm.pushfp {ra}, -16 + +# CHECK-ASM-AND-OBJ: qc.cm.pushfp {ra, s0}, -32 +# CHECK-ASM: encoding: [0x56,0xb9] +qc.cm.pushfp {ra, s0}, -32 + +# CHECK-ASM-AND-OBJ: qc.cm.pushfp {ra, s0-s1}, -32 +# CHECK-ASM: encoding: [0x62,0xb9] +qc.cm.pushfp {ra, s0-s1}, -32 + +# CHECK-ASM-AND-OBJ: qc.cm.pushfp {ra, s0-s3}, -64 +# CHECK-ASM: encoding: [0x86,0xb9] +qc.cm.pushfp {ra, s0-s3}, -64 + +# CHECK-ASM-AND-OBJ: qc.cm.pushfp {ra, s0-s7}, -80 +# CHECK-ASM: encoding: [0xc2,0xb9] +qc.cm.pushfp {ra, s0-s7}, -80 + +# CHECK-ASM-AND-OBJ: qc.cm.pushfp {ra, s0-s7}, -80 +# CHECK-ASM: encoding: [0xc2,0xb9] +qc.cm.pushfp {ra, s0-s7}, -80 + +# CHECK-ASM-AND-OBJ: qc.cm.pushfp {ra, s0-s11}, -112 +# CHECK-ASM: encoding: [0xf2,0xb9] +qc.cm.pushfp {ra, s0-s11}, -112 + +# CHECK-ASM-AND-OBJ: qc.cm.pushfp {ra, s0-s11}, -128 +# CHECK-ASM: encoding: [0xf6,0xb9] +qc.cm.pushfp {ra, s0-s11}, -128 diff --git a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp index 03bd3c861aab9..0ca8add7e85b4 100644 --- a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp +++ b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp @@ -662,6 +662,11 @@ TEST(ParseArchString, RejectsConflictingExtensions) { toString(RISCVISAInfo::parseArchString(Input, true).takeError()), ::testing::EndsWith(" is only supported for 'rv32'")); } + + for (StringRef Input : {"rv32i_zcmp_xqccmp0p1", "rv64i_zcmp_xqccmp0p1"}) { + EXPECT_EQ(toString(RISCVISAInfo::parseArchString(Input, true).takeError()), + "'zcmp' and 'xqccmp' extensions are incompatible"); + } } TEST(ParseArchString, MissingDepency) { @@ -1119,6 +1124,7 @@ Experimental extensions smctr 1.0 ssctr 1.0 svukte 0.3 + xqccmp 0.1 xqcia 0.4 xqciac 0.3 xqcicli 0.2 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
