================
@@ -2993,6 +2993,22 @@ let Predicates = [HasSVE_or_SME] in {
defm : unpred_loadstore_bitcast<nxv2i64>;
defm : unpred_loadstore_bitcast<nxv2f64>;
+ // Allow using LDR/STR to avoid the predicate dependence.
+ let Predicates = [IsLE, AllowMisalignedMemAccesses] in
----------------
rj-jesus wrote:
Thank you very much for the feedback. I'll rebase the patch to resolve the
conflict with `llvm/test/CodeGen/AArch64/sme-framelower-use-bp.ll` and commit
it afterwards. I'll keep an ear out for reports of performance regressions.
Also, I think the other two patterns we were discussing above probably also
need `AllowMisalignedMemAccesses` as they change the width of the vector
elements accessed.
https://github.com/llvm/llvm-project/pull/127837
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