preames wrote: > But the purpose we add vl/vtype dependencies is to prevent the Post-RA > scheduler moving vsetvl instruction across inline assembly. I'm not sure if > there's better approach to solve this problem.
Maybe have RISCVInsertVSETVLI add implicit use operands to the inline assembly at that point? It's what we do for all the vector instructions. In this case, you might want implicit defs. https://github.com/llvm/llvm-project/pull/128636 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
