================ @@ -0,0 +1,500 @@ +//===-- RISCVSchedGenericOOO.td - Generic O3 Processor -----*- tablegen -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +//===----------------------------------------------------------------------===// +// We assume that: +// * 6-issue out-of-order CPU with 192 ROB entries. +// * Units: +// * IXU (Integer ALU Unit): 4 units, only one can execute mul/div. +// * FXU (Floating-point Unit): 2 units. +// * LSU (Load/Store Unit): 2 units. +// * VXU (Vector Unit): 1 unit. +// * Latency: +// * Integer instructions: 1 cycle. +// * Multiplication instructions: 4 cycles. +// * Multiplication/Division instructions: 7-13 cycles. ---------------- dtcxzyw wrote:
```suggestion // *Division instructions: 13-21 cycles. ``` https://github.com/llvm/llvm-project/pull/120712 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
