efriedma-quic wrote: The architecture manual isn't really helpful here... the instruction set doesn't really have any notion of undefined values in this context; the operations in question are always "merging". The intrinsic allows omitting the destination register for convenience, in which case we assume the user doesn't care what the inactive lanes contain. (There are alternate intrinsics which allow explicitly specifying the contents of the destination.)
Intrinsics documentation is at https://developer.arm.com/architectures/instruction-sets/intrinsics , which is what I quoted from. https://github.com/llvm/llvm-project/pull/124596 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
