================ @@ -0,0 +1,494 @@ +//===-- RISCVSchedGenericOOO.td - Generic O3 Processor -----*- tablegen -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +//===----------------------------------------------------------------------===// +// We assume that: +// * 6-issue out-of-order CPU with 192 ROB entries. +// * Units: +// * IXU (Integer ALU Unit): 4 units, only one can execute division. +// * FXU (Floating-point Unit): 2 units. +// * LSU (Load/Store Unit): 2 units. +// * VXU (Vector Unit): 1 unit. +// * Latency: +// * Integer instructions: 1 cycle. +// * Multiplication instructions: 4 cycles. +// * Multiplication/Division instructions: 7-13 cycles. +// * Floating-point instructions: 2-6 cycles. +// * Vector instructions: 2-6 cycles. +// * Load/Store: +// * IXU: 4 cycles. +// * FXU: 4 cycles. +// * VXU: 6 cycles. +// * Integer/floating-point/vector div/rem/sqrt/... are non-pipelined. +//===----------------------------------------------------------------------===// + +def GenericOOOModel : SchedMachineModel { + int IssueWidth = 6; + int MicroOpBufferSize = 192; + int LoadLatency = 4; + int MispredictPenalty = 8; + let CompleteModel = 0; +} + +let SchedModel = GenericOOOModel in { +//===----------------------------------------------------------------------===// +// Resource groups +//===----------------------------------------------------------------------===// +def GenericOOODIV : ProcResource<1>; +def GenericOOOIXU : ProcResource<3>; +def GenericOOOALU : ProcResGroup<[GenericOOODIV, GenericOOOIXU]>; +def GenericOOOLSU : ProcResource<2>; +def GenericOOOFPU : ProcResource<2>; +// TODO: Add vector scheduling. +// def GenericOOOVXU : ProcResource<1>; + +//===----------------------------------------------------------------------===// +// Branches +//===----------------------------------------------------------------------===// +def : WriteRes<WriteJmp, [GenericOOOALU]>; ---------------- dtcxzyw wrote:
IIRC, only one port supports branch/CSR instructions in most implementations. https://github.com/llvm/llvm-project/pull/120712 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
