Author: Craig Topper Date: 2025-01-08T21:02:46-08:00 New Revision: 5d03235c73476dfa3d2dd48c76de106fd1aa2ac7
URL: https://github.com/llvm/llvm-project/commit/5d03235c73476dfa3d2dd48c76de106fd1aa2ac7 DIFF: https://github.com/llvm/llvm-project/commit/5d03235c73476dfa3d2dd48c76de106fd1aa2ac7.diff LOG: [RISCV] Add -mcpu=sifive-p550. (#122164) This is the CPU in SiFive's HiFive Premier P550 development board. Scheduler model will come in a later patch. Added: Modified: clang/test/Driver/riscv-cpus.c clang/test/Misc/target-invalid-cpu-note/riscv.c llvm/docs/ReleaseNotes.md llvm/lib/Target/RISCV/RISCVProcessors.td Removed: ################################################################################ diff --git a/clang/test/Driver/riscv-cpus.c b/clang/test/Driver/riscv-cpus.c index 1b09945620f8c3..e97b6940662d9f 100644 --- a/clang/test/Driver/riscv-cpus.c +++ b/clang/test/Driver/riscv-cpus.c @@ -433,6 +433,19 @@ // MCPU-SIFIVE-P470-SAME: "-target-feature" "+zvkt" // MCPU-SIFIVE-P470-SAME: "-target-abi" "lp64d" +// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=sifive-p550 | FileCheck -check-prefix=MCPU-SIFIVE-P550 %s +// MCPU-SIFIVE-P550: "-nostdsysteminc" "-target-cpu" "sifive-p550" +// MCPU-SIFIVE-P550-SAME: "-target-feature" "+m" +// MCPU-SIFIVE-P550-SAME: "-target-feature" "+a" +// MCPU-SIFIVE-P550-SAME: "-target-feature" "+f" +// MCPU-SIFIVE-P550-SAME: "-target-feature" "+d" +// MCPU-SIFIVE-P550-SAME: "-target-feature" "+c" +// MCPU-SIFIVE-P550-SAME: "-target-feature" "+zicsr" +// MCPU-SIFIVE-P550-SAME: "-target-feature" "+zifencei" +// MCPU-SIFIVE-P550-SAME: "-target-feature" "+zba" +// MCPU-SIFIVE-P550-SAME: "-target-feature" "+zbb" +// MCPU-SIFIVE-P550-SAME: "-target-abi" "lp64d" + // RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=sifive-p670 | FileCheck -check-prefix=MCPU-SIFIVE-P670 %s // MCPU-SIFIVE-P670: "-target-cpu" "sifive-p670" // MCPU-SIFIVE-P670-SAME: "-target-feature" "+m" diff --git a/clang/test/Misc/target-invalid-cpu-note/riscv.c b/clang/test/Misc/target-invalid-cpu-note/riscv.c index fc8536d99cb804..fb54dcb5b3a93a 100644 --- a/clang/test/Misc/target-invalid-cpu-note/riscv.c +++ b/clang/test/Misc/target-invalid-cpu-note/riscv.c @@ -29,6 +29,7 @@ // RISCV64-SAME: {{^}}, rocket-rv64 // RISCV64-SAME: {{^}}, sifive-p450 // RISCV64-SAME: {{^}}, sifive-p470 +// RISCV64-SAME: {{^}}, sifive-p550 // RISCV64-SAME: {{^}}, sifive-p670 // RISCV64-SAME: {{^}}, sifive-s21 // RISCV64-SAME: {{^}}, sifive-s51 @@ -77,6 +78,7 @@ // TUNE-RISCV64-SAME: {{^}}, rocket-rv64 // TUNE-RISCV64-SAME: {{^}}, sifive-p450 // TUNE-RISCV64-SAME: {{^}}, sifive-p470 +// TUNE-RISCV64-SAME: {{^}}, sifive-p550 // TUNE-RISCV64-SAME: {{^}}, sifive-p670 // TUNE-RISCV64-SAME: {{^}}, sifive-s21 // TUNE-RISCV64-SAME: {{^}}, sifive-s51 diff --git a/llvm/docs/ReleaseNotes.md b/llvm/docs/ReleaseNotes.md index 159bd5cea973f8..3463dc8339fd8f 100644 --- a/llvm/docs/ReleaseNotes.md +++ b/llvm/docs/ReleaseNotes.md @@ -198,6 +198,7 @@ Changes to the RISC-V Backend * `-mcpu=syntacore-scr7` was added. * `-mcpu=tt-ascalon-d8` was added. * `-mcpu=mips-p8700` was added. +* `-mcpu=sifive-p550` was added. * The `Zacas` extension is no longer marked as experimental. * Added Smdbltrp, Ssdbltrp extensions to -march. * The `Smmpm`, `Smnpm`, `Ssnpm`, `Supm`, and `Sspm` pointer masking extensions diff --git a/llvm/lib/Target/RISCV/RISCVProcessors.td b/llvm/lib/Target/RISCV/RISCVProcessors.td index 61c7c21367036f..6dfed7ddeb9f63 100644 --- a/llvm/lib/Target/RISCV/RISCVProcessors.td +++ b/llvm/lib/Target/RISCV/RISCVProcessors.td @@ -321,6 +321,25 @@ def SIFIVE_P470 : RISCVProcessorModel<"sifive-p470", SiFiveP400Model, [TuneNoSinkSplatOperands, TuneVXRMPipelineFlush])>; +defvar SiFiveP500TuneFeatures = [TuneNoDefaultUnroll, + TuneConditionalCompressedMoveFusion, + TuneLUIADDIFusion, + TuneAUIPCADDIFusion, + TunePostRAScheduler]; + +def SIFIVE_P550 : RISCVProcessorModel<"sifive-p550", NoSchedModel, + [Feature64Bit, + FeatureStdExtI, + FeatureStdExtZifencei, + FeatureStdExtM, + FeatureStdExtA, + FeatureStdExtF, + FeatureStdExtD, + FeatureStdExtC, + FeatureStdExtZba, + FeatureStdExtZbb], + SiFiveP500TuneFeatures>; + def SIFIVE_P670 : RISCVProcessorModel<"sifive-p670", SiFiveP600Model, !listconcat(RVA22U64Features, [FeatureStdExtV, _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
