https://github.com/phoebewang created https://github.com/llvm/llvm-project/pull/120061
Ref.: https://cdrdv2.intel.com/v1/dl/getContent/671368 >From d2bd70ca596987fc8ed0292e10c56fe1a98b1333 Mon Sep 17 00:00:00 2001 From: "Wang, Phoebe" <phoebe.w...@intel.com> Date: Mon, 16 Dec 2024 17:48:41 +0800 Subject: [PATCH] [X86] Add missing feature USERMSR to DiamondRapids Ref.: https://cdrdv2.intel.com/v1/dl/getContent/671368 --- clang/test/Preprocessor/predefined-arch-macros.c | 4 ++++ llvm/lib/Target/X86/X86.td | 1 + llvm/lib/TargetParser/X86TargetParser.cpp | 2 +- 3 files changed, 6 insertions(+), 1 deletion(-) diff --git a/clang/test/Preprocessor/predefined-arch-macros.c b/clang/test/Preprocessor/predefined-arch-macros.c index 20aa2d4e0a54cb..43f3454ed3c35d 100644 --- a/clang/test/Preprocessor/predefined-arch-macros.c +++ b/clang/test/Preprocessor/predefined-arch-macros.c @@ -1953,6 +1953,8 @@ // CHECK_GNR_M32: #define __SSSE3__ 1 // CHECK_GNR_M32: #define __TSXLDTRK__ 1 // CHECK_GNR_M32: #define __UINTR__ 1 +// CHECK_GNR_M32-NOT: #define __USERMSR__ 1 +// CHECK_DMR_M32: #define __USERMSR__ 1 // CHECK_GNR_M32: #define __VAES__ 1 // CHECK_GNR_M32: #define __VPCLMULQDQ__ 1 // CHECK_GNR_M32: #define __WAITPKG__ 1 @@ -2061,6 +2063,8 @@ // CHECK_GNR_M64: #define __SSSE3__ 1 // CHECK_GNR_M64: #define __TSXLDTRK__ 1 // CHECK_GNR_M64: #define __UINTR__ 1 +// CHECK_GNR_M64-NOT: #define __USERMSR__ 1 +// CHECK_DMR_M64: #define __USERMSR__ 1 // CHECK_GNR_M64: #define __VAES__ 1 // CHECK_GNR_M64: #define __VPCLMULQDQ__ 1 // CHECK_GNR_M64: #define __WAITPKG__ 1 diff --git a/llvm/lib/Target/X86/X86.td b/llvm/lib/Target/X86/X86.td index 5722167beca9f8..38761e1fd7eecc 100644 --- a/llvm/lib/Target/X86/X86.td +++ b/llvm/lib/Target/X86/X86.td @@ -1163,6 +1163,7 @@ def ProcessorFeatures { FeatureAVXNECONVERT, FeatureAVXVNNIINT8, FeatureAVXVNNIINT16, + FeatureUSERMSR, FeatureSHA512, FeatureSM3, FeatureEGPR, diff --git a/llvm/lib/TargetParser/X86TargetParser.cpp b/llvm/lib/TargetParser/X86TargetParser.cpp index cc356186188913..e4b7ed7cf9b61f 100644 --- a/llvm/lib/TargetParser/X86TargetParser.cpp +++ b/llvm/lib/TargetParser/X86TargetParser.cpp @@ -145,7 +145,7 @@ constexpr FeatureBitset FeaturesDiamondRapids = FeatureSM4 | FeatureEGPR | FeatureZU | FeatureCCMP | FeaturePush2Pop2 | FeaturePPX | FeatureNDD | FeatureNF | FeatureCF | FeatureMOVRS | FeatureAMX_MOVRS | FeatureAMX_AVX512 | FeatureAMX_FP8 | FeatureAMX_TF32 | - FeatureAMX_TRANSPOSE; + FeatureAMX_TRANSPOSE | FeatureUSERMSR; // Intel Atom processors. // Bonnell has feature parity with Core2 and adds MOVBE. _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
