[clang] [llvm] [RISCV] Add Qualcomm uC Xqcics(Conditional Select) extension (PR #119504)

[Craig Topper via cfe-commits]

================
@@ -57,6 +57,86 @@ class QCIRVInstRR<bits<5> func5, DAGOperand InTyRs1, string 
opcodestr>
     : RVInstR<{0b00, func5}, 0b011, OPC_CUSTOM_0, (outs GPRNoX0:$rd),
               (ins InTyRs1:$rs1, GPRNoX0:$rs2), opcodestr, "$rd, $rs1, $rs2">;
 
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+class QCISELECTIICC<bits<3> func3, string opcodestr>
+    : RVInst<(outs GPRNoX0:$rd_wb), (ins GPRNoX0:$rd, GPRNoX0:$rs1,
+                            simm5:$simm5, simm5:$simm), opcodestr,
----------------
topperc wrote:

Can we use `simm1` and `simm2` instead of `simm5` and `simm`? I believe that 
matches the spec.

https://github.com/llvm/llvm-project/pull/119504
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