JonPsson1 wrote:
>> Without vector support, it might make sense to have load/store pseudos with >> an extra GPR def operand, so that these loads/stores can be expanded as a >> PostRA pseudo. Then it would only need handling in one place, but OTOH >> having a second explicit def operand is also undesired, maybe. > I don't think we need to spend much effort optimizing for pre-z13 machines at > this point. This wouldn't be an optimization, rather just handling the shift + insert sequences needed for older machines in one place, instead of as of now in both lowerLoadF16(), and in loadRegFromStackSlot() (and similarly for stores). > Also, looks like the clang-format check is complaining a bit ... Fixed. Inline-assembly support for half with tests added. Implemented bitcast i16<->f16 with vector support but letting it fall back to store+load bitcasting for older archs. This type of bitcasting is used with inline-assembly. https://github.com/llvm/llvm-project/pull/109164 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
