Author: Brandon Wu Date: 2024-11-27T10:54:57+08:00 New Revision: 4a7dbede6badd27ce2ad07984134d5d25a2bbada
URL: https://github.com/llvm/llvm-project/commit/4a7dbede6badd27ce2ad07984134d5d25a2bbada DIFF: https://github.com/llvm/llvm-project/commit/4a7dbede6badd27ce2ad07984134d5d25a2bbada.diff LOG: [RISCV] Support `svukte` extension (#115657) This is the extension for "Address-Independent Latency of User-Mode Faults to Supervisor Addresses". Spec: https://github.com/riscv/riscv-isa-manual/pull/1564, https://lf-riscv.atlassian.net/browse/RVS-2977 The spec states that the `svukte` depends on `sv39`, but we don't have `sv39` yet, so I didn't add it to the implied list. Added: Modified: clang/test/Driver/print-supported-extensions-riscv.c clang/test/Preprocessor/riscv-target-features.c llvm/docs/RISCVUsage.rst llvm/lib/Target/RISCV/RISCVFeatures.td llvm/test/CodeGen/RISCV/attributes.ll llvm/test/MC/RISCV/attribute-arch.s llvm/unittests/TargetParser/RISCVISAInfoTest.cpp Removed: ################################################################################ diff --git a/clang/test/Driver/print-supported-extensions-riscv.c b/clang/test/Driver/print-supported-extensions-riscv.c index 774dc3a4e1e756..151e4701a1da84 100644 --- a/clang/test/Driver/print-supported-extensions-riscv.c +++ b/clang/test/Driver/print-supported-extensions-riscv.c @@ -187,6 +187,7 @@ // CHECK-NEXT: zvkgs 0.7 'Zvkgs' (Vector-Scalar GCM instructions for Cryptography) // CHECK-NEXT: smctr 1.0 'Smctr' (Control Transfer Records Machine Level) // CHECK-NEXT: ssctr 1.0 'Ssctr' (Control Transfer Records Supervisor Level) +// CHECK-NEXT: svukte 0.3 'Svukte' (Address-Independent Latency of User-Mode Faults to Supervisor Addresses) // CHECK-EMPTY: // CHECK-NEXT: Supported Profiles // CHECK-NEXT: rva20s64 diff --git a/clang/test/Preprocessor/riscv-target-features.c b/clang/test/Preprocessor/riscv-target-features.c index 13125d749c5fab..e376821a5517c2 100644 --- a/clang/test/Preprocessor/riscv-target-features.c +++ b/clang/test/Preprocessor/riscv-target-features.c @@ -1811,6 +1811,14 @@ // RUN: -o - | FileCheck --check-prefix=CHECK-SSCTR-EXT %s // CHECK-SSCTR-EXT: __riscv_ssctr 1000000{{$}} +// RUN: %clang --target=riscv32 -menable-experimental-extensions \ +// RUN: -march=rv32i_svukte0p3 -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-SVUKTE-EXT %s +// RUN: %clang --target=riscv64 -menable-experimental-extensions \ +// RUN: -march=rv64i_svukte0p3 -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-SVUKTE-EXT %s +// CHECK-SVUKTE-EXT: __riscv_svukte 3000{{$}} + // Misaligned // RUN: %clang --target=riscv32-unknown-linux-gnu -march=rv32i -E -dM %s \ diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst index 1317221448ea5b..bac267591e0152 100644 --- a/llvm/docs/RISCVUsage.rst +++ b/llvm/docs/RISCVUsage.rst @@ -329,6 +329,9 @@ The primary goal of experimental support is to assist in the process of ratifica ``experimental-smctr``, ``experimental-ssctr`` LLVM implements the `1.0-rc3 specification <https://github.com/riscv/riscv-control-transfer-records/releases/tag/v1.0_rc3>`__. +``experimental-svukte`` + LLVM implements the `0.3 draft specification <https://github.com/riscv/riscv-isa-manual/pull/1564>`__. + To use an experimental extension from `clang`, you must add `-menable-experimental-extensions` to the command line, and specify the exact version of the experimental extension you are using. To use an experimental extension with LLVM's internal developer tools (e.g. `llc`, `llvm-objdump`, `llvm-mc`), you must prefix the extension name with `experimental-`. Note that you don't need to specify the version with internal tools, and shouldn't include the `experimental-` prefix with `clang`. Vendor Extensions diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td index 140185ab909e8e..26e96cf831af76 100644 --- a/llvm/lib/Target/RISCV/RISCVFeatures.td +++ b/llvm/lib/Target/RISCV/RISCVFeatures.td @@ -1059,6 +1059,10 @@ def FeatureStdExtSha FeatureStdExtShvstvala, FeatureStdExtShtvala, FeatureStdExtShvstvecd, FeatureStdExtShvsatpa, FeatureStdExtShgatpa]>; +def FeatureStdExtSvukte + : RISCVExperimentalExtension<"svukte", 0, 3, + "'Svukte' (Address-Independent Latency of User-Mode Faults to Supervisor Addresses)">; + // Pointer Masking extensions // A supervisor-level extension that provides pointer masking for the next lower diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll index b47b5ec460a7c3..e03ab078da627a 100644 --- a/llvm/test/CodeGen/RISCV/attributes.ll +++ b/llvm/test/CodeGen/RISCV/attributes.ll @@ -62,6 +62,7 @@ ; RUN: llc -mtriple=riscv32 -mattr=+svbare %s -o - | FileCheck --check-prefixes=CHECK,RV32SVBARE %s ; RUN: llc -mtriple=riscv32 -mattr=+svnapot %s -o - | FileCheck --check-prefixes=CHECK,RV32SVNAPOT %s ; RUN: llc -mtriple=riscv32 -mattr=+svpbmt %s -o - | FileCheck --check-prefixes=CHECK,RV32SVPBMT %s +; RUN: llc -mtriple=riscv32 -mattr=+experimental-svukte %s -o - | FileCheck --check-prefixes=CHECK,RV32SVUKTE %s ; RUN: llc -mtriple=riscv32 -mattr=+svvptc %s -o - | FileCheck --check-prefixes=CHECK,RV32SVVPTC %s ; RUN: llc -mtriple=riscv32 -mattr=+svinval %s -o - | FileCheck --check-prefixes=CHECK,RV32SVINVAL %s ; RUN: llc -mtriple=riscv32 -mattr=+xcvalu %s -o - | FileCheck --check-prefix=RV32XCVALU %s @@ -205,6 +206,7 @@ ; RUN: llc -mtriple=riscv64 -mattr=+svbare %s -o - | FileCheck --check-prefixes=CHECK,RV64SVBARE %s ; RUN: llc -mtriple=riscv64 -mattr=+svnapot %s -o - | FileCheck --check-prefixes=CHECK,RV64SVNAPOT %s ; RUN: llc -mtriple=riscv64 -mattr=+svpbmt %s -o - | FileCheck --check-prefixes=CHECK,RV64SVPBMT %s +; RUN: llc -mtriple=riscv64 -mattr=+experimental-svukte %s -o - | FileCheck --check-prefixes=CHECK,RV64SVUKTE %s ; RUN: llc -mtriple=riscv64 -mattr=+svvptc %s -o - | FileCheck --check-prefixes=CHECK,RV64SVVPTC %s ; RUN: llc -mtriple=riscv64 -mattr=+svinval %s -o - | FileCheck --check-prefixes=CHECK,RV64SVINVAL %s ; RUN: llc -mtriple=riscv64 -mattr=+xventanacondops %s -o - | FileCheck --check-prefixes=CHECK,RV64XVENTANACONDOPS %s @@ -364,6 +366,7 @@ ; RV32SVBARE: .attribute 5, "rv32i2p1_svbare1p0" ; RV32SVNAPOT: .attribute 5, "rv32i2p1_svnapot1p0" ; RV32SVPBMT: .attribute 5, "rv32i2p1_svpbmt1p0" +; RV32SVUKTE: .attribute 5, "rv32i2p1_svukte0p3" ; RV32SVVPTC: .attribute 5, "rv32i2p1_svvptc1p0" ; RV32SVINVAL: .attribute 5, "rv32i2p1_svinval1p0" ; RV32XCVALU: .attribute 5, "rv32i2p1_xcvalu1p0" @@ -509,6 +512,7 @@ ; RV64SVBARE: .attribute 5, "rv64i2p1_svbare1p0" ; RV64SVNAPOT: .attribute 5, "rv64i2p1_svnapot1p0" ; RV64SVPBMT: .attribute 5, "rv64i2p1_svpbmt1p0" +; RV64SVUKTE: .attribute 5, "rv64i2p1_svukte0p3" ; RV64SVVPTC: .attribute 5, "rv64i2p1_svvptc1p0" ; RV64SVINVAL: .attribute 5, "rv64i2p1_svinval1p0" ; RV64XVENTANACONDOPS: .attribute 5, "rv64i2p1_xventanacondops1p0" diff --git a/llvm/test/MC/RISCV/attribute-arch.s b/llvm/test/MC/RISCV/attribute-arch.s index 9cb4387c720b3b..6ffaa62d50dcf5 100644 --- a/llvm/test/MC/RISCV/attribute-arch.s +++ b/llvm/test/MC/RISCV/attribute-arch.s @@ -381,6 +381,9 @@ .attribute arch, "rv32i_svbare1p0" # CHECK: attribute 5, "rv32i2p1_svbare1p0" +.attribute arch, "rv32i_svukte0p3" +# CHECK: attribute 5, "rv32i2p1_svukte0p3" + .attribute arch, "rv32i_svvptc1p0" # CHECK: attribute 5, "rv32i2p1_svvptc1p0" diff --git a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp index 1b445dff8ca96a..0694d0987c5274 100644 --- a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp +++ b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp @@ -1103,6 +1103,7 @@ Experimental extensions zvkgs 0.7 smctr 1.0 ssctr 1.0 + svukte 0.3 Supported Profiles rva20s64 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
