llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT--> @llvm/pr-subscribers-clang Author: Daniel Paoliello (dpaoliello) <details> <summary>Changes</summary> Enables `xs` and `tlb-rmi` target features to be enabled via `-march` and adds new target defines for them in Clang. --- Full diff: https://github.com/llvm/llvm-project/pull/116707.diff 4 Files Affected: - (modified) clang/lib/Basic/Targets/AArch64.cpp (+12) - (modified) clang/lib/Basic/Targets/AArch64.h (+2) - (modified) clang/test/Preprocessor/aarch64-target-features.c (+8) - (modified) llvm/lib/Target/AArch64/AArch64Features.td (+5-5) ``````````diff diff --git a/clang/lib/Basic/Targets/AArch64.cpp b/clang/lib/Basic/Targets/AArch64.cpp index eb8a3ada034482..420b8ad7a01f09 100644 --- a/clang/lib/Basic/Targets/AArch64.cpp +++ b/clang/lib/Basic/Targets/AArch64.cpp @@ -635,6 +635,12 @@ void AArch64TargetInfo::getTargetDefines(const LangOptions &Opts, if (HasGCS) Builder.defineMacro("__ARM_FEATURE_GCS", "1"); + if (HasXS) + Builder.defineMacro("__ARM_FEATURE_XS", "1"); + + if (HasTLBRmi) + Builder.defineMacro("__ARM_FEATURE_TLB_RMI", "1"); + if (*ArchInfo == llvm::AArch64::ARMV8_1A) getTargetDefinesARMV81A(Opts, Builder); else if (*ArchInfo == llvm::AArch64::ARMV8_2A) @@ -790,6 +796,8 @@ bool AArch64TargetInfo::hasFeature(StringRef Feature) const { .Cases("ls64", "ls64_v", "ls64_accdata", HasLS64) .Case("wfxt", HasWFxT) .Case("rcpc3", HasRCPC3) + .Case("xs", HasXS) + .Case("tlb-rmi", HasTLBRmi) .Default(false); } @@ -1102,6 +1110,10 @@ bool AArch64TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, HasPAuthLR = true; HasPAuth = true; } + if (Feature == "+xs") + HasXS = true; + if (Feature == "+tlb-rmi") + HasTLBRmi = true; } // Check features that are manually disabled by command line options. diff --git a/clang/lib/Basic/Targets/AArch64.h b/clang/lib/Basic/Targets/AArch64.h index 4c25bdb5bb16df..47149a74a22f26 100644 --- a/clang/lib/Basic/Targets/AArch64.h +++ b/clang/lib/Basic/Targets/AArch64.h @@ -118,6 +118,8 @@ class LLVM_LIBRARY_VISIBILITY AArch64TargetInfo : public TargetInfo { bool HasRCPC3 = false; bool HasSMEFA64 = false; bool HasPAuthLR = false; + bool HasXS = false; + bool HasTLBRmi = false; const llvm::AArch64::ArchInfo *ArchInfo = &llvm::AArch64::ARMV8A; diff --git a/clang/test/Preprocessor/aarch64-target-features.c b/clang/test/Preprocessor/aarch64-target-features.c index 037a3e186ee559..be26d0d300f94b 100644 --- a/clang/test/Preprocessor/aarch64-target-features.c +++ b/clang/test/Preprocessor/aarch64-target-features.c @@ -738,3 +738,11 @@ // CHECK-SMEB16B16: __ARM_FEATURE_SME2 1 // CHECK-SMEB16B16: __ARM_FEATURE_SME_B16B16 1 // CHECK-SMEB16B16: __ARM_FEATURE_SVE_B16B16 1 + +// ================== Check Armv8.7-A limited-TLB-maintenance instruction. +// RUN: %clang -target aarch64 -march=armv8a+xs -x c -E -dM %s -o - | FileCheck -check-prefix=CHECK-XS %s +// CHECK-XS: __ARM_FEATURE_XS 1 + +// ================== Check Armv8.4-A TLB Range and Maintenance instructions. +// RUN: %clang -target aarch64 -march=armv8a+tlb-rmi -x c -E -dM %s -o - | FileCheck -check-prefix=CHECK-TLB-RMI %s +// CHECK-TLB-RMI: __ARM_FEATURE_TLB_RMI 1 diff --git a/llvm/lib/Target/AArch64/AArch64Features.td b/llvm/lib/Target/AArch64/AArch64Features.td index 088de4328a198d..189b0646a97085 100644 --- a/llvm/lib/Target/AArch64/AArch64Features.td +++ b/llvm/lib/Target/AArch64/AArch64Features.td @@ -227,7 +227,7 @@ def FeatureAM : Extension<"am", "AM", "FEAT_AMUv1", def FeatureSEL2 : Extension<"sel2", "SEL2", "FEAT_SEL2", "Enable Armv8.4-A Secure Exception Level 2 extension">; -def FeatureTLB_RMI : Extension<"tlb-rmi", "TLB_RMI", +def FeatureTLB_RMI : ExtensionWithMArch<"tlb-rmi", "TLB_RMI", "FEAT_TLBIOS, FEAT_TLBIRANGE", "Enable Armv8.4-A TLB Range and Maintenance instructions">; @@ -296,7 +296,7 @@ def FeatureEnhancedCounterVirtualization : // Armv8.7 Architecture Extensions //===----------------------------------------------------------------------===// -def FeatureXS : Extension<"xs", "XS", "FEAT_XS", +def FeatureXS : ExtensionWithMArch<"xs", "XS", "FEAT_XS", "Enable Armv8.7-A limited-TLB-maintenance instruction">; def FeatureWFxT : ExtensionWithMArch<"wfxt", "WFxT", "FEAT_WFxT", @@ -836,7 +836,7 @@ def HasV8_4aOps : Architecture64<8, 4, "a", "v8.4a", [HasV8_3aOps, FeatureDotProd, FeatureNV, FeatureMPAM, FeatureDIT, FeatureTRACEV8_4, FeatureAM, FeatureSEL2, FeatureTLB_RMI, FeatureFlagM, FeatureRCPC_IMMO, FeatureLSE2], - !listconcat(HasV8_3aOps.DefaultExts, [FeatureDotProd, FeatureDIT, FeatureFlagM])>; + !listconcat(HasV8_3aOps.DefaultExts, [FeatureDotProd, FeatureDIT, FeatureTLB_RMI, FeatureFlagM])>; def HasV8_5aOps : Architecture64<8, 5, "a", "v8.5a", [HasV8_4aOps, FeatureAltFPCmp, FeatureFRInt3264, FeatureSpecRestrict, FeatureSB, FeaturePredRes, FeatureCacheDeepPersist, @@ -848,7 +848,7 @@ def HasV8_6aOps : Architecture64<8, 6, "a", "v8.6a", !listconcat(HasV8_5aOps.DefaultExts, [FeatureBF16, FeatureMatMulInt8])>; def HasV8_7aOps : Architecture64<8, 7, "a", "v8.7a", [HasV8_6aOps, FeatureXS, FeatureWFxT, FeatureHCX, FeatureSPE_EEF], - !listconcat(HasV8_6aOps.DefaultExts, [FeatureWFxT])>; + !listconcat(HasV8_6aOps.DefaultExts, [FeatureXS, FeatureWFxT])>; def HasV8_8aOps : Architecture64<8, 8, "a", "v8.8a", [HasV8_7aOps, FeatureHBC, FeatureMOPS, FeatureNMI], !listconcat(HasV8_7aOps.DefaultExts, [FeatureMOPS, FeatureHBC])>; @@ -866,7 +866,7 @@ def HasV9_1aOps : Architecture64<9, 1, "a", "v9.1a", !listconcat(HasV9_0aOps.DefaultExts, [FeatureBF16, FeatureMatMulInt8, FeatureRME])>; def HasV9_2aOps : Architecture64<9, 2, "a", "v9.2a", [HasV8_7aOps, HasV9_1aOps], - !listconcat(HasV9_1aOps.DefaultExts, [FeatureMEC, FeatureWFxT])>; + !listconcat(HasV9_1aOps.DefaultExts, [FeatureMEC, FeatureXS, FeatureWFxT])>; def HasV9_3aOps : Architecture64<9, 3, "a", "v9.3a", [HasV8_8aOps, HasV9_2aOps], !listconcat(HasV9_2aOps.DefaultExts, [FeatureMOPS, FeatureHBC])>; `````````` </details> https://github.com/llvm/llvm-project/pull/116707 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
