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<details>
<summary>
You can test this locally with the following command:
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``````````bash
git-clang-format --diff bbc0e631d2d3facd5952aeafc7400761813acc3a
fb082f6093d5c58b899bfc4b2373966e38b6e763 --extensions cpp,h --
clang/lib/Basic/Targets/SystemZ.h clang/lib/CodeGen/CGBuiltin.cpp
llvm/lib/Target/SystemZ/SystemZAsmPrinter.cpp
llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
llvm/lib/Target/SystemZ/SystemZISelLowering.h
llvm/lib/Target/SystemZ/SystemZLongBranch.cpp
llvm/lib/Target/SystemZ/SystemZRegisterInfo.cpp
llvm/lib/Target/SystemZ/SystemZRegisterInfo.h
``````````
</details>
<details>
<summary>
View the diff from clang-format here.
</summary>
``````````diff
diff --git a/llvm/lib/Target/SystemZ/SystemZAsmPrinter.cpp
b/llvm/lib/Target/SystemZ/SystemZAsmPrinter.cpp
index a75dac5b91..05377aee10 100644
--- a/llvm/lib/Target/SystemZ/SystemZAsmPrinter.cpp
+++ b/llvm/lib/Target/SystemZ/SystemZAsmPrinter.cpp
@@ -687,7 +687,7 @@ void SystemZAsmPrinter::emitInstruction(const MachineInstr
*MI) {
MCInstBuilder(SystemZ::EXRL).addReg(LenMinus1Reg).addExpr(Dot));
return;
}
- // EH_SjLj_Setup is a dummy terminator instruction of size 0,
+ // EH_SjLj_Setup is a dummy terminator instruction of size 0,
// It is used to handle the clobber register for builtin setjmp.
case SystemZ::EH_SjLj_Setup:
return;
diff --git a/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
b/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
index f498f9eab8..6c5ba41431 100644
--- a/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
+++ b/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
@@ -751,13 +751,11 @@ SystemZTargetLowering::SystemZTargetLowering(const
TargetMachine &TM,
setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
- // We're not using SJLJ for exception handling, but they're implemented
- // solely to support use of __builtin_setjmp / __builtin_longjmp.
+ // We're not using SJLJ for exception handling, but they're implemented
+ // solely to support use of __builtin_setjmp / __builtin_longjmp.
setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
-
-
// We want to use MVC in preference to even a single load/store pair.
MaxStoresPerMemcpy = Subtarget.hasVector() ? 2 : 0;
MaxStoresPerMemcpyOptSize = 0;
@@ -947,10 +945,9 @@ bool SystemZTargetLowering::isFPImmLegal(const APFloat
&Imm, EVT VT,
return SystemZVectorConstantInfo(Imm).isVectorConstantLegal(Subtarget);
}
-
MachineBasicBlock *
SystemZTargetLowering::emitEHSjLjSetJmp(MachineInstr &MI,
- MachineBasicBlock *MBB) const {
+ MachineBasicBlock *MBB) const {
DebugLoc DL = MI.getDebugLoc();
const TargetInstrInfo *TII = Subtarget.getInstrInfo();
@@ -969,8 +966,7 @@ SystemZTargetLowering::emitEHSjLjSetJmp(MachineInstr &MI,
Register restoreDstReg = MRI.createVirtualRegister(RC);
MVT PVT = getPointerTy(MF->getDataLayout());
- assert((PVT == MVT::i64 || PVT == MVT::i32) &&
- "Invalid Pointer Size!");
+ assert((PVT == MVT::i64 || PVT == MVT::i32) && "Invalid Pointer Size!");
// For v = setjmp(buf), we generate.
// Algorithm:
//
@@ -1021,67 +1017,66 @@ SystemZTargetLowering::emitEHSjLjSetJmp(MachineInstr
&MI,
sinkMBB->splice(sinkMBB->begin(), MBB,
std::next(MachineBasicBlock::iterator(MI)), MBB->end());
sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
-
// thisMBB:
const int64_t LabelOffset = 1 * PVT.getStoreSize(); // Slot 2.
- const int64_t SPOffset = 3 * PVT.getStoreSize(); // Slot 4.
+ const int64_t SPOffset = 3 * PVT.getStoreSize(); // Slot 4.
// Buf address.
Register BufReg = MI.getOperand(1).getReg();
unsigned LabelReg = 0;
const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
- LabelReg = MRI.createVirtualRegister(PtrRC);
+ LabelReg = MRI.createVirtualRegister(PtrRC);
// prepare IP for longjmp.
BuildMI(*thisMBB, MI, DL, TII->get(SystemZ::LARL), LabelReg)
- .addMBB(restoreMBB);
+ .addMBB(restoreMBB);
// store IP for return from jmp, slot 2, offset = 1.
BuildMI(*thisMBB, MI, DL, TII->get(SystemZ::STG))
- .addReg(LabelReg)
- .addReg(BufReg)
- .addImm(LabelOffset)
- .addReg(0);
+ .addReg(LabelReg)
+ .addReg(BufReg)
+ .addImm(LabelOffset)
+ .addReg(0);
- bool HasFP = Subtarget.getFrameLowering()->hasFP(*MF);
+ bool HasFP = Subtarget.getFrameLowering()->hasFP(*MF);
if (HasFP) {
- const int64_t FPOffset = 0;
- BuildMI(*thisMBB, MI, DL, TII->get(SystemZ::STG))
- .addReg(SystemZ::R11D)
- .addReg(BufReg)
- .addImm(FPOffset)
- .addReg(0);
- }
-
+ const int64_t FPOffset = 0;
+ BuildMI(*thisMBB, MI, DL, TII->get(SystemZ::STG))
+ .addReg(SystemZ::R11D)
+ .addReg(BufReg)
+ .addImm(FPOffset)
+ .addReg(0);
+ }
+
// store SP.
BuildMI(*thisMBB, MI, DL, TII->get(SystemZ::STG))
- .addReg(SystemZ::R15D)
- .addReg(BufReg)
- .addImm(SPOffset)
- .addReg(0);
+ .addReg(SystemZ::R15D)
+ .addReg(BufReg)
+ .addImm(SPOffset)
+ .addReg(0);
// Slot 3(Offset = 2) Backchain value (if building with -mbackchain).
bool BackChain = MF->getSubtarget<SystemZSubtarget>().hasBackChain();
if (BackChain) {
- const int64_t BCOffset = 2 * PVT.getStoreSize();
- Register BCReg = MRI.createVirtualRegister(RC);
- MIB = BuildMI(*thisMBB, MI, DL, TII->get(SystemZ::LG), BCReg)
- .addReg(SystemZ::R15D)
- .addImm(0)
- .addReg(0);
+ const int64_t BCOffset = 2 * PVT.getStoreSize();
+ Register BCReg = MRI.createVirtualRegister(RC);
+ MIB = BuildMI(*thisMBB, MI, DL, TII->get(SystemZ::LG), BCReg)
+ .addReg(SystemZ::R15D)
+ .addImm(0)
+ .addReg(0);
- BuildMI(*thisMBB, MI, DL, TII->get(SystemZ::STG))
- .addReg(BCReg)
- .addReg(BufReg)
- .addImm(BCOffset)
- .addReg(0);
+ BuildMI(*thisMBB, MI, DL, TII->get(SystemZ::STG))
+ .addReg(BCReg)
+ .addReg(BufReg)
+ .addImm(BCOffset)
+ .addReg(0);
}
- // Setup.
+ // Setup.
MIB = BuildMI(*thisMBB, MI, DL, TII->get(SystemZ::EH_SjLj_Setup))
- .addMBB(restoreMBB);
+ .addMBB(restoreMBB);
const SystemZRegisterInfo *RegInfo = Subtarget.getRegisterInfo();
MIB.addRegMask(RegInfo->getNoPreservedMask());
@@ -1095,10 +1090,10 @@ SystemZTargetLowering::emitEHSjLjSetJmp(MachineInstr
&MI,
// sinkMBB:
BuildMI(*sinkMBB, sinkMBB->begin(), DL, TII->get(SystemZ::PHI), DstReg)
- .addReg(mainDstReg)
- .addMBB(mainMBB)
- .addReg(restoreDstReg)
- .addMBB(restoreMBB);
+ .addReg(mainDstReg)
+ .addMBB(mainMBB)
+ .addReg(restoreDstReg)
+ .addMBB(restoreMBB);
// restoreMBB.
BuildMI(restoreMBB, DL, TII->get(SystemZ::LHI), restoreDstReg).addImm(1);
@@ -1112,7 +1107,7 @@ SystemZTargetLowering::emitEHSjLjSetJmp(MachineInstr &MI,
MachineBasicBlock *
SystemZTargetLowering::emitEHSjLjLongJmp(MachineInstr &MI,
- MachineBasicBlock *MBB) const {
+ MachineBasicBlock *MBB) const {
DebugLoc DL = MI.getDebugLoc();
const TargetInstrInfo *TII = Subtarget.getInstrInfo();
@@ -1121,8 +1116,7 @@ SystemZTargetLowering::emitEHSjLjLongJmp(MachineInstr &MI,
MachineRegisterInfo &MRI = MF->getRegInfo();
MVT PVT = getPointerTy(MF->getDataLayout());
- assert((PVT == MVT::i64 || PVT == MVT::i32) &&
- "Invalid Pointer Size!");
+ assert((PVT == MVT::i64 || PVT == MVT::i32) && "Invalid Pointer Size!");
Register BufReg = MI.getOperand(0).getReg();
const TargetRegisterClass *RC = MRI.getRegClass(BufReg);
@@ -1131,49 +1125,49 @@ SystemZTargetLowering::emitEHSjLjLongJmp(MachineInstr
&MI,
MachineInstrBuilder MIB;
- const int64_t FPOffset = 0;
+ const int64_t FPOffset = 0;
const int64_t LabelOffset = 1 * PVT.getStoreSize();
- const int64_t SPOffset = 3 * PVT.getStoreSize();
- const int64_t LPOffset = 4 * PVT.getStoreSize();
+ const int64_t SPOffset = 3 * PVT.getStoreSize();
+ const int64_t LPOffset = 4 * PVT.getStoreSize();
MIB = BuildMI(*MBB, MI, DL, TII->get(SystemZ::LG), Tmp)
- .addReg(BufReg)
- .addImm(LabelOffset)
- .addReg(0);
+ .addReg(BufReg)
+ .addImm(LabelOffset)
+ .addReg(0);
MIB = BuildMI(*MBB, MI, DL, TII->get(SystemZ::LG), SystemZ::R11D)
- .addReg(BufReg)
- .addImm(FPOffset)
- .addReg(0);
+ .addReg(BufReg)
+ .addImm(FPOffset)
+ .addReg(0);
// We are restoring R13 even though we never stored in setjmp from llvm,
- // as gcc always stores R13 in builtin_setjmp. We could have mixed code
+ // as gcc always stores R13 in builtin_setjmp. We could have mixed code
// gcc setjmp and llvm longjmp.
MIB = BuildMI(*MBB, MI, DL, TII->get(SystemZ::LG), SystemZ::R13D)
- .addReg(BufReg)
- .addImm(LPOffset)
- .addReg(0);
+ .addReg(BufReg)
+ .addImm(LPOffset)
+ .addReg(0);
bool BackChain = MF->getSubtarget<SystemZSubtarget>().hasBackChain();
if (BackChain) {
- const int64_t BCOffset = 2 * PVT.getStoreSize();
- MIB = BuildMI(*MBB, MI, DL, TII->get(SystemZ::LG), BCReg)
- .addReg(BufReg)
- .addImm(BCOffset)
- .addReg(0);
+ const int64_t BCOffset = 2 * PVT.getStoreSize();
+ MIB = BuildMI(*MBB, MI, DL, TII->get(SystemZ::LG), BCReg)
+ .addReg(BufReg)
+ .addImm(BCOffset)
+ .addReg(0);
}
MIB = BuildMI(*MBB, MI, DL, TII->get(SystemZ::LG), SystemZ::R15D)
- .addReg(BufReg)
- .addImm(SPOffset)
- .addReg(0);
+ .addReg(BufReg)
+ .addImm(SPOffset)
+ .addReg(0);
if (BackChain) {
- BuildMI(*MBB, MI, DL, TII->get(SystemZ::STG))
- .addReg(BCReg)
- .addReg(SystemZ::R15D)
- .addImm(0)
- .addReg(0);
+ BuildMI(*MBB, MI, DL, TII->get(SystemZ::STG))
+ .addReg(BCReg)
+ .addReg(SystemZ::R15D)
+ .addImm(0)
+ .addReg(0);
}
MIB = BuildMI(*MBB, MI, DL, TII->get(SystemZ::BR)).addReg(Tmp);
@@ -9970,7 +9964,7 @@ MachineBasicBlock
*SystemZTargetLowering::EmitInstrWithCustomInserter(
case SystemZ::PROBED_ALLOCA:
return emitProbedAlloca(MI, MBB);
-
+
case SystemZ::EH_SjLj_SetJmp:
return emitEHSjLjSetJmp(MI, MBB);
case SystemZ::EH_SjLj_LongJmp:
diff --git a/llvm/lib/Target/SystemZ/SystemZISelLowering.h
b/llvm/lib/Target/SystemZ/SystemZISelLowering.h
index 92ac938c90..0a899e861c 100644
--- a/llvm/lib/Target/SystemZ/SystemZISelLowering.h
+++ b/llvm/lib/Target/SystemZ/SystemZISelLowering.h
@@ -477,10 +477,10 @@ public:
return VT != MVT::f64;
}
MachineBasicBlock *emitEHSjLjSetJmp(MachineInstr &MI,
- MachineBasicBlock *MBB) const;
+ MachineBasicBlock *MBB) const;
MachineBasicBlock *emitEHSjLjLongJmp(MachineInstr &MI,
- MachineBasicBlock *MBB) const;
+ MachineBasicBlock *MBB) const;
bool hasInlineStackProbe(const MachineFunction &MF) const override;
AtomicExpansionKind shouldCastAtomicLoadInIR(LoadInst *LI) const override;
@@ -729,7 +729,6 @@ private:
SDValue lowerGET_ROUNDING(SDValue Op, SelectionDAG &DAG) const;
SDValue lowerREADCYCLECOUNTER(SDValue Op, SelectionDAG &DAG) const;
-
bool canTreatAsByteVector(EVT VT) const;
SDValue combineExtract(const SDLoc &DL, EVT ElemVT, EVT VecVT, SDValue
OrigOp,
unsigned Index, DAGCombinerInfo &DCI,
diff --git a/llvm/lib/Target/SystemZ/SystemZLongBranch.cpp
b/llvm/lib/Target/SystemZ/SystemZLongBranch.cpp
index 8267d398c5..36d7623539 100644
--- a/llvm/lib/Target/SystemZ/SystemZLongBranch.cpp
+++ b/llvm/lib/Target/SystemZ/SystemZLongBranch.cpp
@@ -220,10 +220,10 @@ static unsigned getInstSizeInBytes(const MachineInstr &MI,
MI.isImplicitDef() || MI.getOpcode() == TargetOpcode::MEMBARRIER ||
// These have a size that may be zero:
MI.isInlineAsm() || MI.getOpcode() == SystemZ::STACKMAP ||
- MI.getOpcode() == SystemZ::PATCHPOINT ||
+ MI.getOpcode() == SystemZ::PATCHPOINT ||
// EH_SjLj_Setup is a dummy terminator instruction of size 0,
// It is used to handle the clobber register for builtin setjmp.
- MI.getOpcode() == SystemZ::EH_SjLj_Setup) &&
+ MI.getOpcode() == SystemZ::EH_SjLj_Setup) &&
"Missing size value for instruction.");
return Size;
}
diff --git a/llvm/lib/Target/SystemZ/SystemZRegisterInfo.cpp
b/llvm/lib/Target/SystemZ/SystemZRegisterInfo.cpp
index 6d3e542c1b..0df2a15753 100644
--- a/llvm/lib/Target/SystemZ/SystemZRegisterInfo.cpp
+++ b/llvm/lib/Target/SystemZ/SystemZRegisterInfo.cpp
@@ -254,9 +254,8 @@ SystemZRegisterInfo::getCallPreservedMask(const
MachineFunction &MF,
return Regs->getCallPreservedMask(MF, CC);
}
-const uint32_t*
-SystemZRegisterInfo::getNoPreservedMask() const {
- return CSR_SystemZ_NoRegs_RegMask;
+const uint32_t *SystemZRegisterInfo::getNoPreservedMask() const {
+ return CSR_SystemZ_NoRegs_RegMask;
}
BitVector
``````````
</details>
https://github.com/llvm/llvm-project/pull/116642
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