================
@@ -21351,6 +21372,17 @@ bool RISCVTargetLowering::splitValueIntoRegisterParts(
unsigned NumParts, MVT PartVT, std::optional<CallingConv::ID> CC) const {
bool IsABIRegCopy = CC.has_value();
EVT ValueVT = Val.getValueType();
+
+ if (ValueVT == (Subtarget.is64Bit() ? MVT::i128 : MVT::i64) &&
+ NumParts == 1 && PartVT == MVT::Untyped) {
+ // Pairs in Inline Assembly
+ MVT XLenVT = Subtarget.getXLenVT();
+ SDValue Lo, Hi;
+ std::tie(Lo, Hi) = DAG.SplitScalar(Val, DL, XLenVT, XLenVT);
----------------
lenary wrote:
Done.
https://github.com/llvm/llvm-project/pull/112983
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