https://github.com/asb updated https://github.com/llvm/llvm-project/pull/113942
>From 47418b35a6e3e02eb20ff7b81f45571bf1322f5b Mon Sep 17 00:00:00 2001 From: Alex Bradbury <a...@igalia.com> Date: Mon, 28 Oct 2024 14:42:44 +0000 Subject: [PATCH 1/3] [RISCV] Mark RVB23U64 and RVB23S64 as non-experimental The specification was recently ratified <https://github.com/riscv/riscv-profiles/blob/main/src/rvb23-profile.adoc>. --- clang/test/Driver/print-supported-extensions-riscv.c | 4 ++-- clang/test/Driver/riscv-profiles.c | 4 ++-- llvm/docs/RISCVUsage.rst | 4 ++-- llvm/docs/ReleaseNotes.md | 3 ++- llvm/lib/Target/RISCV/RISCVProfiles.td | 4 ++-- llvm/test/CodeGen/RISCV/attributes.ll | 4 ++-- llvm/unittests/TargetParser/RISCVISAInfoTest.cpp | 4 ++-- 7 files changed, 14 insertions(+), 13 deletions(-) diff --git a/clang/test/Driver/print-supported-extensions-riscv.c b/clang/test/Driver/print-supported-extensions-riscv.c index e39847b9c31a8e..68acde65a74bfb 100644 --- a/clang/test/Driver/print-supported-extensions-riscv.c +++ b/clang/test/Driver/print-supported-extensions-riscv.c @@ -193,12 +193,12 @@ // CHECK-NEXT: rva22u64 // CHECK-NEXT: rva23s64 // CHECK-NEXT: rva23u64 +// CHECK-NEXT: rvb23s64 +// CHECK-NEXT: rvb23u64 // CHECK-NEXT: rvi20u32 // CHECK-NEXT: rvi20u64 // CHECK-EMPTY: // CHECK-NEXT: Experimental Profiles -// CHECK-NEXT: rvb23s64 -// CHECK-NEXT: rvb23u64 // CHECK-NEXT: rvm23u32 // CHECK-EMPTY: // CHECK-NEXT: Use -march to specify the target's extension. diff --git a/clang/test/Driver/riscv-profiles.c b/clang/test/Driver/riscv-profiles.c index d85ac8baf4edd9..2b4d19422874cf 100644 --- a/clang/test/Driver/riscv-profiles.c +++ b/clang/test/Driver/riscv-profiles.c @@ -207,7 +207,7 @@ // RVA23S64: "-target-feature" "+svnapot" // RVA23S64: "-target-feature" "+svpbmt" -// RUN: %clang --target=riscv64 -### -c %s 2>&1 -march=rvb23u64 -menable-experimental-extensions \ +// RUN: %clang --target=riscv64 -### -c %s 2>&1 -march=rvb23u64 \ // RUN: | FileCheck -check-prefix=RVB23U64 %s // RVB23U64: "-target-feature" "+m" // RVB23U64: "-target-feature" "+a" @@ -239,7 +239,7 @@ // RVB23U64: "-target-feature" "+zbs" // RVB23U64: "-target-feature" "+zkt" -// RUN: %clang --target=riscv64 -### -c %s 2>&1 -march=rvb23s64 -menable-experimental-extensions \ +// RUN: %clang --target=riscv64 -### -c %s 2>&1 -march=rvb23s64 \ // RUN: | FileCheck -check-prefix=RVB23S64 %s // RVB23S64: "-target-feature" "+m" // RVB23S64: "-target-feature" "+a" diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst index 04f2c357766d44..f6f2eb45c49c17 100644 --- a/llvm/docs/RISCVUsage.rst +++ b/llvm/docs/RISCVUsage.rst @@ -84,6 +84,8 @@ ISA naming string. Currently supported profiles: * ``rva22s64`` * ``rva23u64`` * ``rva23s64`` +* ``rvb23u64`` +* ``rvb23s64`` Note that you can also append additional extension names to be enabled, e.g. ``rva20u64_zicond`` will enable the ``zicond`` extension in addition to those @@ -93,8 +95,6 @@ Profiles that are not yet ratified cannot be used unless ``-menable-experimental-extensions`` (or equivalent for other tools) is specified. This applies to the following profiles: -* ``rvb23u64`` -* ``rvb23s64`` * ``rvm23u32`` .. _riscv-extensions: diff --git a/llvm/docs/ReleaseNotes.md b/llvm/docs/ReleaseNotes.md index ac7a795daf791a..92a45d845f1db8 100644 --- a/llvm/docs/ReleaseNotes.md +++ b/llvm/docs/ReleaseNotes.md @@ -184,7 +184,8 @@ Changes to the RISC-V Backend * The `Smmpm`, `Smnpm`, `Ssnpm`, `Supm`, and `Sspm` pointer masking extensions are no longer marked as experimental. * The `Sha` extension is now supported. -* The RVA23U64 and RVA23S64 profiles are no longer marked as experimental. +* The RVA23U64, RVA23S64, RVB23U64, and RVB23S64 profiles are no longer marked + as experimental. Changes to the WebAssembly Backend ---------------------------------- diff --git a/llvm/lib/Target/RISCV/RISCVProfiles.td b/llvm/lib/Target/RISCV/RISCVProfiles.td index ea0fe08abd7a14..cbf2a2eddf38ed 100644 --- a/llvm/lib/Target/RISCV/RISCVProfiles.td +++ b/llvm/lib/Target/RISCV/RISCVProfiles.td @@ -163,6 +163,6 @@ def RVA22U64 : RISCVProfile<"rva22u64", RVA22U64Features>; def RVA22S64 : RISCVProfile<"rva22s64", RVA22S64Features>; def RVA23U64 : RISCVProfile<"rva23u64", RVA23U64Features>; def RVA23S64 : RISCVProfile<"rva23s64", RVA23S64Features>; -def RVB23U64 : RISCVExperimentalProfile<"rvb23u64", RVB23U64Features>; -def RVB23S64 : RISCVExperimentalProfile<"rvb23s64", RVB23S64Features>; +def RVB23U64 : RISCVProfile<"rvb23u64", RVB23U64Features>; +def RVB23S64 : RISCVProfile<"rvb23s64", RVB23S64Features>; def RVM23U32 : RISCVExperimentalProfile<"rvm23u32", RVM23U32Features>; diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll index 2545c7075e4cf5..c03108c0617e75 100644 --- a/llvm/test/CodeGen/RISCV/attributes.ll +++ b/llvm/test/CodeGen/RISCV/attributes.ll @@ -293,8 +293,8 @@ ; RUN: llc -mtriple=riscv64 -mattr=+rva22s64 %s -o - | FileCheck --check-prefix=RVA22S64 %s ; RUN: llc -mtriple=riscv64 -mattr=+rva23u64 %s -o - | FileCheck --check-prefix=RVA23U64 %s ; RUN: llc -mtriple=riscv64 -mattr=+rva23s64 %s -o - | FileCheck --check-prefix=RVA23S64 %s -; RUN: llc -mtriple=riscv64 -mattr=+experimental-rvb23u64 %s -o - | FileCheck --check-prefix=RVB23U64 %s -; RUN: llc -mtriple=riscv64 -mattr=+experimental-rvb23s64 %s -o - | FileCheck --check-prefix=RVB23S64 %s +; RUN: llc -mtriple=riscv64 -mattr=+rvb23u64 %s -o - | FileCheck --check-prefix=RVB23U64 %s +; RUN: llc -mtriple=riscv64 -mattr=+rvb23s64 %s -o - | FileCheck --check-prefix=RVB23S64 %s ; RUN: llc -mtriple=riscv32 -mattr=+experimental-rvm23u32 %s -o - | FileCheck --check-prefix=RVM23U32 %s ; CHECK: .attribute 4, 16 diff --git a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp index 48792ad0265fc4..a1d493e12fda6d 100644 --- a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp +++ b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp @@ -1138,12 +1138,12 @@ Supported Profiles rva22u64 rva23s64 rva23u64 + rvb23s64 + rvb23u64 rvi20u32 rvi20u64 Experimental Profiles - rvb23s64 - rvb23u64 rvm23u32 Use -march to specify the target's extension. >From b3f5bfec588e4961077a7836ad051a87372ca8f3 Mon Sep 17 00:00:00 2001 From: Alex Bradbury <a...@igalia.com> Date: Mon, 28 Oct 2024 18:08:19 +0000 Subject: [PATCH 2/3] [RISCV] Use the 'B' extension in RISC-V profile definitions RVA22 has retrospectively been defined as including 'B' (as it's a shorthand for Zba+Zbb+Zbs, which were previously explicitly enumerated) and RV{A,B,M}23 are defined featuring B. We don't currently infer B whenever Zba+Zbb+Zbs are present due to concerns about compatibility with external assemblers such as gas. --- llvm/lib/Target/RISCV/RISCVProfiles.td | 12 +++--------- llvm/test/CodeGen/RISCV/attributes.ll | 14 +++++++------- 2 files changed, 10 insertions(+), 16 deletions(-) diff --git a/llvm/lib/Target/RISCV/RISCVProfiles.td b/llvm/lib/Target/RISCV/RISCVProfiles.td index cbf2a2eddf38ed..bcb776e682aea7 100644 --- a/llvm/lib/Target/RISCV/RISCVProfiles.td +++ b/llvm/lib/Target/RISCV/RISCVProfiles.td @@ -45,9 +45,7 @@ defvar RVA22U64Features = !listconcat(RVA20U64BaseFeatures, [FeatureStdExtZa64rs, FeatureStdExtZihpm, FeatureStdExtZihintpause, - FeatureStdExtZba, - FeatureStdExtZbb, - FeatureStdExtZbs, + FeatureStdExtB, FeatureStdExtZic64b, FeatureStdExtZicbom, FeatureStdExtZicbop, @@ -92,9 +90,7 @@ defvar RVB23U64Features = !listconcat(RVA20U64BaseFeatures, [FeatureStdExtZihpm, FeatureStdExtZa64rs, FeatureStdExtZihintpause, - FeatureStdExtZba, - FeatureStdExtZbb, - FeatureStdExtZbs, + FeatureStdExtB, FeatureStdExtZic64b, FeatureStdExtZicbom, FeatureStdExtZicbop, @@ -128,9 +124,7 @@ defvar RVB23S64Features = !listconcat(RVB23U64Features, defvar RVM23U32Features = [Feature32Bit, FeatureStdExtI, FeatureStdExtM, - FeatureStdExtZba, - FeatureStdExtZbb, - FeatureStdExtZbs, + FeatureStdExtB, FeatureStdExtZicond, FeatureStdExtZihintpause, FeatureStdExtZihintntl, diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll index c03108c0617e75..8688009f492b94 100644 --- a/llvm/test/CodeGen/RISCV/attributes.ll +++ b/llvm/test/CodeGen/RISCV/attributes.ll @@ -584,13 +584,13 @@ ; RVI20U64: .attribute 5, "rv64i2p1" ; RVA20U64: .attribute 5, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicsr2p0_zmmul1p0_za128rs1p0" ; RVA20S64: .attribute 5, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicsr2p0_zifencei2p0_zmmul1p0_za128rs1p0_ssccptr1p0_sstvala1p0_sstvecd1p0_svade1p0_svbare1p0" -; RVA22U64: .attribute 5, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicsr2p0_zihintpause2p0_zihpm2p0_zmmul1p0_za64rs1p0_zfhmin1p0_zba1p0_zbb1p0_zbs1p0_zkt1p0" -; RVA22S64: .attribute 5, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicsr2p0_zifencei2p0_zihintpause2p0_zihpm2p0_zmmul1p0_za64rs1p0_zfhmin1p0_zba1p0_zbb1p0_zbs1p0_zkt1p0_ssccptr1p0_sscounterenw1p0_sstvala1p0_sstvecd1p0_svade1p0_svbare1p0_svinval1p0_svpbmt1p0" -; RVA23U64: .attribute 5, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_v1p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicond1p0_zicsr2p0_zihintntl1p0_zihintpause2p0_zihpm2p0_zimop1p0_zmmul1p0_za64rs1p0_zawrs1p0_zfa1p0_zfhmin1p0_zca1p0_zcb1p0_zcmop1p0_zba1p0_zbb1p0_zbs1p0_zkt1p0_zvbb1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfhmin1p0_zvkb1p0_zvkt1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_supm1p0" -; RVA23S64: .attribute 5, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_v1p0_h1p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicond1p0_zicsr2p0_zifencei2p0_zihintntl1p0_zihintpause2p0_zihpm2p0_zimop1p0_zmmul1p0_za64rs1p0_zawrs1p0_zfa1p0_zfhmin1p0_zca1p0_zcb1p0_zcmop1p0_zba1p0_zbb1p0_zbs1p0_zkt1p0_zvbb1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfhmin1p0_zvkb1p0_zvkt1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_sha1p0_shcounterenw1p0_shgatpa1p0_shtvala1p0_shvsatpa1p0_shvstvala1p0_shvstvecd1p0_ssccptr1p0_sscofpmf1p0_sscounterenw1p0_ssnpm1p0_ssstateen1p0_sstc1p0_sstvala1p0_sstvecd1p0_ssu64xl1p0_supm1p0_svade1p0_svbare1p0_svinval1p0_svnapot1p0_svpbmt1p0" -; RVB23U64: .attribute 5, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicond1p0_zicsr2p0_zihintntl1p0_zihintpause2p0_zihpm2p0_zimop1p0_zmmul1p0_za64rs1p0_zawrs1p0_zfa1p0_zca1p0_zcb1p0_zcmop1p0_zba1p0_zbb1p0_zbs1p0_zkt1p0" -; RVB23S64: .attribute 5, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicond1p0_zicsr2p0_zifencei2p0_zihintntl1p0_zihintpause2p0_zihpm2p0_zimop1p0_zmmul1p0_za64rs1p0_zawrs1p0_zfa1p0_zca1p0_zcb1p0_zcmop1p0_zba1p0_zbb1p0_zbs1p0_zkt1p0_ssccptr1p0_sscofpmf1p0_sscounterenw1p0_sstc1p0_sstvala1p0_sstvecd1p0_ssu64xl1p0_svade1p0_svbare1p0_svinval1p0_svnapot1p0_svpbmt1p0" -; RVM23U32: .attribute 5, "rv32i2p1_m2p0_zicbop1p0_zicond1p0_zicsr2p0_zihintntl1p0_zihintpause2p0_zimop1p0_zmmul1p0_zca1p0_zcb1p0_zce1p0_zcmop1p0_zcmp1p0_zcmt1p0_zba1p0_zbb1p0_zbs1p0" +; RVA22U64: .attribute 5, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_b1p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicsr2p0_zihintpause2p0_zihpm2p0_zmmul1p0_za64rs1p0_zfhmin1p0_zba1p0_zbb1p0_zbs1p0_zkt1p0" +; RVA22S64: .attribute 5, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_b1p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicsr2p0_zifencei2p0_zihintpause2p0_zihpm2p0_zmmul1p0_za64rs1p0_zfhmin1p0_zba1p0_zbb1p0_zbs1p0_zkt1p0_ssccptr1p0_sscounterenw1p0_sstvala1p0_sstvecd1p0_svade1p0_svbare1p0_svinval1p0_svpbmt1p0" +; RVA23U64: .attribute 5, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_b1p0_v1p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicond1p0_zicsr2p0_zihintntl1p0_zihintpause2p0_zihpm2p0_zimop1p0_zmmul1p0_za64rs1p0_zawrs1p0_zfa1p0_zfhmin1p0_zca1p0_zcb1p0_zcmop1p0_zba1p0_zbb1p0_zbs1p0_zkt1p0_zvbb1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfhmin1p0_zvkb1p0_zvkt1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_supm1p0" +; RVA23S64: .attribute 5, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_b1p0_v1p0_h1p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicond1p0_zicsr2p0_zifencei2p0_zihintntl1p0_zihintpause2p0_zihpm2p0_zimop1p0_zmmul1p0_za64rs1p0_zawrs1p0_zfa1p0_zfhmin1p0_zca1p0_zcb1p0_zcmop1p0_zba1p0_zbb1p0_zbs1p0_zkt1p0_zvbb1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfhmin1p0_zvkb1p0_zvkt1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_sha1p0_shcounterenw1p0_shgatpa1p0_shtvala1p0_shvsatpa1p0_shvstvala1p0_shvstvecd1p0_ssccptr1p0_sscofpmf1p0_sscounterenw1p0_ssnpm1p0_ssstateen1p0_sstc1p0_sstvala1p0_sstvecd1p0_ssu64xl1p0_supm1p0_svade1p0_svbare1p0_svinval1p0_svnapot1p0_svpbmt1p0" +; RVB23U64: .attribute 5, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_b1p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicond1p0_zicsr2p0_zihintntl1p0_zihintpause2p0_zihpm2p0_zimop1p0_zmmul1p0_za64rs1p0_zawrs1p0_zfa1p0_zca1p0_zcb1p0_zcmop1p0_zba1p0_zbb1p0_zbs1p0_zkt1p0" +; RVB23S64: .attribute 5, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_b1p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicond1p0_zicsr2p0_zifencei2p0_zihintntl1p0_zihintpause2p0_zihpm2p0_zimop1p0_zmmul1p0_za64rs1p0_zawrs1p0_zfa1p0_zca1p0_zcb1p0_zcmop1p0_zba1p0_zbb1p0_zbs1p0_zkt1p0_ssccptr1p0_sscofpmf1p0_sscounterenw1p0_sstc1p0_sstvala1p0_sstvecd1p0_ssu64xl1p0_svade1p0_svbare1p0_svinval1p0_svnapot1p0_svpbmt1p0" +; RVM23U32: .attribute 5, "rv32i2p1_m2p0_b1p0_zicbop1p0_zicond1p0_zicsr2p0_zihintntl1p0_zihintpause2p0_zimop1p0_zmmul1p0_zca1p0_zcb1p0_zce1p0_zcmop1p0_zcmp1p0_zcmt1p0_zba1p0_zbb1p0_zbs1p0" define i32 @addi(i32 %a) { %1 = add i32 %a, 1 >From 9501ce38c9a2e13541f76aa32b1eb7ed3cc62d06 Mon Sep 17 00:00:00 2001 From: Alex Bradbury <a...@igalia.com> Date: Sat, 9 Nov 2024 10:48:38 +0000 Subject: [PATCH 3/3] Add CHECK lines to clang/test/Driver/riscv-profiles.c --- clang/test/Driver/riscv-profiles.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/clang/test/Driver/riscv-profiles.c b/clang/test/Driver/riscv-profiles.c index 67e09d0e69ebc3..c87ec5a27822c5 100644 --- a/clang/test/Driver/riscv-profiles.c +++ b/clang/test/Driver/riscv-profiles.c @@ -57,6 +57,7 @@ // RVA22U64: "-target-feature" "+f" // RVA22U64: "-target-feature" "+d" // RVA22U64: "-target-feature" "+c" +// RVA22U64: "-target-feature" "+b" // RVA22U64: "-target-feature" "+zic64b" // RVA22U64: "-target-feature" "+zicbom" // RVA22U64: "-target-feature" "+zicbop" @@ -83,6 +84,7 @@ // RVA22S64: "-target-feature" "+f" // RVA22S64: "-target-feature" "+d" // RVA22S64: "-target-feature" "+c" +// RVA22S64: "-target-feature" "+b" // RVA22S64: "-target-feature" "+zic64b" // RVA22S64: "-target-feature" "+zicbom" // RVA22S64: "-target-feature" "+zicbop" @@ -118,6 +120,7 @@ // RVA23U64: "-target-feature" "+f" // RVA23U64: "-target-feature" "+d" // RVA23U64: "-target-feature" "+c" +// RVA23U64: "-target-feature" "+b" // RVA23U64: "-target-feature" "+v" // RVA23U64: "-target-feature" "+zic64b" // RVA23U64: "-target-feature" "+zicbom" @@ -156,6 +159,7 @@ // RVA23S64: "-target-feature" "+f" // RVA23S64: "-target-feature" "+d" // RVA23S64: "-target-feature" "+c" +// RVA23S64: "-target-feature" "+b" // RVA23S64: "-target-feature" "+v" // RVA23S64: "-target-feature" "+h" // RVA23S64: "-target-feature" "+zic64b" @@ -217,6 +221,7 @@ // RVB23U64: "-target-feature" "+f" // RVB23U64: "-target-feature" "+d" // RVB23U64: "-target-feature" "+c" +// RVB23U64: "-target-feature" "+b" // RVB23U64: "-target-feature" "+zic64b" // RVB23U64: "-target-feature" "+zicbom" // RVB23U64: "-target-feature" "+zicbop" @@ -249,6 +254,7 @@ // RVB23S64: "-target-feature" "+f" // RVB23S64: "-target-feature" "+d" // RVB23S64: "-target-feature" "+c" +// RVB23S64: "-target-feature" "+b" // RVB23S64: "-target-feature" "+zic64b" // RVB23S64: "-target-feature" "+zicbom" // RVB23S64: "-target-feature" "+zicbop" @@ -290,6 +296,7 @@ // RUN: %clang --target=riscv32 -### -c %s 2>&1 -march=rvm23u32 -menable-experimental-extensions \ // RUN: | FileCheck -check-prefix=RVM23U32 %s // RVM23U32: "-target-feature" "+m" +// RVM23U32: "-target-feature" "+b" // RVM23U32: "-target-feature" "+zicbop" // RVM23U32: "-target-feature" "+zicond" // RVM23U32: "-target-feature" "+zicsr" @@ -309,6 +316,7 @@ // PROFILE-WITH-ADDITIONAL: "-target-feature" "+f" // PROFILE-WITH-ADDITIONAL: "-target-feature" "+d" // PROFILE-WITH-ADDITIONAL: "-target-feature" "+c" +// PROFILE-WITH-ADDITIONAL: "-target-feature" "+b" // PROFILE-WITH-ADDITIONAL: "-target-feature" "+zicbom" // PROFILE-WITH-ADDITIONAL: "-target-feature" "+zicbop" // PROFILE-WITH-ADDITIONAL: "-target-feature" "+zicboz" _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
