================
@@ -267,3 +267,42 @@ let Predicates = [HasAMXCOMPLEX, In64BitMode] in {
}
} // SchedRW = [WriteSystem]
}
+
+// AMX-FP8
+let Predicates = [HasAMXFP8, In64BitMode] in {
+ let SchedRW = [WriteSystem] in {
+ let Constraints = "$src1 = $dst" in {
+ class AMX_FP8_BASE<bits<8> Opcode, string Opstr> :
+ I<Opcode, MRMSrcReg4VOp3, (outs TILE:$dst),
+ (ins TILE:$src1, TILE:$src2, TILE:$src3),
+ !strconcat(Opstr, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
+ []>, VEX, VVVV;
+ }
+
+ def TDPBF8PS : AMX_FP8_BASE<0xfd, "tdpbf8ps">, T_MAP5, PS;
+ def TDPBHF8PS : AMX_FP8_BASE<0xfd, "tdpbhf8ps">, T_MAP5, XD;
+ def TDPHBF8PS : AMX_FP8_BASE<0xfd, "tdphbf8ps">, T_MAP5, XS;
+ def TDPHF8PS : AMX_FP8_BASE<0xfd, "tdphf8ps">, T_MAP5, PD;
+
+ let usesCustomInserter = 1 in {
+ // Pseudo instructions, using immediates instead of tile registers.
+ // To be translated to the actual instructions in X86ISelLowering.cpp
+ def PTDPBF8PS : PseudoI<(outs), (ins u8imm:$src1,
+ u8imm:$src2, u8imm:$src3),
+ [(int_x86_tdpbf8ps timm:$src1,
+ timm:$src2, timm:$src3)]>;
+ def PTDPBHF8PS : PseudoI<(outs), (ins u8imm:$src1,
+ u8imm:$src2, u8imm:$src3),
+ [(int_x86_tdpbhf8ps timm:$src1,
+ timm:$src2, timm:$src3)]>;
+ def PTDPHBF8PS : PseudoI<(outs), (ins u8imm:$src1,
+ u8imm:$src2, u8imm:$src3),
+ [(int_x86_tdphbf8ps timm:$src1,
+ timm:$src2, timm:$src3)]>;
+ def PTDPHF8PS : PseudoI<(outs), (ins u8imm:$src1,
+ u8imm:$src2, u8imm:$src3),
+ [(int_x86_tdphf8ps timm:$src1,
+ timm:$src2, timm:$src3)]>;
----------------
phoebewang wrote:
ditto.
https://github.com/llvm/llvm-project/pull/113850
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