https://github.com/asb created https://github.com/llvm/llvm-project/pull/113918
The specification was recently ratified <https://github.com/riscv/riscv-profiles/blob/main/src/rvb23-profile.adoc>. >From 47418b35a6e3e02eb20ff7b81f45571bf1322f5b Mon Sep 17 00:00:00 2001 From: Alex Bradbury <a...@igalia.com> Date: Mon, 28 Oct 2024 14:42:44 +0000 Subject: [PATCH] [RISCV] Mark RVB23U64 and RVB23S64 as non-experimental The specification was recently ratified <https://github.com/riscv/riscv-profiles/blob/main/src/rvb23-profile.adoc>. --- clang/test/Driver/print-supported-extensions-riscv.c | 4 ++-- clang/test/Driver/riscv-profiles.c | 4 ++-- llvm/docs/RISCVUsage.rst | 4 ++-- llvm/docs/ReleaseNotes.md | 3 ++- llvm/lib/Target/RISCV/RISCVProfiles.td | 4 ++-- llvm/test/CodeGen/RISCV/attributes.ll | 4 ++-- llvm/unittests/TargetParser/RISCVISAInfoTest.cpp | 4 ++-- 7 files changed, 14 insertions(+), 13 deletions(-) diff --git a/clang/test/Driver/print-supported-extensions-riscv.c b/clang/test/Driver/print-supported-extensions-riscv.c index e39847b9c31a8e..68acde65a74bfb 100644 --- a/clang/test/Driver/print-supported-extensions-riscv.c +++ b/clang/test/Driver/print-supported-extensions-riscv.c @@ -193,12 +193,12 @@ // CHECK-NEXT: rva22u64 // CHECK-NEXT: rva23s64 // CHECK-NEXT: rva23u64 +// CHECK-NEXT: rvb23s64 +// CHECK-NEXT: rvb23u64 // CHECK-NEXT: rvi20u32 // CHECK-NEXT: rvi20u64 // CHECK-EMPTY: // CHECK-NEXT: Experimental Profiles -// CHECK-NEXT: rvb23s64 -// CHECK-NEXT: rvb23u64 // CHECK-NEXT: rvm23u32 // CHECK-EMPTY: // CHECK-NEXT: Use -march to specify the target's extension. diff --git a/clang/test/Driver/riscv-profiles.c b/clang/test/Driver/riscv-profiles.c index d85ac8baf4edd9..2b4d19422874cf 100644 --- a/clang/test/Driver/riscv-profiles.c +++ b/clang/test/Driver/riscv-profiles.c @@ -207,7 +207,7 @@ // RVA23S64: "-target-feature" "+svnapot" // RVA23S64: "-target-feature" "+svpbmt" -// RUN: %clang --target=riscv64 -### -c %s 2>&1 -march=rvb23u64 -menable-experimental-extensions \ +// RUN: %clang --target=riscv64 -### -c %s 2>&1 -march=rvb23u64 \ // RUN: | FileCheck -check-prefix=RVB23U64 %s // RVB23U64: "-target-feature" "+m" // RVB23U64: "-target-feature" "+a" @@ -239,7 +239,7 @@ // RVB23U64: "-target-feature" "+zbs" // RVB23U64: "-target-feature" "+zkt" -// RUN: %clang --target=riscv64 -### -c %s 2>&1 -march=rvb23s64 -menable-experimental-extensions \ +// RUN: %clang --target=riscv64 -### -c %s 2>&1 -march=rvb23s64 \ // RUN: | FileCheck -check-prefix=RVB23S64 %s // RVB23S64: "-target-feature" "+m" // RVB23S64: "-target-feature" "+a" diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst index 04f2c357766d44..f6f2eb45c49c17 100644 --- a/llvm/docs/RISCVUsage.rst +++ b/llvm/docs/RISCVUsage.rst @@ -84,6 +84,8 @@ ISA naming string. Currently supported profiles: * ``rva22s64`` * ``rva23u64`` * ``rva23s64`` +* ``rvb23u64`` +* ``rvb23s64`` Note that you can also append additional extension names to be enabled, e.g. ``rva20u64_zicond`` will enable the ``zicond`` extension in addition to those @@ -93,8 +95,6 @@ Profiles that are not yet ratified cannot be used unless ``-menable-experimental-extensions`` (or equivalent for other tools) is specified. This applies to the following profiles: -* ``rvb23u64`` -* ``rvb23s64`` * ``rvm23u32`` .. _riscv-extensions: diff --git a/llvm/docs/ReleaseNotes.md b/llvm/docs/ReleaseNotes.md index ac7a795daf791a..92a45d845f1db8 100644 --- a/llvm/docs/ReleaseNotes.md +++ b/llvm/docs/ReleaseNotes.md @@ -184,7 +184,8 @@ Changes to the RISC-V Backend * The `Smmpm`, `Smnpm`, `Ssnpm`, `Supm`, and `Sspm` pointer masking extensions are no longer marked as experimental. * The `Sha` extension is now supported. -* The RVA23U64 and RVA23S64 profiles are no longer marked as experimental. +* The RVA23U64, RVA23S64, RVB23U64, and RVB23S64 profiles are no longer marked + as experimental. Changes to the WebAssembly Backend ---------------------------------- diff --git a/llvm/lib/Target/RISCV/RISCVProfiles.td b/llvm/lib/Target/RISCV/RISCVProfiles.td index ea0fe08abd7a14..cbf2a2eddf38ed 100644 --- a/llvm/lib/Target/RISCV/RISCVProfiles.td +++ b/llvm/lib/Target/RISCV/RISCVProfiles.td @@ -163,6 +163,6 @@ def RVA22U64 : RISCVProfile<"rva22u64", RVA22U64Features>; def RVA22S64 : RISCVProfile<"rva22s64", RVA22S64Features>; def RVA23U64 : RISCVProfile<"rva23u64", RVA23U64Features>; def RVA23S64 : RISCVProfile<"rva23s64", RVA23S64Features>; -def RVB23U64 : RISCVExperimentalProfile<"rvb23u64", RVB23U64Features>; -def RVB23S64 : RISCVExperimentalProfile<"rvb23s64", RVB23S64Features>; +def RVB23U64 : RISCVProfile<"rvb23u64", RVB23U64Features>; +def RVB23S64 : RISCVProfile<"rvb23s64", RVB23S64Features>; def RVM23U32 : RISCVExperimentalProfile<"rvm23u32", RVM23U32Features>; diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll index 2545c7075e4cf5..c03108c0617e75 100644 --- a/llvm/test/CodeGen/RISCV/attributes.ll +++ b/llvm/test/CodeGen/RISCV/attributes.ll @@ -293,8 +293,8 @@ ; RUN: llc -mtriple=riscv64 -mattr=+rva22s64 %s -o - | FileCheck --check-prefix=RVA22S64 %s ; RUN: llc -mtriple=riscv64 -mattr=+rva23u64 %s -o - | FileCheck --check-prefix=RVA23U64 %s ; RUN: llc -mtriple=riscv64 -mattr=+rva23s64 %s -o - | FileCheck --check-prefix=RVA23S64 %s -; RUN: llc -mtriple=riscv64 -mattr=+experimental-rvb23u64 %s -o - | FileCheck --check-prefix=RVB23U64 %s -; RUN: llc -mtriple=riscv64 -mattr=+experimental-rvb23s64 %s -o - | FileCheck --check-prefix=RVB23S64 %s +; RUN: llc -mtriple=riscv64 -mattr=+rvb23u64 %s -o - | FileCheck --check-prefix=RVB23U64 %s +; RUN: llc -mtriple=riscv64 -mattr=+rvb23s64 %s -o - | FileCheck --check-prefix=RVB23S64 %s ; RUN: llc -mtriple=riscv32 -mattr=+experimental-rvm23u32 %s -o - | FileCheck --check-prefix=RVM23U32 %s ; CHECK: .attribute 4, 16 diff --git a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp index 48792ad0265fc4..a1d493e12fda6d 100644 --- a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp +++ b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp @@ -1138,12 +1138,12 @@ Supported Profiles rva22u64 rva23s64 rva23u64 + rvb23s64 + rvb23u64 rvi20u32 rvi20u64 Experimental Profiles - rvb23s64 - rvb23u64 rvm23u32 Use -march to specify the target's extension. _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
