https://github.com/asb created https://github.com/llvm/llvm-project/pull/113826
All of the extensions used by these profile are themselves non-experimental, and RVA23 was just ratified <https://riscv.org/announcements/2024/10/risc-v-announces-ratification-of-the-rva23-profile-standard/>. <https://github.com/riscv/riscv-profiles/blob/main/src/rva23-profile.adoc> We lack a way of expressing `Ss1p13` (supervisor architecture 1.13), but this is a problem we have for RVA22 (Ss1p12) and RVA20 (Ss1p11) so I don't feel it's a blocker. Stacks on top of #113823. I have of course made this check myself, but it would be helpful for reviewers to step through the extension list we enable vs the ratified RVA23 to triple-check all is in order. >From 0a6e4734def4cb8a3a601c0f4a4f4d5cdea3c990 Mon Sep 17 00:00:00 2001 From: Alex Bradbury <a...@igalia.com> Date: Sun, 27 Oct 2024 15:40:21 +0000 Subject: [PATCH 1/3] [RISCV] Add the Sha extension This was introduced in the now-ratified RVA23 profile (and also added to the RVA22 text) as a simple way of referring to H plus the set of supervisor extensions required by RVA23. --- clang/test/Driver/print-supported-extensions-riscv.c | 1 + clang/test/Preprocessor/riscv-target-features.c | 9 +++++++++ llvm/docs/RISCVUsage.rst | 1 + llvm/docs/ReleaseNotes.md | 1 + llvm/lib/Target/RISCV/RISCVFeatures.td | 7 +++++++ llvm/test/CodeGen/RISCV/attributes.ll | 4 ++++ llvm/unittests/TargetParser/RISCVISAInfoTest.cpp | 1 + 7 files changed, 24 insertions(+) diff --git a/clang/test/Driver/print-supported-extensions-riscv.c b/clang/test/Driver/print-supported-extensions-riscv.c index 342d6e921a5a83..fc8a9c04667b6b 100644 --- a/clang/test/Driver/print-supported-extensions-riscv.c +++ b/clang/test/Driver/print-supported-extensions-riscv.c @@ -110,6 +110,7 @@ // CHECK-NEXT: zvl8192b 1.0 'Zvl' (Minimum Vector Length) 8192 // CHECK-NEXT: zhinx 1.0 'Zhinx' (Half Float in Integer) // CHECK-NEXT: zhinxmin 1.0 'Zhinxmin' (Half Float in Integer Minimal) +// CHECK-NEXT: sha 1.0 'Sha' (Augmented Hypervisor) // CHECK-NEXT: shcounterenw 1.0 'Shcounterenw' (Support writeable hcounteren enable bit for any hpmcounter that is not read-only zero) // CHECK-NEXT: shgatpa 1.0 'Sgatpa' (SvNNx4 mode supported for all modes supported by satp, as well as Bare) // CHECK-NEXT: shtvala 1.0 'Shtvala' (htval provides all needed values) diff --git a/clang/test/Preprocessor/riscv-target-features.c b/clang/test/Preprocessor/riscv-target-features.c index 98ad564d2b8408..6e586714af84d3 100644 --- a/clang/test/Preprocessor/riscv-target-features.c +++ b/clang/test/Preprocessor/riscv-target-features.c @@ -20,6 +20,7 @@ // CHECK-NOT: __riscv_m {{.*$}} // CHECK-NOT: __riscv_mul {{.*$}} // CHECK-NOT: __riscv_muldiv {{.*$}} +// CHECK-NOT: __riscv_sha {{.*$}} // CHECK-NOT: __riscv_shcounterenw {{.*$}} // CHECK-NOT: __riscv_shgatpa {{.*$}} // CHECK-NOT: __riscv_shtvala {{.*$}} @@ -323,6 +324,14 @@ // CHECK-M-EXT: __riscv_mul 1 // CHECK-M-EXT: __riscv_muldiv 1 +// RUN: %clang --target=riscv32-unknown-linux-gnu \ +// RUN: -march=rv32isha -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-SHCOUNTERENW-EXT %s +// RUN: %clang --target=riscv64-unknown-linux-gnu \ +// RUN: -march=rv64isha -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-SHCOUNTERENW-EXT %s +// CHECK-SHA-EXT: __riscv_sha 1000000{{$}} + // RUN: %clang --target=riscv32-unknown-linux-gnu \ // RUN: -march=rv32ishcounterenw -E -dM %s \ // RUN: -o - | FileCheck --check-prefix=CHECK-SHCOUNTERENW-EXT %s diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst index ab58cdaa1b2f95..6075a2289d473d 100644 --- a/llvm/docs/RISCVUsage.rst +++ b/llvm/docs/RISCVUsage.rst @@ -119,6 +119,7 @@ on support follow. ``E`` Supported (`See note <#riscv-rve-note>`__) ``H`` Assembly Support ``M`` Supported + ``Sha`` Supported ``Shcounterenw`` Assembly Support (`See note <#riscv-profiles-extensions-note>`__) ``Shgatpa`` Assembly Support (`See note <#riscv-profiles-extensions-note>`__) ``Shtvala`` Assembly Support (`See note <#riscv-profiles-extensions-note>`__) diff --git a/llvm/docs/ReleaseNotes.md b/llvm/docs/ReleaseNotes.md index e3d93f0dfd0ec5..6ee312aee8c53c 100644 --- a/llvm/docs/ReleaseNotes.md +++ b/llvm/docs/ReleaseNotes.md @@ -176,6 +176,7 @@ Changes to the RISC-V Backend * The `Zacas` extension is no longer marked as experimental. * The `Smmpm`, `Smnpm`, `Ssnpm`, `Supm`, and `Sspm` pointer masking extensions are no longer marked as experimental. +* The `Sha` extension is now supported. Changes to the WebAssembly Backend ---------------------------------- diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td index 778df542022f22..559f0e5950eddd 100644 --- a/llvm/lib/Target/RISCV/RISCVFeatures.td +++ b/llvm/lib/Target/RISCV/RISCVFeatures.td @@ -1029,6 +1029,13 @@ def FeatureStdExtSvpbmt : RISCVExtension<"svpbmt", 1, 0, "'Svpbmt' (Page-Based Memory Types)">; +def FeatureStdExtSha + : RISCVExtension<"sha", 1, 0, + "'Sha' (Augmented Hypervisor)", + [FeatureStdExtH, FeatureStdExtSsstateen, FeatureStdExtShcounterenw, + FeatureStdExtShvstvala, FeatureStdExtShtvala, FeatureStdExtShvstvecd, + FeatureStdExtShvsatpa, FeatureStdExtShgatpa]>; + // Pointer Masking extensions // A supervisor-level extension that provides pointer masking for the next lower diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll index 9be9ddd05ee290..4cc9ef2ea0d7ff 100644 --- a/llvm/test/CodeGen/RISCV/attributes.ll +++ b/llvm/test/CodeGen/RISCV/attributes.ll @@ -39,6 +39,7 @@ ; RUN: llc -mtriple=riscv32 -mattr=+zicbom %s -o - | FileCheck --check-prefixes=CHECK,RV32ZICBOM %s ; RUN: llc -mtriple=riscv32 -mattr=+zicboz %s -o - | FileCheck --check-prefixes=CHECK,RV32ZICBOZ %s ; RUN: llc -mtriple=riscv32 -mattr=+zicbop %s -o - | FileCheck --check-prefixes=CHECK,RV32ZICBOP %s +; RUN: llc -mtriple=riscv32 -mattr=+sha %s -o - | FileCheck --check-prefixes=CHECK,RV32SHA %s ; RUN: llc -mtriple=riscv32 -mattr=+shcounterenw %s -o - | FileCheck --check-prefixes=CHECK,RV32SHCOUNTERENW %s ; RUN: llc -mtriple=riscv32 -mattr=+shgatpa %s -o - | FileCheck --check-prefixes=CHECK,RV32SHGATPA %s ; RUN: llc -mtriple=riscv32 -mattr=+shvsatpa %s -o - | FileCheck --check-prefixes=CHECK,RV32SHVSATPA %s @@ -178,6 +179,7 @@ ; RUN: llc -mtriple=riscv64 -mattr=+zicbom %s -o - | FileCheck --check-prefixes=CHECK,RV64ZICBOM %s ; RUN: llc -mtriple=riscv64 -mattr=+zicboz %s -o - | FileCheck --check-prefixes=CHECK,RV64ZICBOZ %s ; RUN: llc -mtriple=riscv64 -mattr=+zicbop %s -o - | FileCheck --check-prefixes=CHECK,RV64ZICBOP %s +; RUN: llc -mtriple=riscv64 -mattr=+sha %s -o - | FileCheck --check-prefixes=CHECK,RV64SHA %s ; RUN: llc -mtriple=riscv64 -mattr=+shcounterenw %s -o - | FileCheck --check-prefixes=CHECK,RV64SHCOUNTERENW %s ; RUN: llc -mtriple=riscv64 -mattr=+shgatpa %s -o - | FileCheck --check-prefixes=CHECK,RV64SHGATPA %s ; RUN: llc -mtriple=riscv64 -mattr=+shvsatpa %s -o - | FileCheck --check-prefixes=CHECK,RV64SHVSATPA %s @@ -333,6 +335,7 @@ ; RV32ZICBOM: .attribute 5, "rv32i2p1_zicbom1p0" ; RV32ZICBOZ: .attribute 5, "rv32i2p1_zicboz1p0" ; RV32ZICBOP: .attribute 5, "rv32i2p1_zicbop1p0" +; RV32SHA: .attribute 5, "rv32i2p1_h1p0_sha1p0_shcounterenw1p0_shgatpa1p0_shtvala1p0_shvsatpa1p0_shvstvala1p0_shvstvecd1p0_ssstateen1p0" ; RV32SHCOUNTERENW: .attribute 5, "rv32i2p1_shcounterenw1p0" ; RV32SHGATPA: .attribute 5, "rv32i2p1_shgatpa1p0" ; RV32SHVSATPA: .attribute 5, "rv32i2p1_shvsatpa1p0" @@ -474,6 +477,7 @@ ; RV64ZAMA16B: .attribute 5, "rv64i2p1_zama16b1p0" ; RV64ZAWRS: .attribute 5, "rv64i2p1_zawrs1p0" ; RV64ZICBOP: .attribute 5, "rv64i2p1_zicbop1p0" +; RV64SHA: .attribute 5, "rv64i2p1_h1p0_sha1p0_shcounterenw1p0_shgatpa1p0_shtvala1p0_shvsatpa1p0_shvstvala1p0_shvstvecd1p0_ssstateen1p0" ; RV64SHCOUNTERENW: .attribute 5, "rv64i2p1_shcounterenw1p0" ; RV64SHGATPA: .attribute 5, "rv64i2p1_shgatpa1p0" ; RV64SHVSATPA: .attribute 5, "rv64i2p1_shvsatpa1p0" diff --git a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp index 2e9c548ae872f3..e402b1a40de34d 100644 --- a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp +++ b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp @@ -1055,6 +1055,7 @@ R"(All available -march extensions for RISC-V zvl8192b 1.0 zhinx 1.0 zhinxmin 1.0 + sha 1.0 shcounterenw 1.0 shgatpa 1.0 shtvala 1.0 >From 04f3b2da46ac398d8ad391889cee8ed45f721cdf Mon Sep 17 00:00:00 2001 From: Alex Bradbury <a...@igalia.com> Date: Sun, 27 Oct 2024 16:27:31 +0000 Subject: [PATCH 2/3] [RISCV] Use Sha extension in RVA23S64 profile In the ratified version of the RVA23S64 definition, the Sha extension is now used to group together the set of hypervisor related extensions. <https://github.com/riscv/riscv-profiles/blob/main/src/rva23-profile.adoc> --- llvm/lib/Target/RISCV/RISCVProfiles.td | 9 +-------- llvm/test/CodeGen/RISCV/attributes.ll | 2 +- 2 files changed, 2 insertions(+), 9 deletions(-) diff --git a/llvm/lib/Target/RISCV/RISCVProfiles.td b/llvm/lib/Target/RISCV/RISCVProfiles.td index ce7d1973989fc1..78c076fdb0b26e 100644 --- a/llvm/lib/Target/RISCV/RISCVProfiles.td +++ b/llvm/lib/Target/RISCV/RISCVProfiles.td @@ -82,14 +82,7 @@ defvar RVA23S64BaseFeatures = !listconcat(RVA22S64BaseFeatures, FeatureStdExtSscofpmf, FeatureStdExtSsnpm, FeatureStdExtSsu64xl, - FeatureStdExtH, - FeatureStdExtSsstateen, - FeatureStdExtShcounterenw, - FeatureStdExtShvstvala, - FeatureStdExtShtvala, - FeatureStdExtShvstvecd, - FeatureStdExtShvsatpa, - FeatureStdExtShgatpa]); + FeatureStdExtSha]); defvar RVA23S64Features = !listconcat(RVA23U64Features, RVA23S64BaseFeatures); diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll index 4cc9ef2ea0d7ff..5c835befd6f505 100644 --- a/llvm/test/CodeGen/RISCV/attributes.ll +++ b/llvm/test/CodeGen/RISCV/attributes.ll @@ -583,7 +583,7 @@ ; RVA22U64: .attribute 5, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicsr2p0_zihintpause2p0_zihpm2p0_zmmul1p0_za64rs1p0_zfhmin1p0_zba1p0_zbb1p0_zbs1p0_zkt1p0" ; RVA22S64: .attribute 5, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicsr2p0_zifencei2p0_zihintpause2p0_zihpm2p0_zmmul1p0_za64rs1p0_zfhmin1p0_zba1p0_zbb1p0_zbs1p0_zkt1p0_ssccptr1p0_sscounterenw1p0_sstvala1p0_sstvecd1p0_svade1p0_svbare1p0_svinval1p0_svpbmt1p0" ; RVA23U64: .attribute 5, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_v1p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicond1p0_zicsr2p0_zihintntl1p0_zihintpause2p0_zihpm2p0_zimop1p0_zmmul1p0_za64rs1p0_zawrs1p0_zfa1p0_zfhmin1p0_zca1p0_zcb1p0_zcmop1p0_zba1p0_zbb1p0_zbs1p0_zkt1p0_zvbb1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfhmin1p0_zvkb1p0_zvkt1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_supm1p0" -; RVA23S64: .attribute 5, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_v1p0_h1p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicond1p0_zicsr2p0_zifencei2p0_zihintntl1p0_zihintpause2p0_zihpm2p0_zimop1p0_zmmul1p0_za64rs1p0_zawrs1p0_zfa1p0_zfhmin1p0_zca1p0_zcb1p0_zcmop1p0_zba1p0_zbb1p0_zbs1p0_zkt1p0_zvbb1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfhmin1p0_zvkb1p0_zvkt1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_shcounterenw1p0_shgatpa1p0_shtvala1p0_shvsatpa1p0_shvstvala1p0_shvstvecd1p0_ssccptr1p0_sscofpmf1p0_sscounterenw1p0_ssnpm1p0_ssstateen1p0_sstc1p0_sstvala1p0_sstvecd1p0_ssu64xl1p0_supm1p0_svade1p0_svbare1p0_svinval1p0_svnapot1p0_svpbmt1p0" +; RVA23S64: .attribute 5, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_v1p0_h1p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicond1p0_zicsr2p0_zifencei2p0_zihintntl1p0_zihintpause2p0_zihpm2p0_zimop1p0_zmmul1p0_za64rs1p0_zawrs1p0_zfa1p0_zfhmin1p0_zca1p0_zcb1p0_zcmop1p0_zba1p0_zbb1p0_zbs1p0_zkt1p0_zvbb1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfhmin1p0_zvkb1p0_zvkt1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_sha1p0_shcounterenw1p0_shgatpa1p0_shtvala1p0_shvsatpa1p0_shvstvala1p0_shvstvecd1p0_ssccptr1p0_sscofpmf1p0_sscounterenw1p0_ssnpm1p0_ssstateen1p0_sstc1p0_sstvala1p0_sstvecd1p0_ssu64xl1p0_supm1p0_svade1p0_svbare1p0_svinval1p0_svnapot1p0_svpbmt1p0" ; RVB23U64: .attribute 5, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicond1p0_zicsr2p0_zihintntl1p0_zihintpause2p0_zihpm2p0_zimop1p0_zmmul1p0_za64rs1p0_zawrs1p0_zfa1p0_zca1p0_zcb1p0_zcmop1p0_zba1p0_zbb1p0_zbs1p0_zkt1p0" ; RVB23S64: .attribute 5, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicond1p0_zicsr2p0_zifencei2p0_zihintntl1p0_zihintpause2p0_zihpm2p0_zimop1p0_zmmul1p0_za64rs1p0_zawrs1p0_zfa1p0_zca1p0_zcb1p0_zcmop1p0_zba1p0_zbb1p0_zbs1p0_zkt1p0_ssccptr1p0_sscofpmf1p0_sscounterenw1p0_sstc1p0_sstvala1p0_sstvecd1p0_ssu64xl1p0_svade1p0_svbare1p0_svinval1p0_svnapot1p0_svpbmt1p0" ; RVM23U32: .attribute 5, "rv32i2p1_m2p0_zicbop1p0_zicond1p0_zicsr2p0_zihintntl1p0_zihintpause2p0_zimop1p0_zmmul1p0_zca1p0_zcb1p0_zce1p0_zcmop1p0_zcmp1p0_zcmt1p0_zba1p0_zbb1p0_zbs1p0" >From 24e50c0face1f5b35651e7120f48e6be3e9bdba5 Mon Sep 17 00:00:00 2001 From: Alex Bradbury <a...@igalia.com> Date: Sun, 27 Oct 2024 17:54:47 +0000 Subject: [PATCH 3/3] [RISCV] Mark the RVA23S64 and RVA23U64 profiles as non-experimental All of the extensions used by these profile are themselves non-experimental, and RVA23 was just ratified <https://riscv.org/announcements/2024/10/risc-v-announces-ratification-of-the-rva23-profile-standard/>. <https://github.com/riscv/riscv-profiles/blob/main/src/rva23-profile.adoc> We lack a way of expressing `Ss1p13` (supervisor architecture 1.13), but this is a problem we have for RVA22 (Ss1p12) and RVA20 (Ss1p11) so I don't feel it's a blocker. --- clang/test/Driver/print-supported-extensions-riscv.c | 4 ++-- clang/test/Driver/riscv-profiles.c | 10 +++++----- llvm/docs/RISCVUsage.rst | 4 ++-- llvm/docs/ReleaseNotes.md | 1 + llvm/lib/Target/RISCV/RISCVProfiles.td | 4 ++-- llvm/test/CodeGen/RISCV/attributes.ll | 4 ++-- llvm/unittests/TargetParser/RISCVISAInfoTest.cpp | 8 ++++---- 7 files changed, 18 insertions(+), 17 deletions(-) diff --git a/clang/test/Driver/print-supported-extensions-riscv.c b/clang/test/Driver/print-supported-extensions-riscv.c index fc8a9c04667b6b..e02d20ce74ef94 100644 --- a/clang/test/Driver/print-supported-extensions-riscv.c +++ b/clang/test/Driver/print-supported-extensions-riscv.c @@ -190,12 +190,12 @@ // CHECK-NEXT: rva20u64 // CHECK-NEXT: rva22s64 // CHECK-NEXT: rva22u64 +// CHECK-NEXT: rva23s64 +// CHECK-NEXT: rva23u64 // CHECK-NEXT: rvi20u32 // CHECK-NEXT: rvi20u64 // CHECK-EMPTY: // CHECK-NEXT: Experimental Profiles -// CHECK-NEXT: rva23s64 -// CHECK-NEXT: rva23u64 // CHECK-NEXT: rvb23s64 // CHECK-NEXT: rvb23u64 // CHECK-NEXT: rvm23u32 diff --git a/clang/test/Driver/riscv-profiles.c b/clang/test/Driver/riscv-profiles.c index 42e23cf57c880f..d85ac8baf4edd9 100644 --- a/clang/test/Driver/riscv-profiles.c +++ b/clang/test/Driver/riscv-profiles.c @@ -111,7 +111,7 @@ // RVA22S64: "-target-feature" "+svinval" // RVA22S64: "-target-feature" "+svpbmt" -// RUN: %clang --target=riscv64 -### -c %s 2>&1 -march=rva23u64 -menable-experimental-extensions \ +// RUN: %clang --target=riscv64 -### -c %s 2>&1 -march=rva23u64 \ // RUN: | FileCheck -check-prefix=RVA23U64 %s // RVA23U64: "-target-feature" "+m" // RVA23U64: "-target-feature" "+a" @@ -148,7 +148,7 @@ // RVA23U64: "-target-feature" "+zvfhmin" // RVA23U64: "-target-feature" "+zvkt" -// RUN: %clang --target=riscv64 -### -c %s 2>&1 -march=rva23s64 -menable-experimental-extensions \ +// RUN: %clang --target=riscv64 -### -c %s 2>&1 -march=rva23s64 \ // RUN: | FileCheck -check-prefix=RVA23S64 %s // RVA23S64: "-target-feature" "+m" // RVA23S64: "-target-feature" "+a" @@ -323,6 +323,6 @@ // RUN: not %clang --target=riscv64 -### -c %s 2>&1 -march=rva22u64zfa | FileCheck -check-prefix=INVALID-ADDITIONAL %s // INVALID-ADDITIONAL: error: invalid arch name 'rva22u64zfa', additional extensions must be after separator '_' -// RUN: not %clang --target=riscv64 -### -c %s 2>&1 -march=rva23u64 | FileCheck -check-prefix=EXPERIMENTAL-NOFLAG %s -// EXPERIMENTAL-NOFLAG: error: invalid arch name 'rva23u64' -// EXPERIMENTAL-NOFLAG: requires '-menable-experimental-extensions' for profile 'rva23u64' +// RUN: not %clang --target=riscv32 -### -c %s 2>&1 -march=rvm23u32 | FileCheck -check-prefix=EXPERIMENTAL-NOFLAG %s +// EXPERIMENTAL-NOFLAG: error: invalid arch name 'rvm23u32' +// EXPERIMENTAL-NOFLAG: requires '-menable-experimental-extensions' for profile 'rvm23u32' diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst index 6075a2289d473d..9016a154d2fe36 100644 --- a/llvm/docs/RISCVUsage.rst +++ b/llvm/docs/RISCVUsage.rst @@ -82,6 +82,8 @@ ISA naming string. Currently supported profiles: * ``rva20s64`` * ``rva22u64`` * ``rva22s64`` +* ``rva23u64`` +* ``rva23s64`` Note that you can also append additional extension names to be enabled, e.g. ``rva20u64_zicond`` will enable the ``zicond`` extension in addition to those @@ -91,8 +93,6 @@ Profiles that are not yet ratified cannot be used unless ``-menable-experimental-extensions`` (or equivalent for other tools) is specified. This applies to the following profiles: -* ``rva23u64`` -* ``rva23s64`` * ``rvb23u64`` * ``rvb23s64`` * ``rvm23u32`` diff --git a/llvm/docs/ReleaseNotes.md b/llvm/docs/ReleaseNotes.md index 6ee312aee8c53c..90a0d8fc553dfb 100644 --- a/llvm/docs/ReleaseNotes.md +++ b/llvm/docs/ReleaseNotes.md @@ -177,6 +177,7 @@ Changes to the RISC-V Backend * The `Smmpm`, `Smnpm`, `Ssnpm`, `Supm`, and `Sspm` pointer masking extensions are no longer marked as experimental. * The `Sha` extension is now supported. +* The RVA23U64 and RVA23S64 profiles are no longer marked as experimental. Changes to the WebAssembly Backend ---------------------------------- diff --git a/llvm/lib/Target/RISCV/RISCVProfiles.td b/llvm/lib/Target/RISCV/RISCVProfiles.td index 78c076fdb0b26e..ea0fe08abd7a14 100644 --- a/llvm/lib/Target/RISCV/RISCVProfiles.td +++ b/llvm/lib/Target/RISCV/RISCVProfiles.td @@ -161,8 +161,8 @@ def RVA20U64 : RISCVProfile<"rva20u64", RVA20U64Features>; def RVA20S64 : RISCVProfile<"rva20s64", RVA20S64Features>; def RVA22U64 : RISCVProfile<"rva22u64", RVA22U64Features>; def RVA22S64 : RISCVProfile<"rva22s64", RVA22S64Features>; -def RVA23U64 : RISCVExperimentalProfile<"rva23u64", RVA23U64Features>; -def RVA23S64 : RISCVExperimentalProfile<"rva23s64", RVA23S64Features>; +def RVA23U64 : RISCVProfile<"rva23u64", RVA23U64Features>; +def RVA23S64 : RISCVProfile<"rva23s64", RVA23S64Features>; def RVB23U64 : RISCVExperimentalProfile<"rvb23u64", RVB23U64Features>; def RVB23S64 : RISCVExperimentalProfile<"rvb23s64", RVB23S64Features>; def RVM23U32 : RISCVExperimentalProfile<"rvm23u32", RVM23U32Features>; diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll index 5c835befd6f505..789de4abc6211e 100644 --- a/llvm/test/CodeGen/RISCV/attributes.ll +++ b/llvm/test/CodeGen/RISCV/attributes.ll @@ -289,8 +289,8 @@ ; RUN: llc -mtriple=riscv64 -mattr=+rva20s64 %s -o - | FileCheck --check-prefix=RVA20S64 %s ; RUN: llc -mtriple=riscv64 -mattr=+rva22u64 %s -o - | FileCheck --check-prefix=RVA22U64 %s ; RUN: llc -mtriple=riscv64 -mattr=+rva22s64 %s -o - | FileCheck --check-prefix=RVA22S64 %s -; RUN: llc -mtriple=riscv64 -mattr=+experimental-rva23u64 %s -o - | FileCheck --check-prefix=RVA23U64 %s -; RUN: llc -mtriple=riscv64 -mattr=+experimental-rva23s64 %s -o - | FileCheck --check-prefix=RVA23S64 %s +; RUN: llc -mtriple=riscv64 -mattr=+rva23u64 %s -o - | FileCheck --check-prefix=RVA23U64 %s +; RUN: llc -mtriple=riscv64 -mattr=+rva23s64 %s -o - | FileCheck --check-prefix=RVA23S64 %s ; RUN: llc -mtriple=riscv64 -mattr=+experimental-rvb23u64 %s -o - | FileCheck --check-prefix=RVB23U64 %s ; RUN: llc -mtriple=riscv64 -mattr=+experimental-rvb23s64 %s -o - | FileCheck --check-prefix=RVB23S64 %s ; RUN: llc -mtriple=riscv32 -mattr=+experimental-rvm23u32 %s -o - | FileCheck --check-prefix=RVM23U32 %s diff --git a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp index e402b1a40de34d..bcd3bbfed3479a 100644 --- a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp +++ b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp @@ -774,8 +774,8 @@ TEST(ParseArchString, TEST(ParseArchString, RejectsExperimentalProfilesIfEnableExperimentalExtensionsNotSet) { EXPECT_EQ( - toString(RISCVISAInfo::parseArchString("rva23u64", false).takeError()), - "requires '-menable-experimental-extensions' for profile 'rva23u64'"); + toString(RISCVISAInfo::parseArchString("rvm23u32", false).takeError()), + "requires '-menable-experimental-extensions' for profile 'rvm23u32'"); } TEST(ToFeatures, IIsDroppedAndExperimentalExtensionsArePrefixed) { @@ -1135,12 +1135,12 @@ Supported Profiles rva20u64 rva22s64 rva22u64 + rva23s64 + rva23u64 rvi20u32 rvi20u64 Experimental Profiles - rva23s64 - rva23u64 rvb23s64 rvb23u64 rvm23u32 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
