https://github.com/dong-miao updated
https://github.com/llvm/llvm-project/pull/113758
>From 6424bebfcf16ef9694d7406b0298045da2d426bf Mon Sep 17 00:00:00 2001
From: dong-miao <601183...@qq.com>
Date: Sat, 26 Oct 2024 06:49:04 +0000
Subject: [PATCH 1/4] [RISCV]Add svvptc extensions
---
clang/test/Driver/print-supported-extensions-riscv.c | 1 +
clang/test/Preprocessor/riscv-target-features.c | 9 +++++++++
llvm/docs/RISCVUsage.rst | 1 +
llvm/lib/Target/RISCV/RISCVFeatures.td | 4 ++++
llvm/test/CodeGen/RISCV/attributes.ll | 4 ++++
llvm/test/MC/RISCV/attribute-arch.s | 3 +++
llvm/unittests/TargetParser/RISCVISAInfoTest.cpp | 1 +
7 files changed, 23 insertions(+)
diff --git a/clang/test/Driver/print-supported-extensions-riscv.c
b/clang/test/Driver/print-supported-extensions-riscv.c
index 342d6e921a5a83..2d7376f8fe9401 100644
--- a/clang/test/Driver/print-supported-extensions-riscv.c
+++ b/clang/test/Driver/print-supported-extensions-riscv.c
@@ -146,6 +146,7 @@
// CHECK-NEXT: svinval 1.0 'Svinval' (Fine-Grained
Address-Translation Cache Invalidation)
// CHECK-NEXT: svnapot 1.0 'Svnapot' (NAPOT Translation
Contiguity)
// CHECK-NEXT: svpbmt 1.0 'Svpbmt' (Page-Based Memory
Types)
+// CHECK-NEXT: svvptc 1.0 'Svvptc' (Obviating
Memory-Management Instructions after Marking PTEs Valid)
// CHECK-NEXT: xcvalu 1.0 'XCValu' (CORE-V ALU
Operations)
// CHECK-NEXT: xcvbi 1.0 'XCVbi' (CORE-V Immediate
Branching)
// CHECK-NEXT: xcvbitmanip 1.0 'XCVbitmanip' (CORE-V Bit
Manipulation)
diff --git a/clang/test/Preprocessor/riscv-target-features.c
b/clang/test/Preprocessor/riscv-target-features.c
index 98ad564d2b8408..5b4d42b053edc6 100644
--- a/clang/test/Preprocessor/riscv-target-features.c
+++ b/clang/test/Preprocessor/riscv-target-features.c
@@ -51,6 +51,7 @@
// CHECK-NOT: __riscv_svinval {{.*$}}
// CHECK-NOT: __riscv_svnapot {{.*$}}
// CHECK-NOT: __riscv_svpbmt {{.*$}}
+// CHECK-NOT: __riscv_svvptc {{.*$}}
// CHECK-NOT: __riscv_v {{.*$}}
// CHECK-NOT: __riscv_v_elen {{.*$}}
// CHECK-NOT: __riscv_v_elen_fp {{.*$}}
@@ -507,6 +508,14 @@
// RUN: -o - | FileCheck --check-prefix=CHECK-SVPBMT-EXT %s
// CHECK-SVPBMT-EXT: __riscv_svpbmt 1000000{{$}}
+// RUN: %clang --target=riscv32-unknown-linux-gnu \
+// RUN: -march=rv32isvvptc -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-SVVPTC-EXT %s
+// RUN: %clang --target=riscv64-unknown-linux-gnu \
+// RUN: -march=rv64isvvptc -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-SVVPTC-EXT %s
+// CHECK-SVVPTC-EXT: __riscv_svvptc 1000000{{$}}
+
// RUN: %clang --target=riscv32-unknown-linux-gnu \
// RUN: -march=rv32iv1p0 -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-V-EXT %s
diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index ab58cdaa1b2f95..958168772fe413 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -155,6 +155,7 @@ on support follow.
``Svinval`` Assembly Support
``Svnapot`` Assembly Support
``Svpbmt`` Supported
+ ``Svvptc`` Supported
``V`` Supported
``Za128rs`` Supported (`See note
<#riscv-profiles-extensions-note>`__)
``Za64rs`` Supported (`See note
<#riscv-profiles-extensions-note>`__)
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td
b/llvm/lib/Target/RISCV/RISCVFeatures.td
index 778df542022f22..3b86bc69153631 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -1029,6 +1029,10 @@ def FeatureStdExtSvpbmt
: RISCVExtension<"svpbmt", 1, 0,
"'Svpbmt' (Page-Based Memory Types)">;
+def FeatureStdExtSvvptc
+ : RISCVExtension<"svvptc", 1, 0,
+ "'svvptc' (Obviating Memory-Management Instructions after
Marking PTEs Valid)">;
+
// Pointer Masking extensions
// A supervisor-level extension that provides pointer masking for the next
lower
diff --git a/llvm/test/CodeGen/RISCV/attributes.ll
b/llvm/test/CodeGen/RISCV/attributes.ll
index e9743d484f776f..2d07919e042edc 100644
--- a/llvm/test/CodeGen/RISCV/attributes.ll
+++ b/llvm/test/CodeGen/RISCV/attributes.ll
@@ -62,6 +62,7 @@
; RUN: llc -mtriple=riscv32 -mattr=+svnapot %s -o - | FileCheck
--check-prefixes=CHECK,RV32SVNAPOT %s
; RUN: llc -mtriple=riscv32 -mattr=+svpbmt %s -o - | FileCheck
--check-prefixes=CHECK,RV32SVPBMT %s
; RUN: llc -mtriple=riscv32 -mattr=+svinval %s -o - | FileCheck
--check-prefixes=CHECK,RV32SVINVAL %s
+; RUN: llc -mtriple=riscv32 -mattr=+svvptc %s -o - | FileCheck
--check-prefixes=CHECK,RV32SVVPTC %s
; RUN: llc -mtriple=riscv32 -mattr=+xcvalu %s -o - | FileCheck
--check-prefix=RV32XCVALU %s
; RUN: llc -mtriple=riscv32 -mattr=+xcvbitmanip %s -o - | FileCheck
--check-prefix=RV32XCVBITMANIP %s
; RUN: llc -mtriple=riscv32 -mattr=+xcvelw %s -o - | FileCheck
--check-prefix=RV32XCVELW %s
@@ -201,6 +202,7 @@
; RUN: llc -mtriple=riscv64 -mattr=+svnapot %s -o - | FileCheck
--check-prefixes=CHECK,RV64SVNAPOT %s
; RUN: llc -mtriple=riscv64 -mattr=+svpbmt %s -o - | FileCheck
--check-prefixes=CHECK,RV64SVPBMT %s
; RUN: llc -mtriple=riscv64 -mattr=+svinval %s -o - | FileCheck
--check-prefixes=CHECK,RV64SVINVAL %s
+; RUN: llc -mtriple=riscv64 -mattr=+svvptc %s -o - | FileCheck
--check-prefixes=CHECK,RV64SVVPTC %s
; RUN: llc -mtriple=riscv64 -mattr=+xventanacondops %s -o - | FileCheck
--check-prefixes=CHECK,RV64XVENTANACONDOPS %s
; RUN: llc -mtriple=riscv64 -mattr=+xsfvfwmaccqqq %s -o - | FileCheck
--check-prefix=RV64XSFVFWMACCQQQ %s
; RUN: llc -mtriple=riscv64 -mattr=+xtheadba %s -o - | FileCheck
--check-prefixes=CHECK,RV64XTHEADBA %s
@@ -356,6 +358,7 @@
; RV32SVNAPOT: .attribute 5, "rv32i2p1_svnapot1p0"
; RV32SVPBMT: .attribute 5, "rv32i2p1_svpbmt1p0"
; RV32SVINVAL: .attribute 5, "rv32i2p1_svinval1p0"
+; RV32SVVPTC: .attribute 5, "rv32i2p1_svvptc1p0"
; RV32XCVALU: .attribute 5, "rv32i2p1_xcvalu1p0"
; RV32XCVBITMANIP: .attribute 5, "rv32i2p1_xcvbitmanip1p0"
; RV32XCVELW: .attribute 5, "rv32i2p1_xcvelw1p0"
@@ -497,6 +500,7 @@
; RV64SVNAPOT: .attribute 5, "rv64i2p1_svnapot1p0"
; RV64SVPBMT: .attribute 5, "rv64i2p1_svpbmt1p0"
; RV64SVINVAL: .attribute 5, "rv64i2p1_svinval1p0"
+; RV64SVVPTC: .attribute 5, "rv64i2p1_svvptc1p0"
; RV64XVENTANACONDOPS: .attribute 5, "rv64i2p1_xventanacondops1p0"
; RV64XSFVFWMACCQQQ: .attribute 5,
"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvl32b1p0_xsfvfwmaccqqq1p0"
; RV64XTHEADBA: .attribute 5, "rv64i2p1_xtheadba1p0"
diff --git a/llvm/test/MC/RISCV/attribute-arch.s
b/llvm/test/MC/RISCV/attribute-arch.s
index 2332bcacc99d06..a744a660a7076f 100644
--- a/llvm/test/MC/RISCV/attribute-arch.s
+++ b/llvm/test/MC/RISCV/attribute-arch.s
@@ -375,6 +375,9 @@
.attribute arch, "rv32i_svbare1p0"
# CHECK: attribute 5, "rv32i2p1_svbare1p0"
+.attribute arch, "rv32i_svvptc1p0"
+# CHECK: attribute 5, "rv32i2p1_svvptc1p0"
+
.attribute arch, "rv32i_zfbfmin1p0"
# CHECK: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfbfmin1p0"
diff --git a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
index 2e9c548ae872f3..4e24bcd6632ce9 100644
--- a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
+++ b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
@@ -1091,6 +1091,7 @@ R"(All available -march extensions for RISC-V
svinval 1.0
svnapot 1.0
svpbmt 1.0
+ svvptc 1.0
xcvalu 1.0
xcvbi 1.0
xcvbitmanip 1.0
>From 8bd46d94d6a2032e4664eac33bf3ba4024bcb2c3 Mon Sep 17 00:00:00 2001
From: dong-miao <miaozhendon...@mails.ucas.ac.cn>
Date: Sat, 26 Oct 2024 17:32:05 +0800
Subject: [PATCH 2/4] Update print-supported-extensions-riscv.c
---
clang/test/Driver/print-supported-extensions-riscv.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/clang/test/Driver/print-supported-extensions-riscv.c
b/clang/test/Driver/print-supported-extensions-riscv.c
index 2d7376f8fe9401..342d6e921a5a83 100644
--- a/clang/test/Driver/print-supported-extensions-riscv.c
+++ b/clang/test/Driver/print-supported-extensions-riscv.c
@@ -146,7 +146,6 @@
// CHECK-NEXT: svinval 1.0 'Svinval' (Fine-Grained
Address-Translation Cache Invalidation)
// CHECK-NEXT: svnapot 1.0 'Svnapot' (NAPOT Translation
Contiguity)
// CHECK-NEXT: svpbmt 1.0 'Svpbmt' (Page-Based Memory
Types)
-// CHECK-NEXT: svvptc 1.0 'Svvptc' (Obviating
Memory-Management Instructions after Marking PTEs Valid)
// CHECK-NEXT: xcvalu 1.0 'XCValu' (CORE-V ALU
Operations)
// CHECK-NEXT: xcvbi 1.0 'XCVbi' (CORE-V Immediate
Branching)
// CHECK-NEXT: xcvbitmanip 1.0 'XCVbitmanip' (CORE-V Bit
Manipulation)
>From 5a9b859a0041247ee4db7eda33c932ea6532d083 Mon Sep 17 00:00:00 2001
From: dong-miao <miaozhendon...@mails.ucas.ac.cn>
Date: Sat, 26 Oct 2024 18:13:49 +0800
Subject: [PATCH 3/4] Update print-supported-extensions-riscv.c
---
clang/test/Driver/print-supported-extensions-riscv.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/clang/test/Driver/print-supported-extensions-riscv.c
b/clang/test/Driver/print-supported-extensions-riscv.c
index 342d6e921a5a83..2d7376f8fe9401 100644
--- a/clang/test/Driver/print-supported-extensions-riscv.c
+++ b/clang/test/Driver/print-supported-extensions-riscv.c
@@ -146,6 +146,7 @@
// CHECK-NEXT: svinval 1.0 'Svinval' (Fine-Grained
Address-Translation Cache Invalidation)
// CHECK-NEXT: svnapot 1.0 'Svnapot' (NAPOT Translation
Contiguity)
// CHECK-NEXT: svpbmt 1.0 'Svpbmt' (Page-Based Memory
Types)
+// CHECK-NEXT: svvptc 1.0 'Svvptc' (Obviating
Memory-Management Instructions after Marking PTEs Valid)
// CHECK-NEXT: xcvalu 1.0 'XCValu' (CORE-V ALU
Operations)
// CHECK-NEXT: xcvbi 1.0 'XCVbi' (CORE-V Immediate
Branching)
// CHECK-NEXT: xcvbitmanip 1.0 'XCVbitmanip' (CORE-V Bit
Manipulation)
>From fa4d2a4cb113282b31d72d7a12871cdfdddae001 Mon Sep 17 00:00:00 2001
From: dong-miao <miaozhendon...@mails.ucas.ac.cn>
Date: Sat, 26 Oct 2024 20:01:05 +0800
Subject: [PATCH 4/4] Update print-supported-extensions-riscv.c
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