[clang] [llvm] [HLSL][SPIRV] Added clamp intrinsic (PR #113394)

[Adam Yang via cfe-commits]

https://github.com/adam-yang updated 
https://github.com/llvm/llvm-project/pull/113394

>From 8cf5032a5580b97c4c4965e577374f627fbe0643 Mon Sep 17 00:00:00 2001
From: Adam Yang <31109344+adam-y...@users.noreply.github.com>
Date: Mon, 14 Oct 2024 16:35:45 -0700
Subject: [PATCH 1/6] Added the intrinsics and modified the clang test

---
 clang/lib/CodeGen/CGBuiltin.cpp               |  25 ++-
 clang/test/CodeGenHLSL/builtins/clamp.hlsl    | 174 +++++++++---------
 llvm/include/llvm/IR/IntrinsicsSPIRV.td       |   3 +
 .../Target/SPIRV/SPIRVInstructionSelector.cpp |   6 +
 4 files changed, 122 insertions(+), 86 deletions(-)

diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp
index 1ad950798c2118..1087537ae4ee29 100644
--- a/clang/lib/CodeGen/CGBuiltin.cpp
+++ b/clang/lib/CodeGen/CGBuiltin.cpp
@@ -18665,10 +18665,27 @@ Value *CodeGenFunction::EmitHLSLBuiltinExpr(unsigned 
BuiltinID,
     if (auto *VecTy = Ty->getAs<VectorType>())
       Ty = VecTy->getElementType();
     IsUnsigned = Ty->isUnsignedIntegerType();
-    return Builder.CreateIntrinsic(
-        /*ReturnType=*/OpX->getType(),
-        IsUnsigned ? Intrinsic::dx_uclamp : Intrinsic::dx_clamp,
-        ArrayRef<Value *>{OpX, OpMin, OpMax}, nullptr, "dx.clamp");
+    switch (CGM.getTarget().getTriple().getArch()) {
+    case llvm::Triple::dxil: {
+      return Builder.CreateIntrinsic(
+          /*ReturnType=*/OpX->getType(),
+          IsUnsigned ? Intrinsic::dx_uclamp : Intrinsic::dx_clamp,
+          ArrayRef<Value *>{OpX, OpMin, OpMax}, nullptr, "dx.clamp");
+    } break;
+    case llvm::Triple::spirv: {
+      Intrinsic::ID Intr = Intrinsic::spv_sclamp;
+      if (Ty->isFloatingType()) {
+        Intr = Intrinsic::spv_fclamp;
+      } else if (IsUnsigned) {
+        Intr = Intrinsic::spv_uclamp;
+      }
+      return Builder.CreateIntrinsic(OpX->getType(), Intr,
+                                     ArrayRef<Value *>{OpX, OpMin, OpMax},
+                                     nullptr, "spv.clamp");
+    } break;
+    default:
+      llvm_unreachable("Intrinsic clamp not supported by target architecture");
+    }
   }
   case Builtin::BI__builtin_hlsl_cross: {
     Value *Op0 = EmitScalarExpr(E->getArg(0));
diff --git a/clang/test/CodeGenHLSL/builtins/clamp.hlsl 
b/clang/test/CodeGenHLSL/builtins/clamp.hlsl
index af8f6b9733a071..806e786ae70931 100644
--- a/clang/test/CodeGenHLSL/builtins/clamp.hlsl
+++ b/clang/test/CodeGenHLSL/builtins/clamp.hlsl
@@ -1,133 +1,143 @@
 // RUN: %clang_cc1 -finclude-default-header -triple 
dxil-pc-shadermodel6.3-library %s \
 // RUN:  -fnative-half-type -emit-llvm -disable-llvm-passes -o - | \
-// RUN:  FileCheck %s --check-prefixes=CHECK,NATIVE_HALF
+// RUN:  FileCheck %s --check-prefixes=CHECK,NATIVE_HALF \
+// RUN:  -DSCLAMP="dx.clamp" -DUCLAMP="dx.uclamp" -DFCLAMP="dx.clamp" 
-DFNATTR="noundef"
 // RUN: %clang_cc1 -finclude-default-header -triple 
dxil-pc-shadermodel6.3-library %s \
 // RUN:  -emit-llvm -disable-llvm-passes -o - | \
-// RUN:  FileCheck %s --check-prefixes=CHECK,NO_HALF
+// RUN:  FileCheck %s --check-prefixes=CHECK,NO_HALF \
+// RUN:  -DSCLAMP="dx.clamp" -DUCLAMP="dx.uclamp" -DFCLAMP="dx.clamp" 
-DFNATTR="noundef"
+// RUN: %clang_cc1 -finclude-default-header -triple 
spirv-unknown-vulkan-compute %s \
+// RUN:  -fnative-half-type -emit-llvm -disable-llvm-passes -o - | \
+// RUN:  FileCheck %s --check-prefixes=CHECK,NATIVE_HALF \
+// RUN:  -DSCLAMP="spv.sclamp" -DUCLAMP="spv.uclamp" -DFCLAMP="spv.fclamp" 
-DFNATTR="spir_func noundef"
+// RUN: %clang_cc1 -finclude-default-header -triple 
spirv-unknown-vulkan-compute %s \
+// RUN:  -emit-llvm -disable-llvm-passes -o - | \
+// RUN:  FileCheck %s --check-prefixes=CHECK,NO_HALF \
+// RUN:  -DSCLAMP="spv.sclamp" -DUCLAMP="spv.uclamp" -DFCLAMP="spv.fclamp" 
-DFNATTR="spir_func noundef"
 
 #ifdef __HLSL_ENABLE_16_BIT
-// NATIVE_HALF-LABEL: define noundef i16 @_Z16test_clamp_short
-// NATIVE_HALF: call i16 @llvm.dx.clamp.i16(
+// NATIVE_HALF: define [[FNATTR]] i16 @_Z16test_clamp_short
+// NATIVE_HALF: call i16 @llvm.[[SCLAMP]].i16(
 int16_t test_clamp_short(int16_t p0, int16_t p1) { return clamp(p0, p1,p1); }
-// NATIVE_HALF-LABEL: define noundef <2 x i16> @_Z17test_clamp_short2
-// NATIVE_HALF: call <2 x i16> @llvm.dx.clamp.v2i16(
+// NATIVE_HALF: define [[FNATTR]] <2 x i16> @_Z17test_clamp_short2
+// NATIVE_HALF: call <2 x i16> @llvm.[[SCLAMP]].v2i16(
 int16_t2 test_clamp_short2(int16_t2 p0, int16_t2 p1) { return clamp(p0, 
p1,p1); }
-// NATIVE_HALF-LABEL: define noundef <3 x i16> @_Z17test_clamp_short3
-// NATIVE_HALF: call <3 x i16> @llvm.dx.clamp.v3i16
+// NATIVE_HALF: define [[FNATTR]] <3 x i16> @_Z17test_clamp_short3
+// NATIVE_HALF: call <3 x i16> @llvm.[[SCLAMP]].v3i16
 int16_t3 test_clamp_short3(int16_t3 p0, int16_t3 p1) { return clamp(p0, 
p1,p1); }
-// NATIVE_HALF-LABEL: define noundef <4 x i16> @_Z17test_clamp_short4
-// NATIVE_HALF: call <4 x i16> @llvm.dx.clamp.v4i16
+// NATIVE_HALF: define [[FNATTR]] <4 x i16> @_Z17test_clamp_short4
+// NATIVE_HALF: call <4 x i16> @llvm.[[SCLAMP]].v4i16
 int16_t4 test_clamp_short4(int16_t4 p0, int16_t4 p1) { return clamp(p0, 
p1,p1); }
 
-// NATIVE_HALF-LABEL: define noundef i16 @_Z17test_clamp_ushort
-// NATIVE_HALF: call i16 @llvm.dx.uclamp.i16(
+// NATIVE_HALF: define [[FNATTR]] i16 @_Z17test_clamp_ushort
+// NATIVE_HALF: call i16 @llvm.[[UCLAMP]].i16(
 uint16_t test_clamp_ushort(uint16_t p0, uint16_t p1) { return clamp(p0, 
p1,p1); }
-// NATIVE_HALF-LABEL: define noundef <2 x i16> @_Z18test_clamp_ushort2
-// NATIVE_HALF: call <2 x i16> @llvm.dx.uclamp.v2i16
+// NATIVE_HALF: define [[FNATTR]] <2 x i16> @_Z18test_clamp_ushort2
+// NATIVE_HALF: call <2 x i16> @llvm.[[UCLAMP]].v2i16
 uint16_t2 test_clamp_ushort2(uint16_t2 p0, uint16_t2 p1) { return clamp(p0, 
p1,p1); }
-// NATIVE_HALF-LABEL: define noundef <3 x i16> @_Z18test_clamp_ushort3
-// NATIVE_HALF: call <3 x i16> @llvm.dx.uclamp.v3i16
+// NATIVE_HALF: define [[FNATTR]] <3 x i16> @_Z18test_clamp_ushort3
+// NATIVE_HALF: call <3 x i16> @llvm.[[UCLAMP]].v3i16
 uint16_t3 test_clamp_ushort3(uint16_t3 p0, uint16_t3 p1) { return clamp(p0, 
p1,p1); }
-// NATIVE_HALF-LABEL: define noundef <4 x i16> @_Z18test_clamp_ushort4
-// NATIVE_HALF: call <4 x i16> @llvm.dx.uclamp.v4i16
+// NATIVE_HALF: define [[FNATTR]] <4 x i16> @_Z18test_clamp_ushort4
+// NATIVE_HALF: call <4 x i16> @llvm.[[UCLAMP]].v4i16
 uint16_t4 test_clamp_ushort4(uint16_t4 p0, uint16_t4 p1) { return clamp(p0, 
p1,p1); }
 #endif
 
-// CHECK-LABEL: define noundef i32 @_Z14test_clamp_int
-// CHECK: call i32 @llvm.dx.clamp.i32(
+// CHECK: define [[FNATTR]] i32 @_Z14test_clamp_int
+// CHECK: call i32 @llvm.[[SCLAMP]].i32(
 int test_clamp_int(int p0, int p1) { return clamp(p0, p1,p1); }
-// CHECK-LABEL: define noundef <2 x i32> @_Z15test_clamp_int2
-// CHECK: call <2 x i32> @llvm.dx.clamp.v2i32
+// CHECK: define [[FNATTR]] <2 x i32> @_Z15test_clamp_int2
+// CHECK: call <2 x i32> @llvm.[[SCLAMP]].v2i32
 int2 test_clamp_int2(int2 p0, int2 p1) { return clamp(p0, p1,p1); }
-// CHECK-LABEL: define noundef <3 x i32> @_Z15test_clamp_int3
-// CHECK: call <3 x i32> @llvm.dx.clamp.v3i32
+// CHECK: define [[FNATTR]] <3 x i32> @_Z15test_clamp_int3
+// CHECK: call <3 x i32> @llvm.[[SCLAMP]].v3i32
 int3 test_clamp_int3(int3 p0, int3 p1) { return clamp(p0, p1,p1); }
-// CHECK-LABEL: define noundef <4 x i32> @_Z15test_clamp_int4
-// CHECK: call <4 x i32> @llvm.dx.clamp.v4i32
+// CHECK: define [[FNATTR]] <4 x i32> @_Z15test_clamp_int4
+// CHECK: call <4 x i32> @llvm.[[SCLAMP]].v4i32
 int4 test_clamp_int4(int4 p0, int4 p1) { return clamp(p0, p1,p1); }
 
-// CHECK-LABEL: define noundef i32 @_Z15test_clamp_uint
-// CHECK: call i32 @llvm.dx.uclamp.i32(
+// CHECK: define [[FNATTR]] i32 @_Z15test_clamp_uint
+// CHECK: call i32 @llvm.[[UCLAMP]].i32(
 int test_clamp_uint(uint p0, uint p1) { return clamp(p0, p1,p1); }
-// CHECK-LABEL: define noundef <2 x i32> @_Z16test_clamp_uint2
-// CHECK: call <2 x i32> @llvm.dx.uclamp.v2i32
+// CHECK: define [[FNATTR]] <2 x i32> @_Z16test_clamp_uint2
+// CHECK: call <2 x i32> @llvm.[[UCLAMP]].v2i32
 uint2 test_clamp_uint2(uint2 p0, uint2 p1) { return clamp(p0, p1,p1); }
-// CHECK-LABEL: define noundef <3 x i32> @_Z16test_clamp_uint3
-// CHECK: call <3 x i32> @llvm.dx.uclamp.v3i32
+// CHECK: define [[FNATTR]] <3 x i32> @_Z16test_clamp_uint3
+// CHECK: call <3 x i32> @llvm.[[UCLAMP]].v3i32
 uint3 test_clamp_uint3(uint3 p0, uint3 p1) { return clamp(p0, p1,p1); }
-// CHECK-LABEL: define noundef <4 x i32> @_Z16test_clamp_uint4
-// CHECK: call <4 x i32> @llvm.dx.uclamp.v4i32
+// CHECK: define [[FNATTR]] <4 x i32> @_Z16test_clamp_uint4
+// CHECK: call <4 x i32> @llvm.[[UCLAMP]].v4i32
 uint4 test_clamp_uint4(uint4 p0, uint4 p1) { return clamp(p0, p1,p1); }
 
-// CHECK-LABEL: define noundef i64 @_Z15test_clamp_long
-// CHECK: call i64 @llvm.dx.clamp.i64(
+// CHECK: define [[FNATTR]] i64 @_Z15test_clamp_long
+// CHECK: call i64 @llvm.[[SCLAMP]].i64(
 int64_t test_clamp_long(int64_t p0, int64_t p1) { return clamp(p0, p1,p1); }
-// CHECK-LABEL: define noundef <2 x i64> @_Z16test_clamp_long2
-// CHECK: call <2 x i64> @llvm.dx.clamp.v2i64
+// CHECK: define [[FNATTR]] <2 x i64> @_Z16test_clamp_long2
+// CHECK: call <2 x i64> @llvm.[[SCLAMP]].v2i64
 int64_t2 test_clamp_long2(int64_t2 p0, int64_t2 p1) { return clamp(p0, p1,p1); 
}
-// CHECK-LABEL: define noundef <3 x i64> @_Z16test_clamp_long3
-// CHECK: call <3 x i64> @llvm.dx.clamp.v3i64
+// CHECK: define [[FNATTR]] <3 x i64> @_Z16test_clamp_long3
+// CHECK: call <3 x i64> @llvm.[[SCLAMP]].v3i64
 int64_t3 test_clamp_long3(int64_t3 p0, int64_t3 p1) { return clamp(p0, p1,p1); 
}
-// CHECK-LABEL: define noundef <4 x i64> @_Z16test_clamp_long4
-// CHECK: call <4 x i64> @llvm.dx.clamp.v4i64
+// CHECK: define [[FNATTR]] <4 x i64> @_Z16test_clamp_long4
+// CHECK: call <4 x i64> @llvm.[[SCLAMP]].v4i64
 int64_t4 test_clamp_long4(int64_t4 p0, int64_t4 p1) { return clamp(p0, p1,p1); 
}
 
-// CHECK-LABEL: define noundef i64 @_Z16test_clamp_ulong
-// CHECK: call i64 @llvm.dx.uclamp.i64(
+// CHECK: define [[FNATTR]] i64 @_Z16test_clamp_ulong
+// CHECK: call i64 @llvm.[[UCLAMP]].i64(
 uint64_t test_clamp_ulong(uint64_t p0, uint64_t p1) { return clamp(p0, p1,p1); 
}
-// CHECK-LABEL: define noundef <2 x i64> @_Z17test_clamp_ulong2
-// CHECK: call <2 x i64> @llvm.dx.uclamp.v2i64
+// CHECK: define [[FNATTR]] <2 x i64> @_Z17test_clamp_ulong2
+// CHECK: call <2 x i64> @llvm.[[UCLAMP]].v2i64
 uint64_t2 test_clamp_ulong2(uint64_t2 p0, uint64_t2 p1) { return clamp(p0, 
p1,p1); }
-// CHECK-LABEL: define noundef <3 x i64> @_Z17test_clamp_ulong3
-// CHECK: call <3 x i64> @llvm.dx.uclamp.v3i64
+// CHECK: define [[FNATTR]] <3 x i64> @_Z17test_clamp_ulong3
+// CHECK: call <3 x i64> @llvm.[[UCLAMP]].v3i64
 uint64_t3 test_clamp_ulong3(uint64_t3 p0, uint64_t3 p1) { return clamp(p0, 
p1,p1); }
-// CHECK-LABEL: define noundef <4 x i64> @_Z17test_clamp_ulong4
-// CHECK: call <4 x i64> @llvm.dx.uclamp.v4i64
+// CHECK: define [[FNATTR]] <4 x i64> @_Z17test_clamp_ulong4
+// CHECK: call <4 x i64> @llvm.[[UCLAMP]].v4i64
 uint64_t4 test_clamp_ulong4(uint64_t4 p0, uint64_t4 p1) { return clamp(p0, 
p1,p1); }
 
-// NATIVE_HALF-LABEL: define noundef half @_Z15test_clamp_half
-// NATIVE_HALF: call half @llvm.dx.clamp.f16(
-// NO_HALF-LABEL: define noundef float @_Z15test_clamp_half
-// NO_HALF: call float @llvm.dx.clamp.f32(
+// NATIVE_HALF: define [[FNATTR]] half @_Z15test_clamp_half
+// NATIVE_HALF: call half @llvm.[[FCLAMP]].f16(
+// NO_HALF: define [[FNATTR]] float @_Z15test_clamp_half
+// NO_HALF: call float @llvm.[[FCLAMP]].f32(
 half test_clamp_half(half p0, half p1) { return clamp(p0, p1,p1); }
-// NATIVE_HALF-LABEL: define noundef <2 x half> @_Z16test_clamp_half2
-// NATIVE_HALF: call <2 x half> @llvm.dx.clamp.v2f16
-// NO_HALF-LABEL: define noundef <2 x float> @_Z16test_clamp_half2
-// NO_HALF: call <2 x float> @llvm.dx.clamp.v2f32(
+// NATIVE_HALF: define [[FNATTR]] <2 x half> @_Z16test_clamp_half2
+// NATIVE_HALF: call <2 x half> @llvm.[[FCLAMP]].v2f16
+// NO_HALF: define [[FNATTR]] <2 x float> @_Z16test_clamp_half2
+// NO_HALF: call <2 x float> @llvm.[[FCLAMP]].v2f32(
 half2 test_clamp_half2(half2 p0, half2 p1) { return clamp(p0, p1,p1); }
-// NATIVE_HALF-LABEL: define noundef <3 x half> @_Z16test_clamp_half3
-// NATIVE_HALF: call <3 x half> @llvm.dx.clamp.v3f16
-// NO_HALF-LABEL: define noundef <3 x float> @_Z16test_clamp_half3
-// NO_HALF: call <3 x float> @llvm.dx.clamp.v3f32(
+// NATIVE_HALF: define [[FNATTR]] <3 x half> @_Z16test_clamp_half3
+// NATIVE_HALF: call <3 x half> @llvm.[[FCLAMP]].v3f16
+// NO_HALF: define [[FNATTR]] <3 x float> @_Z16test_clamp_half3
+// NO_HALF: call <3 x float> @llvm.[[FCLAMP]].v3f32(
 half3 test_clamp_half3(half3 p0, half3 p1) { return clamp(p0, p1,p1); }
-// NATIVE_HALF-LABEL: define noundef <4 x half> @_Z16test_clamp_half4
-// NATIVE_HALF: call <4 x half> @llvm.dx.clamp.v4f16
-// NO_HALF-LABEL: define noundef <4 x float> @_Z16test_clamp_half4
-// NO_HALF: call <4 x float> @llvm.dx.clamp.v4f32(
+// NATIVE_HALF: define [[FNATTR]] <4 x half> @_Z16test_clamp_half4
+// NATIVE_HALF: call <4 x half> @llvm.[[FCLAMP]].v4f16
+// NO_HALF: define [[FNATTR]] <4 x float> @_Z16test_clamp_half4
+// NO_HALF: call <4 x float> @llvm.[[FCLAMP]].v4f32(
 half4 test_clamp_half4(half4 p0, half4 p1) { return clamp(p0, p1,p1); }
 
-// CHECK-LABEL: define noundef float @_Z16test_clamp_float
-// CHECK: call float @llvm.dx.clamp.f32(
+// CHECK: define [[FNATTR]] float @_Z16test_clamp_float
+// CHECK: call float @llvm.[[FCLAMP]].f32(
 float test_clamp_float(float p0, float p1) { return clamp(p0, p1,p1); }
-// CHECK-LABEL: define noundef <2 x float> @_Z17test_clamp_float2
-// CHECK: call <2 x float> @llvm.dx.clamp.v2f32
+// CHECK: define [[FNATTR]] <2 x float> @_Z17test_clamp_float2
+// CHECK: call <2 x float> @llvm.[[FCLAMP]].v2f32
 float2 test_clamp_float2(float2 p0, float2 p1) { return clamp(p0, p1,p1); }
-// CHECK-LABEL: define noundef <3 x float> @_Z17test_clamp_float3
-// CHECK: call <3 x float> @llvm.dx.clamp.v3f32
+// CHECK: define [[FNATTR]] <3 x float> @_Z17test_clamp_float3
+// CHECK: call <3 x float> @llvm.[[FCLAMP]].v3f32
 float3 test_clamp_float3(float3 p0, float3 p1) { return clamp(p0, p1,p1); }
-// CHECK-LABEL: define noundef <4 x float> @_Z17test_clamp_float4
-// CHECK: call <4 x float> @llvm.dx.clamp.v4f32
+// CHECK: define [[FNATTR]] <4 x float> @_Z17test_clamp_float4
+// CHECK: call <4 x float> @llvm.[[FCLAMP]].v4f32
 float4 test_clamp_float4(float4 p0, float4 p1) { return clamp(p0, p1,p1); }
 
-// CHECK-LABEL: define noundef double @_Z17test_clamp_double
-// CHECK: call double @llvm.dx.clamp.f64(
+// CHECK: define [[FNATTR]] double @_Z17test_clamp_double
+// CHECK: call double @llvm.[[FCLAMP]].f64(
 double test_clamp_double(double p0, double p1) { return clamp(p0, p1,p1); }
-// CHECK-LABEL: define noundef <2 x double> @_Z18test_clamp_double2
-// CHECK: call <2 x double> @llvm.dx.clamp.v2f64
+// CHECK: define [[FNATTR]] <2 x double> @_Z18test_clamp_double2
+// CHECK: call <2 x double> @llvm.[[FCLAMP]].v2f64
 double2 test_clamp_double2(double2 p0, double2 p1) { return clamp(p0, p1,p1); }
-// CHECK-LABEL: define noundef <3 x double> @_Z18test_clamp_double3
-// CHECK: call <3 x double> @llvm.dx.clamp.v3f64
+// CHECK: define [[FNATTR]] <3 x double> @_Z18test_clamp_double3
+// CHECK: call <3 x double> @llvm.[[FCLAMP]].v3f64
 double3 test_clamp_double3(double3 p0, double3 p1) { return clamp(p0, p1,p1); }
-// CHECK-LABEL: define noundef <4 x double> @_Z18test_clamp_double4
-// CHECK: call <4 x double> @llvm.dx.clamp.v4f64
+// CHECK: define [[FNATTR]] <4 x double> @_Z18test_clamp_double4
+// CHECK: call <4 x double> @llvm.[[FCLAMP]].v4f64
 double4 test_clamp_double4(double4 p0, double4 p1) { return clamp(p0, p1,p1); }
diff --git a/llvm/include/llvm/IR/IntrinsicsSPIRV.td 
b/llvm/include/llvm/IR/IntrinsicsSPIRV.td
index 6df2eb156a0774..b19d2a299a6eeb 100644
--- a/llvm/include/llvm/IR/IntrinsicsSPIRV.td
+++ b/llvm/include/llvm/IR/IntrinsicsSPIRV.td
@@ -87,6 +87,9 @@ let TargetPrefix = "spv" in {
   def int_spv_wave_readlane : DefaultAttrsIntrinsic<[llvm_any_ty], 
[LLVMMatchType<0>, llvm_i32_ty], [IntrConvergent, IntrNoMem]>;
   def int_spv_sign : DefaultAttrsIntrinsic<[LLVMScalarOrSameVectorWidth<0, 
llvm_i32_ty>], [llvm_any_ty], [IntrNoMem]>;
   def int_spv_radians : DefaultAttrsIntrinsic<[LLVMMatchType<0>], 
[llvm_anyfloat_ty], [IntrNoMem]>;
+  def int_spv_uclamp : DefaultAttrsIntrinsic<[llvm_any_ty], [LLVMMatchType<0>, 
LLVMMatchType<0>, LLVMMatchType<0>], [IntrNoMem]>;
+  def int_spv_sclamp : DefaultAttrsIntrinsic<[llvm_any_ty], [LLVMMatchType<0>, 
LLVMMatchType<0>, LLVMMatchType<0>], [IntrNoMem]>;
+  def int_spv_fclamp : DefaultAttrsIntrinsic<[llvm_anyfloat_ty], 
[LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>], [IntrNoMem]>;
 
   // Create resource handle given the binding information. Returns a 
   // type appropriate for the kind of resource given the set id, binding id,
diff --git a/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp 
b/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
index d9377fe4b91a1a..ca668941d0231d 100644
--- a/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
@@ -2559,6 +2559,12 @@ bool SPIRVInstructionSelector::selectIntrinsic(Register 
ResVReg,
   } break;
   case Intrinsic::spv_saturate:
     return selectSaturate(ResVReg, ResType, I);
+  case Intrinsic::spv_fclamp:
+    return selectExtInst(ResVReg, ResType, I, CL::fclamp, GL::FClamp);
+  case Intrinsic::spv_uclamp:
+    return selectExtInst(ResVReg, ResType, I, CL::u_clamp, GL::UClamp);
+  case Intrinsic::spv_sclamp:
+    return selectExtInst(ResVReg, ResType, I, CL::s_clamp, GL::SClamp);
   case Intrinsic::spv_wave_is_first_lane: {
     SPIRVType *IntTy = GR.getOrCreateSPIRVIntegerType(32, I, TII);
     return BuildMI(BB, I, I.getDebugLoc(),

>From 15897bacfdb71d277e1a74cc12cb3a5d80d6f949 Mon Sep 17 00:00:00 2001
From: Adam Yang <31109344+adam-y...@users.noreply.github.com>
Date: Tue, 22 Oct 2024 15:57:52 -0700
Subject: [PATCH 2/6] LLC tests

---
 .../SPIRV/hlsl-intrinsics/clamp-vec.ll        | 130 ++++++++++++++++++
 .../CodeGen/SPIRV/hlsl-intrinsics/clamp.ll    | 122 ++++++++++++++++
 2 files changed, 252 insertions(+)
 create mode 100644 llvm/test/CodeGen/SPIRV/hlsl-intrinsics/clamp-vec.ll
 create mode 100644 llvm/test/CodeGen/SPIRV/hlsl-intrinsics/clamp.ll

diff --git a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/clamp-vec.ll 
b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/clamp-vec.ll
new file mode 100644
index 00000000000000..6af5bf2fc1812b
--- /dev/null
+++ b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/clamp-vec.ll
@@ -0,0 +1,130 @@
+; RUN: llc  -verify-machineinstrs -O0 -mtriple=spirv-unknown-unknown %s -o - | 
FileCheck %s
+; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o - 
-filetype=obj | spirv-val %}
+
+; CHECK-DAG: %[[#op_ext_glsl:]] = OpExtInstImport "GLSL.std.450"
+
+; CHECK-DAG: %[[#float_64:]] = OpTypeFloat 64
+; CHECK-DAG: %[[#float_32:]] = OpTypeFloat 32
+; CHECK-DAG: %[[#float_16:]] = OpTypeFloat 16
+
+; CHECK-DAG: %[[#int_64:]] = OpTypeInt 64
+; CHECK-DAG: %[[#int_32:]] = OpTypeInt 32
+; CHECK-DAG: %[[#int_16:]] = OpTypeInt 16
+
+; CHECK-DAG: %[[#vec4_float_64:]] = OpTypeVector %[[#float_64]] 4
+; CHECK-DAG: %[[#vec4_float_32:]] = OpTypeVector %[[#float_32]] 4
+; CHECK-DAG: %[[#vec4_float_16:]] = OpTypeVector %[[#float_16]] 4
+
+; CHECK-DAG: %[[#vec4_int_64:]] = OpTypeVector %[[#int_64]] 4
+; CHECK-DAG: %[[#vec4_int_32:]] = OpTypeVector %[[#int_32]] 4
+; CHECK-DAG: %[[#vec4_int_16:]] = OpTypeVector %[[#int_16]] 4
+
+; CHECK-LABEL: Begin function test_sclamp_v4i16
+define noundef <4 x i16> @test_sclamp_v4i16(<4 x i16> noundef %a, <4 x i16> 
noundef %b, <4 x i16> noundef %c) {
+entry:
+  ; CHECK: %[[#vec4_i16_arg0:]] = OpFunctionParameter %[[#vec4_int_16]]
+  ; CHECK: %[[#vec4_i16_arg1:]] = OpFunctionParameter %[[#vec4_int_16]]
+  ; CHECK: %[[#vec4_i16_arg2:]] = OpFunctionParameter %[[#vec4_int_16]]
+  ; CHECK: %[[#]] = OpExtInst %[[#vec4_int_16]] %[[#op_ext_glsl]] SClamp 
%[[#vec4_i16_arg0]] %[[#vec4_i16_arg1]] %[[#vec4_i16_arg2]]
+  %0 = call <4 x i16> @llvm.spv.sclamp.v4i16(<4 x i16> %a, <4 x i16> %b, <4 x 
i16> %c)
+  ret <4 x i16> %0
+}
+
+; CHECK-LABEL: Begin function test_sclamp_v4i32
+define noundef <4 x i32> @test_sclamp_v4i32(<4 x i32> noundef %a, <4 x i32> 
noundef %b, <4 x i32> noundef %c) {
+entry:
+  ; CHECK: %[[#vec4_i32_arg0:]] = OpFunctionParameter %[[#vec4_int_32]]
+  ; CHECK: %[[#vec4_i32_arg1:]] = OpFunctionParameter %[[#vec4_int_32]]
+  ; CHECK: %[[#vec4_i32_arg2:]] = OpFunctionParameter %[[#vec4_int_32]]
+  ; CHECK: %[[#]] = OpExtInst %[[#vec4_int_32]] %[[#op_ext_glsl]] SClamp 
%[[#vec4_i32_arg0]] %[[#vec4_i32_arg1]] %[[#vec4_i32_arg2]]
+  %0 = call <4 x i32> @llvm.spv.sclamp.v4i32(<4 x i32> %a, <4 x i32> %b, <4 x 
i32> %c)
+  ret <4 x i32> %0
+}
+
+; CHECK-LABEL: Begin function test_sclamp_v4i64
+define noundef <4 x i64> @test_sclamp_v4i64(<4 x i64> noundef %a, <4 x i64> 
noundef %b, <4 x i64> noundef %c) {
+entry:
+  ; CHECK: %[[#vec4_i64_arg0:]] = OpFunctionParameter %[[#vec4_int_64]]
+  ; CHECK: %[[#vec4_i64_arg1:]] = OpFunctionParameter %[[#vec4_int_64]]
+  ; CHECK: %[[#vec4_i64_arg2:]] = OpFunctionParameter %[[#vec4_int_64]]
+  ; CHECK: %[[#]] = OpExtInst %[[#vec4_int_64]] %[[#op_ext_glsl]] SClamp 
%[[#vec4_i64_arg0]] %[[#vec4_i64_arg1]] %[[#vec4_i64_arg2]]
+  %0 = call <4 x i64> @llvm.spv.sclamp.v4i64(<4 x i64> %a, <4 x i64> %b, <4 x 
i64> %c)
+  ret <4 x i64> %0
+}
+
+; CHECK-LABEL: Begin function test_fclamp_v4half
+define noundef <4 x half> @test_fclamp_v4half(<4 x half> noundef %a, <4 x 
half> noundef %b, <4 x half> noundef %c) {
+entry:
+  ; CHECK: %[[#vec4_f16_arg0:]] = OpFunctionParameter %[[#vec4_float_16]]
+  ; CHECK: %[[#vec4_f16_arg1:]] = OpFunctionParameter %[[#vec4_float_16]]
+  ; CHECK: %[[#vec4_f16_arg2:]] = OpFunctionParameter %[[#vec4_float_16]]
+  ; CHECK: %[[#]] = OpExtInst %[[#vec4_float_16]] %[[#op_ext_glsl]] FClamp 
%[[#vec4_f16_arg0]] %[[#vec4_f16_arg1]] %[[#vec4_f16_arg2]]
+  %0 = call <4 x half> @llvm.spv.fclamp.v4f16(<4 x half> %a, <4 x half> %b, <4 
x half> %c)
+  ret <4 x half> %0
+}
+
+; CHECK-LABEL: Begin function test_fclamp_v4float
+define noundef <4 x float> @test_fclamp_v4float(<4 x float> noundef %a, <4 x 
float> noundef %b, <4 x float> noundef %c) {
+entry:
+  ; CHECK: %[[#vec4_f32_arg0:]] = OpFunctionParameter %[[#vec4_float_32]]
+  ; CHECK: %[[#vec4_f32_arg1:]] = OpFunctionParameter %[[#vec4_float_32]]
+  ; CHECK: %[[#vec4_f32_arg2:]] = OpFunctionParameter %[[#vec4_float_32]]
+  ; CHECK: %[[#]] = OpExtInst %[[#vec4_float_32]] %[[#op_ext_glsl]] FClamp 
%[[#vec4_f32_arg0]] %[[#vec4_f32_arg1]] %[[#vec4_f32_arg2]]
+  %0 = call <4 x float> @llvm.spv.fclamp.v4f32(<4 x float> %a, <4 x float> %b, 
<4 x float> %c)
+  ret <4 x float> %0
+}
+
+; CHECK-LABEL: Begin function test_fclamp_v4double
+define noundef <4 x double> @test_fclamp_v4double(<4 x double> noundef %a, <4 
x double> noundef %b, <4 x double> noundef %c) {
+entry:
+  ; CHECK: %[[#vec4_f64_arg0:]] = OpFunctionParameter %[[#vec4_float_64]]
+  ; CHECK: %[[#vec4_f64_arg1:]] = OpFunctionParameter %[[#vec4_float_64]]
+  ; CHECK: %[[#vec4_f64_arg2:]] = OpFunctionParameter %[[#vec4_float_64]]
+  ; CHECK: %[[#]] = OpExtInst %[[#vec4_float_64]] %[[#op_ext_glsl]] FClamp 
%[[#vec4_f64_arg0]] %[[#vec4_f64_arg1]] %[[#vec4_f64_arg2]]
+  %0 = call <4 x double> @llvm.spv.fclamp.v4f64(<4 x double> %a, <4 x double> 
%b, <4 x double> %c)
+  ret <4 x double> %0
+}
+
+; CHECK-LABEL: Begin function test_uclamp_v4i16
+define noundef <4 x i16> @test_uclamp_v4i16(<4 x i16> noundef %a, <4 x i16> 
noundef %b, <4 x i16> noundef %c) {
+entry:
+  ; CHECK: %[[#vec4_i16_arg0:]] = OpFunctionParameter %[[#vec4_int_16]]
+  ; CHECK: %[[#vec4_i16_arg1:]] = OpFunctionParameter %[[#vec4_int_16]]
+  ; CHECK: %[[#vec4_i16_arg2:]] = OpFunctionParameter %[[#vec4_int_16]]
+  ; CHECK: %[[#]] = OpExtInst %[[#vec4_int_16]] %[[#op_ext_glsl]] UClamp 
%[[#vec4_i16_arg0]] %[[#vec4_i16_arg1]] %[[#vec4_i16_arg2]]
+  %0 = call <4 x i16> @llvm.spv.uclamp.v4i16(<4 x i16> %a, <4 x i16> %b, <4 x 
i16> %c)
+  ret <4 x i16> %0
+}
+
+; CHECK-LABEL: Begin function test_uclamp_v4i32
+define noundef <4 x i32> @test_uclamp_v4i32(<4 x i32> noundef %a, <4 x i32> 
noundef %b, <4 x i32> noundef %c) {
+entry:
+  ; CHECK: %[[#vec4_i32_arg0:]] = OpFunctionParameter %[[#vec4_int_32]]
+  ; CHECK: %[[#vec4_i32_arg1:]] = OpFunctionParameter %[[#vec4_int_32]]
+  ; CHECK: %[[#vec4_i32_arg2:]] = OpFunctionParameter %[[#vec4_int_32]]
+  ; CHECK: %[[#]] = OpExtInst %[[#vec4_int_32]] %[[#op_ext_glsl]] UClamp 
%[[#vec4_i32_arg0]] %[[#vec4_i32_arg1]] %[[#vec4_i32_arg2]]
+  %0 = call <4 x i32> @llvm.spv.uclamp.v4i32(<4 x i32> %a, <4 x i32> %b, <4 x 
i32> %c)
+  ret <4 x i32> %0
+}
+
+; CHECK-LABEL: Begin function test_uclamp_v4i64
+define noundef <4 x i64> @test_uclamp_v4i64(<4 x i64> noundef %a, <4 x i64> 
noundef %b, <4 x i64> noundef %c) {
+entry:
+  ; CHECK: %[[#vec4_i64_arg0:]] = OpFunctionParameter %[[#vec4_int_64]]
+  ; CHECK: %[[#vec4_i64_arg1:]] = OpFunctionParameter %[[#vec4_int_64]]
+  ; CHECK: %[[#vec4_i64_arg2:]] = OpFunctionParameter %[[#vec4_int_64]]
+  ; CHECK: %[[#]] = OpExtInst %[[#vec4_int_64]] %[[#op_ext_glsl]] UClamp 
%[[#vec4_i64_arg0]] %[[#vec4_i64_arg1]] %[[#vec4_i64_arg2]]
+  %0 = call <4 x i64> @llvm.spv.uclamp.v4i64(<4 x i64> %a, <4 x i64> %b, <4 x 
i64> %c)
+  ret <4 x i64> %0
+}
+
+declare <4 x half> @llvm.spv.fclamp.v4f16(<4 x half>, <4 x half>, <4 x half>)
+declare <4 x float> @llvm.spv.fclamp.v4f32(<4 x float>, <4 x float>, <4 x 
float>)
+declare <4 x double> @llvm.spv.fclamp.v4f64(<4 x double>, <4 x double>, <4 x 
double>)
+declare <4 x i16> @llvm.spv.sclamp.v4i16(<4 x i16>, <4 x i16>, <4 x i16>)
+declare <4 x i32> @llvm.spv.sclamp.v4i32(<4 x i32>, <4 x i32>, <4 x i32>)
+declare <4 x i64> @llvm.spv.sclamp.v4i64(<4 x i64>, <4 x i64>, <4 x i64>)
+declare <4 x i16> @llvm.spv.uclamp.v4i16(<4 x i16>, <4 x i16>, <4 x i16>)
+declare <4 x i32> @llvm.spv.uclamp.v4i32(<4 x i32>, <4 x i32>, <4 x i32>)
+declare <4 x i64> @llvm.spv.uclamp.v4i64(<4 x i64>, <4 x i64>, <4 x i64>)
+
diff --git a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/clamp.ll 
b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/clamp.ll
new file mode 100644
index 00000000000000..cdc58f7b742505
--- /dev/null
+++ b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/clamp.ll
@@ -0,0 +1,122 @@
+; RUN: llc  -verify-machineinstrs -O0 -mtriple=spirv-unknown-unknown %s -o - | 
FileCheck %s
+; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o - 
-filetype=obj | spirv-val %}
+
+; CHECK-DAG: %[[#op_ext_glsl:]] = OpExtInstImport "GLSL.std.450"
+
+; CHECK-DAG: %[[#float_64:]] = OpTypeFloat 64
+; CHECK-DAG: %[[#float_32:]] = OpTypeFloat 32
+; CHECK-DAG: %[[#float_16:]] = OpTypeFloat 16
+
+; CHECK-DAG: %[[#int_64:]] = OpTypeInt 64
+; CHECK-DAG: %[[#int_32:]] = OpTypeInt 32
+; CHECK-DAG: %[[#int_16:]] = OpTypeInt 16
+
+; CHECK-LABEL: Begin function test_sclamp_i16
+define noundef i16 @test_sclamp_i16(i16 noundef %a, i16 noundef %b, i16 
noundef %c) {
+entry:
+  ; CHECK: %[[#i16_arg0:]] = OpFunctionParameter %[[#int_16]]
+  ; CHECK: %[[#i16_arg1:]] = OpFunctionParameter %[[#int_16]]
+  ; CHECK: %[[#i16_arg2:]] = OpFunctionParameter %[[#int_16]]
+  ; CHECK: %[[#]] = OpExtInst %[[#int_16]] %[[#op_ext_glsl]] SClamp 
%[[#i16_arg0]] %[[#i16_arg1]] %[[#i16_arg2]]
+  %0 = call i16 @llvm.spv.sclamp.i16(i16 %a, i16 %b, i16 %c)
+  ret i16 %0
+}
+
+; CHECK-LABEL: Begin function test_sclamp_i32
+define noundef i32 @test_sclamp_i32(i32 noundef %a, i32 noundef %b, i32 
noundef %c) {
+entry:
+  ; CHECK: %[[#i32_arg0:]] = OpFunctionParameter %[[#int_32]]
+  ; CHECK: %[[#i32_arg1:]] = OpFunctionParameter %[[#int_32]]
+  ; CHECK: %[[#i32_arg2:]] = OpFunctionParameter %[[#int_32]]
+  ; CHECK: %[[#]] = OpExtInst %[[#int_32]] %[[#op_ext_glsl]] SClamp 
%[[#i32_arg0]] %[[#i32_arg1]] %[[#i32_arg2]]
+  %0 = call i32 @llvm.spv.sclamp.i32(i32 %a, i32 %b, i32 %c)
+  ret i32 %0
+}
+
+; CHECK-LABEL: Begin function test_sclamp_i64
+define noundef i64 @test_sclamp_i64(i64 noundef %a, i64 noundef %b, i64 
noundef %c) {
+entry:
+  ; CHECK: %[[#i64_arg0:]] = OpFunctionParameter %[[#int_64]]
+  ; CHECK: %[[#i64_arg1:]] = OpFunctionParameter %[[#int_64]]
+  ; CHECK: %[[#i64_arg2:]] = OpFunctionParameter %[[#int_64]]
+  ; CHECK: %[[#]] = OpExtInst %[[#int_64]] %[[#op_ext_glsl]] SClamp 
%[[#i64_arg0]] %[[#i64_arg1]] %[[#i64_arg2]]
+  %0 = call i64 @llvm.spv.sclamp.i64(i64 %a, i64 %b, i64 %c)
+  ret i64 %0
+}
+
+; CHECK-LABEL: Begin function test_fclamp_half
+define noundef half @test_fclamp_half(half noundef %a, half noundef %b, half 
noundef %c) {
+entry:
+  ; CHECK: %[[#f16_arg0:]] = OpFunctionParameter %[[#float_16]]
+  ; CHECK: %[[#f16_arg1:]] = OpFunctionParameter %[[#float_16]]
+  ; CHECK: %[[#f16_arg2:]] = OpFunctionParameter %[[#float_16]]
+  ; CHECK: %[[#]] = OpExtInst %[[#float_16]] %[[#op_ext_glsl]] FClamp 
%[[#f16_arg0]] %[[#f16_arg1]] %[[#f16_arg2]]
+  %0 = call half @llvm.spv.fclamp.f16(half %a, half %b, half %c)
+  ret half %0
+}
+
+; CHECK-LABEL: Begin function test_fclamp_float
+define noundef float @test_fclamp_float(float noundef %a, float noundef %b, 
float noundef %c) {
+entry:
+  ; CHECK: %[[#f32_arg0:]] = OpFunctionParameter %[[#float_32]]
+  ; CHECK: %[[#f32_arg1:]] = OpFunctionParameter %[[#float_32]]
+  ; CHECK: %[[#f32_arg2:]] = OpFunctionParameter %[[#float_32]]
+  ; CHECK: %[[#]] = OpExtInst %[[#float_32]] %[[#op_ext_glsl]] FClamp 
%[[#f32_arg0]] %[[#f32_arg1]] %[[#f32_arg2]]
+  %0 = call float @llvm.spv.fclamp.f32(float %a, float %b, float %c)
+  ret float %0
+}
+
+; CHECK-LABEL: Begin function test_fclamp_double
+define noundef double @test_fclamp_double(double noundef %a, double noundef 
%b, double noundef %c) {
+entry:
+  ; CHECK: %[[#f64_arg0:]] = OpFunctionParameter %[[#float_64]]
+  ; CHECK: %[[#f64_arg1:]] = OpFunctionParameter %[[#float_64]]
+  ; CHECK: %[[#f64_arg2:]] = OpFunctionParameter %[[#float_64]]
+  ; CHECK: %[[#]] = OpExtInst %[[#float_64]] %[[#op_ext_glsl]] FClamp 
%[[#f64_arg0]] %[[#f64_arg1]] %[[#f64_arg2]]
+  %0 = call double @llvm.spv.fclamp.f64(double %a, double %b, double %c)
+  ret double %0
+}
+
+; CHECK-LABEL: Begin function test_uclamp_i16
+define noundef i16 @test_uclamp_i16(i16 noundef %a, i16 noundef %b, i16 
noundef %c) {
+entry:
+  ; CHECK: %[[#i16_arg0:]] = OpFunctionParameter %[[#int_16]]
+  ; CHECK: %[[#i16_arg1:]] = OpFunctionParameter %[[#int_16]]
+  ; CHECK: %[[#i16_arg2:]] = OpFunctionParameter %[[#int_16]]
+  ; CHECK: %[[#]] = OpExtInst %[[#int_16]] %[[#op_ext_glsl]] UClamp 
%[[#i16_arg0]] %[[#i16_arg1]] %[[#i16_arg2]]
+  %0 = call i16 @llvm.spv.uclamp.i16(i16 %a, i16 %b, i16 %c)
+  ret i16 %0
+}
+
+; CHECK-LABEL: Begin function test_uclamp_i32
+define noundef i32 @test_uclamp_i32(i32 noundef %a, i32 noundef %b, i32 
noundef %c) {
+entry:
+  ; CHECK: %[[#i32_arg0:]] = OpFunctionParameter %[[#int_32]]
+  ; CHECK: %[[#i32_arg1:]] = OpFunctionParameter %[[#int_32]]
+  ; CHECK: %[[#i32_arg2:]] = OpFunctionParameter %[[#int_32]]
+  ; CHECK: %[[#]] = OpExtInst %[[#int_32]] %[[#op_ext_glsl]] UClamp 
%[[#i32_arg0]] %[[#i32_arg1]] %[[#i32_arg2]]
+  %0 = call i32 @llvm.spv.uclamp.i32(i32 %a, i32 %b, i32 %c)
+  ret i32 %0
+}
+
+; CHECK-LABEL: Begin function test_uclamp_i64
+define noundef i64 @test_uclamp_i64(i64 noundef %a, i64 noundef %b, i64 
noundef %c) {
+entry:
+  ; CHECK: %[[#i64_arg0:]] = OpFunctionParameter %[[#int_64]]
+  ; CHECK: %[[#i64_arg1:]] = OpFunctionParameter %[[#int_64]]
+  ; CHECK: %[[#i64_arg2:]] = OpFunctionParameter %[[#int_64]]
+  ; CHECK: %[[#]] = OpExtInst %[[#int_64]] %[[#op_ext_glsl]] UClamp 
%[[#i64_arg0]] %[[#i64_arg1]] %[[#i64_arg2]]
+  %0 = call i64 @llvm.spv.uclamp.i64(i64 %a, i64 %b, i64 %c)
+  ret i64 %0
+}
+
+declare half @llvm.spv.fclamp.f16(half, half, half)
+declare float @llvm.spv.fclamp.f32(float, float, float)
+declare double @llvm.spv.fclamp.f64(double, double, double)
+declare i16 @llvm.spv.sclamp.i16(i16, i16, i16)
+declare i32 @llvm.spv.sclamp.i32(i32, i32, i32)
+declare i64 @llvm.spv.sclamp.i64(i64, i64, i64)
+declare i16 @llvm.spv.uclamp.i16(i16, i16, i16)
+declare i32 @llvm.spv.uclamp.i32(i32, i32, i32)
+declare i64 @llvm.spv.uclamp.i64(i64, i64, i64)
+

>From b669cfb5e90a34146cd5a3a8d8d9cb612e3e0fbf Mon Sep 17 00:00:00 2001
From: Adam Yang <31109344+adam-y...@users.noreply.github.com>
Date: Tue, 22 Oct 2024 16:02:27 -0700
Subject: [PATCH 3/6] Testing opencl too

---
 .../SPIRV/hlsl-intrinsics/clamp-vec.ll        |  20 +--
 .../CodeGen/SPIRV/hlsl-intrinsics/clamp.ll    |  20 +--
 llvm/test/CodeGen/SPIRV/opencl/clamp-vec.ll   | 132 ++++++++++++++++++
 llvm/test/CodeGen/SPIRV/opencl/clamp.ll       | 124 ++++++++++++++++
 4 files changed, 276 insertions(+), 20 deletions(-)
 create mode 100644 llvm/test/CodeGen/SPIRV/opencl/clamp-vec.ll
 create mode 100644 llvm/test/CodeGen/SPIRV/opencl/clamp.ll

diff --git a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/clamp-vec.ll 
b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/clamp-vec.ll
index 6af5bf2fc1812b..cd0111c399abf7 100644
--- a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/clamp-vec.ll
+++ b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/clamp-vec.ll
@@ -1,7 +1,7 @@
 ; RUN: llc  -verify-machineinstrs -O0 -mtriple=spirv-unknown-unknown %s -o - | 
FileCheck %s
 ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o - 
-filetype=obj | spirv-val %}
 
-; CHECK-DAG: %[[#op_ext_glsl:]] = OpExtInstImport "GLSL.std.450"
+; CHECK-DAG: %[[#op_ext:]] = OpExtInstImport "GLSL.std.450"
 
 ; CHECK-DAG: %[[#float_64:]] = OpTypeFloat 64
 ; CHECK-DAG: %[[#float_32:]] = OpTypeFloat 32
@@ -25,7 +25,7 @@ entry:
   ; CHECK: %[[#vec4_i16_arg0:]] = OpFunctionParameter %[[#vec4_int_16]]
   ; CHECK: %[[#vec4_i16_arg1:]] = OpFunctionParameter %[[#vec4_int_16]]
   ; CHECK: %[[#vec4_i16_arg2:]] = OpFunctionParameter %[[#vec4_int_16]]
-  ; CHECK: %[[#]] = OpExtInst %[[#vec4_int_16]] %[[#op_ext_glsl]] SClamp 
%[[#vec4_i16_arg0]] %[[#vec4_i16_arg1]] %[[#vec4_i16_arg2]]
+  ; CHECK: %[[#]] = OpExtInst %[[#vec4_int_16]] %[[#op_ext]] SClamp 
%[[#vec4_i16_arg0]] %[[#vec4_i16_arg1]] %[[#vec4_i16_arg2]]
   %0 = call <4 x i16> @llvm.spv.sclamp.v4i16(<4 x i16> %a, <4 x i16> %b, <4 x 
i16> %c)
   ret <4 x i16> %0
 }
@@ -36,7 +36,7 @@ entry:
   ; CHECK: %[[#vec4_i32_arg0:]] = OpFunctionParameter %[[#vec4_int_32]]
   ; CHECK: %[[#vec4_i32_arg1:]] = OpFunctionParameter %[[#vec4_int_32]]
   ; CHECK: %[[#vec4_i32_arg2:]] = OpFunctionParameter %[[#vec4_int_32]]
-  ; CHECK: %[[#]] = OpExtInst %[[#vec4_int_32]] %[[#op_ext_glsl]] SClamp 
%[[#vec4_i32_arg0]] %[[#vec4_i32_arg1]] %[[#vec4_i32_arg2]]
+  ; CHECK: %[[#]] = OpExtInst %[[#vec4_int_32]] %[[#op_ext]] SClamp 
%[[#vec4_i32_arg0]] %[[#vec4_i32_arg1]] %[[#vec4_i32_arg2]]
   %0 = call <4 x i32> @llvm.spv.sclamp.v4i32(<4 x i32> %a, <4 x i32> %b, <4 x 
i32> %c)
   ret <4 x i32> %0
 }
@@ -47,7 +47,7 @@ entry:
   ; CHECK: %[[#vec4_i64_arg0:]] = OpFunctionParameter %[[#vec4_int_64]]
   ; CHECK: %[[#vec4_i64_arg1:]] = OpFunctionParameter %[[#vec4_int_64]]
   ; CHECK: %[[#vec4_i64_arg2:]] = OpFunctionParameter %[[#vec4_int_64]]
-  ; CHECK: %[[#]] = OpExtInst %[[#vec4_int_64]] %[[#op_ext_glsl]] SClamp 
%[[#vec4_i64_arg0]] %[[#vec4_i64_arg1]] %[[#vec4_i64_arg2]]
+  ; CHECK: %[[#]] = OpExtInst %[[#vec4_int_64]] %[[#op_ext]] SClamp 
%[[#vec4_i64_arg0]] %[[#vec4_i64_arg1]] %[[#vec4_i64_arg2]]
   %0 = call <4 x i64> @llvm.spv.sclamp.v4i64(<4 x i64> %a, <4 x i64> %b, <4 x 
i64> %c)
   ret <4 x i64> %0
 }
@@ -58,7 +58,7 @@ entry:
   ; CHECK: %[[#vec4_f16_arg0:]] = OpFunctionParameter %[[#vec4_float_16]]
   ; CHECK: %[[#vec4_f16_arg1:]] = OpFunctionParameter %[[#vec4_float_16]]
   ; CHECK: %[[#vec4_f16_arg2:]] = OpFunctionParameter %[[#vec4_float_16]]
-  ; CHECK: %[[#]] = OpExtInst %[[#vec4_float_16]] %[[#op_ext_glsl]] FClamp 
%[[#vec4_f16_arg0]] %[[#vec4_f16_arg1]] %[[#vec4_f16_arg2]]
+  ; CHECK: %[[#]] = OpExtInst %[[#vec4_float_16]] %[[#op_ext]] FClamp 
%[[#vec4_f16_arg0]] %[[#vec4_f16_arg1]] %[[#vec4_f16_arg2]]
   %0 = call <4 x half> @llvm.spv.fclamp.v4f16(<4 x half> %a, <4 x half> %b, <4 
x half> %c)
   ret <4 x half> %0
 }
@@ -69,7 +69,7 @@ entry:
   ; CHECK: %[[#vec4_f32_arg0:]] = OpFunctionParameter %[[#vec4_float_32]]
   ; CHECK: %[[#vec4_f32_arg1:]] = OpFunctionParameter %[[#vec4_float_32]]
   ; CHECK: %[[#vec4_f32_arg2:]] = OpFunctionParameter %[[#vec4_float_32]]
-  ; CHECK: %[[#]] = OpExtInst %[[#vec4_float_32]] %[[#op_ext_glsl]] FClamp 
%[[#vec4_f32_arg0]] %[[#vec4_f32_arg1]] %[[#vec4_f32_arg2]]
+  ; CHECK: %[[#]] = OpExtInst %[[#vec4_float_32]] %[[#op_ext]] FClamp 
%[[#vec4_f32_arg0]] %[[#vec4_f32_arg1]] %[[#vec4_f32_arg2]]
   %0 = call <4 x float> @llvm.spv.fclamp.v4f32(<4 x float> %a, <4 x float> %b, 
<4 x float> %c)
   ret <4 x float> %0
 }
@@ -80,7 +80,7 @@ entry:
   ; CHECK: %[[#vec4_f64_arg0:]] = OpFunctionParameter %[[#vec4_float_64]]
   ; CHECK: %[[#vec4_f64_arg1:]] = OpFunctionParameter %[[#vec4_float_64]]
   ; CHECK: %[[#vec4_f64_arg2:]] = OpFunctionParameter %[[#vec4_float_64]]
-  ; CHECK: %[[#]] = OpExtInst %[[#vec4_float_64]] %[[#op_ext_glsl]] FClamp 
%[[#vec4_f64_arg0]] %[[#vec4_f64_arg1]] %[[#vec4_f64_arg2]]
+  ; CHECK: %[[#]] = OpExtInst %[[#vec4_float_64]] %[[#op_ext]] FClamp 
%[[#vec4_f64_arg0]] %[[#vec4_f64_arg1]] %[[#vec4_f64_arg2]]
   %0 = call <4 x double> @llvm.spv.fclamp.v4f64(<4 x double> %a, <4 x double> 
%b, <4 x double> %c)
   ret <4 x double> %0
 }
@@ -91,7 +91,7 @@ entry:
   ; CHECK: %[[#vec4_i16_arg0:]] = OpFunctionParameter %[[#vec4_int_16]]
   ; CHECK: %[[#vec4_i16_arg1:]] = OpFunctionParameter %[[#vec4_int_16]]
   ; CHECK: %[[#vec4_i16_arg2:]] = OpFunctionParameter %[[#vec4_int_16]]
-  ; CHECK: %[[#]] = OpExtInst %[[#vec4_int_16]] %[[#op_ext_glsl]] UClamp 
%[[#vec4_i16_arg0]] %[[#vec4_i16_arg1]] %[[#vec4_i16_arg2]]
+  ; CHECK: %[[#]] = OpExtInst %[[#vec4_int_16]] %[[#op_ext]] UClamp 
%[[#vec4_i16_arg0]] %[[#vec4_i16_arg1]] %[[#vec4_i16_arg2]]
   %0 = call <4 x i16> @llvm.spv.uclamp.v4i16(<4 x i16> %a, <4 x i16> %b, <4 x 
i16> %c)
   ret <4 x i16> %0
 }
@@ -102,7 +102,7 @@ entry:
   ; CHECK: %[[#vec4_i32_arg0:]] = OpFunctionParameter %[[#vec4_int_32]]
   ; CHECK: %[[#vec4_i32_arg1:]] = OpFunctionParameter %[[#vec4_int_32]]
   ; CHECK: %[[#vec4_i32_arg2:]] = OpFunctionParameter %[[#vec4_int_32]]
-  ; CHECK: %[[#]] = OpExtInst %[[#vec4_int_32]] %[[#op_ext_glsl]] UClamp 
%[[#vec4_i32_arg0]] %[[#vec4_i32_arg1]] %[[#vec4_i32_arg2]]
+  ; CHECK: %[[#]] = OpExtInst %[[#vec4_int_32]] %[[#op_ext]] UClamp 
%[[#vec4_i32_arg0]] %[[#vec4_i32_arg1]] %[[#vec4_i32_arg2]]
   %0 = call <4 x i32> @llvm.spv.uclamp.v4i32(<4 x i32> %a, <4 x i32> %b, <4 x 
i32> %c)
   ret <4 x i32> %0
 }
@@ -113,7 +113,7 @@ entry:
   ; CHECK: %[[#vec4_i64_arg0:]] = OpFunctionParameter %[[#vec4_int_64]]
   ; CHECK: %[[#vec4_i64_arg1:]] = OpFunctionParameter %[[#vec4_int_64]]
   ; CHECK: %[[#vec4_i64_arg2:]] = OpFunctionParameter %[[#vec4_int_64]]
-  ; CHECK: %[[#]] = OpExtInst %[[#vec4_int_64]] %[[#op_ext_glsl]] UClamp 
%[[#vec4_i64_arg0]] %[[#vec4_i64_arg1]] %[[#vec4_i64_arg2]]
+  ; CHECK: %[[#]] = OpExtInst %[[#vec4_int_64]] %[[#op_ext]] UClamp 
%[[#vec4_i64_arg0]] %[[#vec4_i64_arg1]] %[[#vec4_i64_arg2]]
   %0 = call <4 x i64> @llvm.spv.uclamp.v4i64(<4 x i64> %a, <4 x i64> %b, <4 x 
i64> %c)
   ret <4 x i64> %0
 }
diff --git a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/clamp.ll 
b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/clamp.ll
index cdc58f7b742505..61b89e16f2bd48 100644
--- a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/clamp.ll
+++ b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/clamp.ll
@@ -1,7 +1,7 @@
 ; RUN: llc  -verify-machineinstrs -O0 -mtriple=spirv-unknown-unknown %s -o - | 
FileCheck %s
 ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o - 
-filetype=obj | spirv-val %}
 
-; CHECK-DAG: %[[#op_ext_glsl:]] = OpExtInstImport "GLSL.std.450"
+; CHECK-DAG: %[[#op_ext:]] = OpExtInstImport "GLSL.std.450"
 
 ; CHECK-DAG: %[[#float_64:]] = OpTypeFloat 64
 ; CHECK-DAG: %[[#float_32:]] = OpTypeFloat 32
@@ -17,7 +17,7 @@ entry:
   ; CHECK: %[[#i16_arg0:]] = OpFunctionParameter %[[#int_16]]
   ; CHECK: %[[#i16_arg1:]] = OpFunctionParameter %[[#int_16]]
   ; CHECK: %[[#i16_arg2:]] = OpFunctionParameter %[[#int_16]]
-  ; CHECK: %[[#]] = OpExtInst %[[#int_16]] %[[#op_ext_glsl]] SClamp 
%[[#i16_arg0]] %[[#i16_arg1]] %[[#i16_arg2]]
+  ; CHECK: %[[#]] = OpExtInst %[[#int_16]] %[[#op_ext]] SClamp %[[#i16_arg0]] 
%[[#i16_arg1]] %[[#i16_arg2]]
   %0 = call i16 @llvm.spv.sclamp.i16(i16 %a, i16 %b, i16 %c)
   ret i16 %0
 }
@@ -28,7 +28,7 @@ entry:
   ; CHECK: %[[#i32_arg0:]] = OpFunctionParameter %[[#int_32]]
   ; CHECK: %[[#i32_arg1:]] = OpFunctionParameter %[[#int_32]]
   ; CHECK: %[[#i32_arg2:]] = OpFunctionParameter %[[#int_32]]
-  ; CHECK: %[[#]] = OpExtInst %[[#int_32]] %[[#op_ext_glsl]] SClamp 
%[[#i32_arg0]] %[[#i32_arg1]] %[[#i32_arg2]]
+  ; CHECK: %[[#]] = OpExtInst %[[#int_32]] %[[#op_ext]] SClamp %[[#i32_arg0]] 
%[[#i32_arg1]] %[[#i32_arg2]]
   %0 = call i32 @llvm.spv.sclamp.i32(i32 %a, i32 %b, i32 %c)
   ret i32 %0
 }
@@ -39,7 +39,7 @@ entry:
   ; CHECK: %[[#i64_arg0:]] = OpFunctionParameter %[[#int_64]]
   ; CHECK: %[[#i64_arg1:]] = OpFunctionParameter %[[#int_64]]
   ; CHECK: %[[#i64_arg2:]] = OpFunctionParameter %[[#int_64]]
-  ; CHECK: %[[#]] = OpExtInst %[[#int_64]] %[[#op_ext_glsl]] SClamp 
%[[#i64_arg0]] %[[#i64_arg1]] %[[#i64_arg2]]
+  ; CHECK: %[[#]] = OpExtInst %[[#int_64]] %[[#op_ext]] SClamp %[[#i64_arg0]] 
%[[#i64_arg1]] %[[#i64_arg2]]
   %0 = call i64 @llvm.spv.sclamp.i64(i64 %a, i64 %b, i64 %c)
   ret i64 %0
 }
@@ -50,7 +50,7 @@ entry:
   ; CHECK: %[[#f16_arg0:]] = OpFunctionParameter %[[#float_16]]
   ; CHECK: %[[#f16_arg1:]] = OpFunctionParameter %[[#float_16]]
   ; CHECK: %[[#f16_arg2:]] = OpFunctionParameter %[[#float_16]]
-  ; CHECK: %[[#]] = OpExtInst %[[#float_16]] %[[#op_ext_glsl]] FClamp 
%[[#f16_arg0]] %[[#f16_arg1]] %[[#f16_arg2]]
+  ; CHECK: %[[#]] = OpExtInst %[[#float_16]] %[[#op_ext]] FClamp 
%[[#f16_arg0]] %[[#f16_arg1]] %[[#f16_arg2]]
   %0 = call half @llvm.spv.fclamp.f16(half %a, half %b, half %c)
   ret half %0
 }
@@ -61,7 +61,7 @@ entry:
   ; CHECK: %[[#f32_arg0:]] = OpFunctionParameter %[[#float_32]]
   ; CHECK: %[[#f32_arg1:]] = OpFunctionParameter %[[#float_32]]
   ; CHECK: %[[#f32_arg2:]] = OpFunctionParameter %[[#float_32]]
-  ; CHECK: %[[#]] = OpExtInst %[[#float_32]] %[[#op_ext_glsl]] FClamp 
%[[#f32_arg0]] %[[#f32_arg1]] %[[#f32_arg2]]
+  ; CHECK: %[[#]] = OpExtInst %[[#float_32]] %[[#op_ext]] FClamp 
%[[#f32_arg0]] %[[#f32_arg1]] %[[#f32_arg2]]
   %0 = call float @llvm.spv.fclamp.f32(float %a, float %b, float %c)
   ret float %0
 }
@@ -72,7 +72,7 @@ entry:
   ; CHECK: %[[#f64_arg0:]] = OpFunctionParameter %[[#float_64]]
   ; CHECK: %[[#f64_arg1:]] = OpFunctionParameter %[[#float_64]]
   ; CHECK: %[[#f64_arg2:]] = OpFunctionParameter %[[#float_64]]
-  ; CHECK: %[[#]] = OpExtInst %[[#float_64]] %[[#op_ext_glsl]] FClamp 
%[[#f64_arg0]] %[[#f64_arg1]] %[[#f64_arg2]]
+  ; CHECK: %[[#]] = OpExtInst %[[#float_64]] %[[#op_ext]] FClamp 
%[[#f64_arg0]] %[[#f64_arg1]] %[[#f64_arg2]]
   %0 = call double @llvm.spv.fclamp.f64(double %a, double %b, double %c)
   ret double %0
 }
@@ -83,7 +83,7 @@ entry:
   ; CHECK: %[[#i16_arg0:]] = OpFunctionParameter %[[#int_16]]
   ; CHECK: %[[#i16_arg1:]] = OpFunctionParameter %[[#int_16]]
   ; CHECK: %[[#i16_arg2:]] = OpFunctionParameter %[[#int_16]]
-  ; CHECK: %[[#]] = OpExtInst %[[#int_16]] %[[#op_ext_glsl]] UClamp 
%[[#i16_arg0]] %[[#i16_arg1]] %[[#i16_arg2]]
+  ; CHECK: %[[#]] = OpExtInst %[[#int_16]] %[[#op_ext]] UClamp %[[#i16_arg0]] 
%[[#i16_arg1]] %[[#i16_arg2]]
   %0 = call i16 @llvm.spv.uclamp.i16(i16 %a, i16 %b, i16 %c)
   ret i16 %0
 }
@@ -94,7 +94,7 @@ entry:
   ; CHECK: %[[#i32_arg0:]] = OpFunctionParameter %[[#int_32]]
   ; CHECK: %[[#i32_arg1:]] = OpFunctionParameter %[[#int_32]]
   ; CHECK: %[[#i32_arg2:]] = OpFunctionParameter %[[#int_32]]
-  ; CHECK: %[[#]] = OpExtInst %[[#int_32]] %[[#op_ext_glsl]] UClamp 
%[[#i32_arg0]] %[[#i32_arg1]] %[[#i32_arg2]]
+  ; CHECK: %[[#]] = OpExtInst %[[#int_32]] %[[#op_ext]] UClamp %[[#i32_arg0]] 
%[[#i32_arg1]] %[[#i32_arg2]]
   %0 = call i32 @llvm.spv.uclamp.i32(i32 %a, i32 %b, i32 %c)
   ret i32 %0
 }
@@ -105,7 +105,7 @@ entry:
   ; CHECK: %[[#i64_arg0:]] = OpFunctionParameter %[[#int_64]]
   ; CHECK: %[[#i64_arg1:]] = OpFunctionParameter %[[#int_64]]
   ; CHECK: %[[#i64_arg2:]] = OpFunctionParameter %[[#int_64]]
-  ; CHECK: %[[#]] = OpExtInst %[[#int_64]] %[[#op_ext_glsl]] UClamp 
%[[#i64_arg0]] %[[#i64_arg1]] %[[#i64_arg2]]
+  ; CHECK: %[[#]] = OpExtInst %[[#int_64]] %[[#op_ext]] UClamp %[[#i64_arg0]] 
%[[#i64_arg1]] %[[#i64_arg2]]
   %0 = call i64 @llvm.spv.uclamp.i64(i64 %a, i64 %b, i64 %c)
   ret i64 %0
 }
diff --git a/llvm/test/CodeGen/SPIRV/opencl/clamp-vec.ll 
b/llvm/test/CodeGen/SPIRV/opencl/clamp-vec.ll
new file mode 100644
index 00000000000000..35f5559c46921e
--- /dev/null
+++ b/llvm/test/CodeGen/SPIRV/opencl/clamp-vec.ll
@@ -0,0 +1,132 @@
+; RUN: llc  -verify-machineinstrs -O0 -mtriple=spirv64-unknown-unknown %s -o - 
| FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown %s -o - 
| FileCheck %s
+; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - 
-filetype=obj | spirv-val %}
+; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv32-unknown-unknown %s -o - 
-filetype=obj | spirv-val %}
+
+; CHECK-DAG: %[[#op_ext:]] = OpExtInstImport "OpenCL.std"
+
+; CHECK-DAG: %[[#float_64:]] = OpTypeFloat 64
+; CHECK-DAG: %[[#float_32:]] = OpTypeFloat 32
+; CHECK-DAG: %[[#float_16:]] = OpTypeFloat 16
+
+; CHECK-DAG: %[[#int_64:]] = OpTypeInt 64
+; CHECK-DAG: %[[#int_32:]] = OpTypeInt 32
+; CHECK-DAG: %[[#int_16:]] = OpTypeInt 16
+
+; CHECK-DAG: %[[#vec4_float_64:]] = OpTypeVector %[[#float_64]] 4
+; CHECK-DAG: %[[#vec4_float_32:]] = OpTypeVector %[[#float_32]] 4
+; CHECK-DAG: %[[#vec4_float_16:]] = OpTypeVector %[[#float_16]] 4
+
+; CHECK-DAG: %[[#vec4_int_64:]] = OpTypeVector %[[#int_64]] 4
+; CHECK-DAG: %[[#vec4_int_32:]] = OpTypeVector %[[#int_32]] 4
+; CHECK-DAG: %[[#vec4_int_16:]] = OpTypeVector %[[#int_16]] 4
+
+; CHECK-LABEL: Begin function test_sclamp_v4i16
+define noundef <4 x i16> @test_sclamp_v4i16(<4 x i16> noundef %a, <4 x i16> 
noundef %b, <4 x i16> noundef %c) {
+entry:
+  ; CHECK: %[[#vec4_i16_arg0:]] = OpFunctionParameter %[[#vec4_int_16]]
+  ; CHECK: %[[#vec4_i16_arg1:]] = OpFunctionParameter %[[#vec4_int_16]]
+  ; CHECK: %[[#vec4_i16_arg2:]] = OpFunctionParameter %[[#vec4_int_16]]
+  ; CHECK: %[[#]] = OpExtInst %[[#vec4_int_16]] %[[#op_ext]] s_clamp 
%[[#vec4_i16_arg0]] %[[#vec4_i16_arg1]] %[[#vec4_i16_arg2]]
+  %0 = call <4 x i16> @llvm.spv.sclamp.v4i16(<4 x i16> %a, <4 x i16> %b, <4 x 
i16> %c)
+  ret <4 x i16> %0
+}
+
+; CHECK-LABEL: Begin function test_sclamp_v4i32
+define noundef <4 x i32> @test_sclamp_v4i32(<4 x i32> noundef %a, <4 x i32> 
noundef %b, <4 x i32> noundef %c) {
+entry:
+  ; CHECK: %[[#vec4_i32_arg0:]] = OpFunctionParameter %[[#vec4_int_32]]
+  ; CHECK: %[[#vec4_i32_arg1:]] = OpFunctionParameter %[[#vec4_int_32]]
+  ; CHECK: %[[#vec4_i32_arg2:]] = OpFunctionParameter %[[#vec4_int_32]]
+  ; CHECK: %[[#]] = OpExtInst %[[#vec4_int_32]] %[[#op_ext]] s_clamp 
%[[#vec4_i32_arg0]] %[[#vec4_i32_arg1]] %[[#vec4_i32_arg2]]
+  %0 = call <4 x i32> @llvm.spv.sclamp.v4i32(<4 x i32> %a, <4 x i32> %b, <4 x 
i32> %c)
+  ret <4 x i32> %0
+}
+
+; CHECK-LABEL: Begin function test_sclamp_v4i64
+define noundef <4 x i64> @test_sclamp_v4i64(<4 x i64> noundef %a, <4 x i64> 
noundef %b, <4 x i64> noundef %c) {
+entry:
+  ; CHECK: %[[#vec4_i64_arg0:]] = OpFunctionParameter %[[#vec4_int_64]]
+  ; CHECK: %[[#vec4_i64_arg1:]] = OpFunctionParameter %[[#vec4_int_64]]
+  ; CHECK: %[[#vec4_i64_arg2:]] = OpFunctionParameter %[[#vec4_int_64]]
+  ; CHECK: %[[#]] = OpExtInst %[[#vec4_int_64]] %[[#op_ext]] s_clamp 
%[[#vec4_i64_arg0]] %[[#vec4_i64_arg1]] %[[#vec4_i64_arg2]]
+  %0 = call <4 x i64> @llvm.spv.sclamp.v4i64(<4 x i64> %a, <4 x i64> %b, <4 x 
i64> %c)
+  ret <4 x i64> %0
+}
+
+; CHECK-LABEL: Begin function test_fclamp_v4half
+define noundef <4 x half> @test_fclamp_v4half(<4 x half> noundef %a, <4 x 
half> noundef %b, <4 x half> noundef %c) {
+entry:
+  ; CHECK: %[[#vec4_f16_arg0:]] = OpFunctionParameter %[[#vec4_float_16]]
+  ; CHECK: %[[#vec4_f16_arg1:]] = OpFunctionParameter %[[#vec4_float_16]]
+  ; CHECK: %[[#vec4_f16_arg2:]] = OpFunctionParameter %[[#vec4_float_16]]
+  ; CHECK: %[[#]] = OpExtInst %[[#vec4_float_16]] %[[#op_ext]] fclamp 
%[[#vec4_f16_arg0]] %[[#vec4_f16_arg1]] %[[#vec4_f16_arg2]]
+  %0 = call <4 x half> @llvm.spv.fclamp.v4f16(<4 x half> %a, <4 x half> %b, <4 
x half> %c)
+  ret <4 x half> %0
+}
+
+; CHECK-LABEL: Begin function test_fclamp_v4float
+define noundef <4 x float> @test_fclamp_v4float(<4 x float> noundef %a, <4 x 
float> noundef %b, <4 x float> noundef %c) {
+entry:
+  ; CHECK: %[[#vec4_f32_arg0:]] = OpFunctionParameter %[[#vec4_float_32]]
+  ; CHECK: %[[#vec4_f32_arg1:]] = OpFunctionParameter %[[#vec4_float_32]]
+  ; CHECK: %[[#vec4_f32_arg2:]] = OpFunctionParameter %[[#vec4_float_32]]
+  ; CHECK: %[[#]] = OpExtInst %[[#vec4_float_32]] %[[#op_ext]] fclamp 
%[[#vec4_f32_arg0]] %[[#vec4_f32_arg1]] %[[#vec4_f32_arg2]]
+  %0 = call <4 x float> @llvm.spv.fclamp.v4f32(<4 x float> %a, <4 x float> %b, 
<4 x float> %c)
+  ret <4 x float> %0
+}
+
+; CHECK-LABEL: Begin function test_fclamp_v4double
+define noundef <4 x double> @test_fclamp_v4double(<4 x double> noundef %a, <4 
x double> noundef %b, <4 x double> noundef %c) {
+entry:
+  ; CHECK: %[[#vec4_f64_arg0:]] = OpFunctionParameter %[[#vec4_float_64]]
+  ; CHECK: %[[#vec4_f64_arg1:]] = OpFunctionParameter %[[#vec4_float_64]]
+  ; CHECK: %[[#vec4_f64_arg2:]] = OpFunctionParameter %[[#vec4_float_64]]
+  ; CHECK: %[[#]] = OpExtInst %[[#vec4_float_64]] %[[#op_ext]] fclamp 
%[[#vec4_f64_arg0]] %[[#vec4_f64_arg1]] %[[#vec4_f64_arg2]]
+  %0 = call <4 x double> @llvm.spv.fclamp.v4f64(<4 x double> %a, <4 x double> 
%b, <4 x double> %c)
+  ret <4 x double> %0
+}
+
+; CHECK-LABEL: Begin function test_uclamp_v4i16
+define noundef <4 x i16> @test_uclamp_v4i16(<4 x i16> noundef %a, <4 x i16> 
noundef %b, <4 x i16> noundef %c) {
+entry:
+  ; CHECK: %[[#vec4_i16_arg0:]] = OpFunctionParameter %[[#vec4_int_16]]
+  ; CHECK: %[[#vec4_i16_arg1:]] = OpFunctionParameter %[[#vec4_int_16]]
+  ; CHECK: %[[#vec4_i16_arg2:]] = OpFunctionParameter %[[#vec4_int_16]]
+  ; CHECK: %[[#]] = OpExtInst %[[#vec4_int_16]] %[[#op_ext]] u_clamp 
%[[#vec4_i16_arg0]] %[[#vec4_i16_arg1]] %[[#vec4_i16_arg2]]
+  %0 = call <4 x i16> @llvm.spv.uclamp.v4i16(<4 x i16> %a, <4 x i16> %b, <4 x 
i16> %c)
+  ret <4 x i16> %0
+}
+
+; CHECK-LABEL: Begin function test_uclamp_v4i32
+define noundef <4 x i32> @test_uclamp_v4i32(<4 x i32> noundef %a, <4 x i32> 
noundef %b, <4 x i32> noundef %c) {
+entry:
+  ; CHECK: %[[#vec4_i32_arg0:]] = OpFunctionParameter %[[#vec4_int_32]]
+  ; CHECK: %[[#vec4_i32_arg1:]] = OpFunctionParameter %[[#vec4_int_32]]
+  ; CHECK: %[[#vec4_i32_arg2:]] = OpFunctionParameter %[[#vec4_int_32]]
+  ; CHECK: %[[#]] = OpExtInst %[[#vec4_int_32]] %[[#op_ext]] u_clamp 
%[[#vec4_i32_arg0]] %[[#vec4_i32_arg1]] %[[#vec4_i32_arg2]]
+  %0 = call <4 x i32> @llvm.spv.uclamp.v4i32(<4 x i32> %a, <4 x i32> %b, <4 x 
i32> %c)
+  ret <4 x i32> %0
+}
+
+; CHECK-LABEL: Begin function test_uclamp_v4i64
+define noundef <4 x i64> @test_uclamp_v4i64(<4 x i64> noundef %a, <4 x i64> 
noundef %b, <4 x i64> noundef %c) {
+entry:
+  ; CHECK: %[[#vec4_i64_arg0:]] = OpFunctionParameter %[[#vec4_int_64]]
+  ; CHECK: %[[#vec4_i64_arg1:]] = OpFunctionParameter %[[#vec4_int_64]]
+  ; CHECK: %[[#vec4_i64_arg2:]] = OpFunctionParameter %[[#vec4_int_64]]
+  ; CHECK: %[[#]] = OpExtInst %[[#vec4_int_64]] %[[#op_ext]] u_clamp 
%[[#vec4_i64_arg0]] %[[#vec4_i64_arg1]] %[[#vec4_i64_arg2]]
+  %0 = call <4 x i64> @llvm.spv.uclamp.v4i64(<4 x i64> %a, <4 x i64> %b, <4 x 
i64> %c)
+  ret <4 x i64> %0
+}
+
+declare <4 x half> @llvm.spv.fclamp.v4f16(<4 x half>, <4 x half>, <4 x half>)
+declare <4 x float> @llvm.spv.fclamp.v4f32(<4 x float>, <4 x float>, <4 x 
float>)
+declare <4 x double> @llvm.spv.fclamp.v4f64(<4 x double>, <4 x double>, <4 x 
double>)
+declare <4 x i16> @llvm.spv.sclamp.v4i16(<4 x i16>, <4 x i16>, <4 x i16>)
+declare <4 x i32> @llvm.spv.sclamp.v4i32(<4 x i32>, <4 x i32>, <4 x i32>)
+declare <4 x i64> @llvm.spv.sclamp.v4i64(<4 x i64>, <4 x i64>, <4 x i64>)
+declare <4 x i16> @llvm.spv.uclamp.v4i16(<4 x i16>, <4 x i16>, <4 x i16>)
+declare <4 x i32> @llvm.spv.uclamp.v4i32(<4 x i32>, <4 x i32>, <4 x i32>)
+declare <4 x i64> @llvm.spv.uclamp.v4i64(<4 x i64>, <4 x i64>, <4 x i64>)
+
diff --git a/llvm/test/CodeGen/SPIRV/opencl/clamp.ll 
b/llvm/test/CodeGen/SPIRV/opencl/clamp.ll
new file mode 100644
index 00000000000000..f6500442042cd9
--- /dev/null
+++ b/llvm/test/CodeGen/SPIRV/opencl/clamp.ll
@@ -0,0 +1,124 @@
+; RUN: llc  -verify-machineinstrs -O0 -mtriple=spirv64-unknown-unknown %s -o - 
| FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown %s -o - 
| FileCheck %s
+; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - 
-filetype=obj | spirv-val %}
+; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv32-unknown-unknown %s -o - 
-filetype=obj | spirv-val %}
+
+; CHECK-DAG: %[[#op_ext:]] = OpExtInstImport "OpenCL.std"
+
+; CHECK-DAG: %[[#float_64:]] = OpTypeFloat 64
+; CHECK-DAG: %[[#float_32:]] = OpTypeFloat 32
+; CHECK-DAG: %[[#float_16:]] = OpTypeFloat 16
+
+; CHECK-DAG: %[[#int_64:]] = OpTypeInt 64
+; CHECK-DAG: %[[#int_32:]] = OpTypeInt 32
+; CHECK-DAG: %[[#int_16:]] = OpTypeInt 16
+
+; CHECK-LABEL: Begin function test_sclamp_i16
+define noundef i16 @test_sclamp_i16(i16 noundef %a, i16 noundef %b, i16 
noundef %c) {
+entry:
+  ; CHECK: %[[#i16_arg0:]] = OpFunctionParameter %[[#int_16]]
+  ; CHECK: %[[#i16_arg1:]] = OpFunctionParameter %[[#int_16]]
+  ; CHECK: %[[#i16_arg2:]] = OpFunctionParameter %[[#int_16]]
+  ; CHECK: %[[#]] = OpExtInst %[[#int_16]] %[[#op_ext]] s_clamp %[[#i16_arg0]] 
%[[#i16_arg1]] %[[#i16_arg2]]
+  %0 = call i16 @llvm.spv.sclamp.i16(i16 %a, i16 %b, i16 %c)
+  ret i16 %0
+}
+
+; CHECK-LABEL: Begin function test_sclamp_i32
+define noundef i32 @test_sclamp_i32(i32 noundef %a, i32 noundef %b, i32 
noundef %c) {
+entry:
+  ; CHECK: %[[#i32_arg0:]] = OpFunctionParameter %[[#int_32]]
+  ; CHECK: %[[#i32_arg1:]] = OpFunctionParameter %[[#int_32]]
+  ; CHECK: %[[#i32_arg2:]] = OpFunctionParameter %[[#int_32]]
+  ; CHECK: %[[#]] = OpExtInst %[[#int_32]] %[[#op_ext]] s_clamp %[[#i32_arg0]] 
%[[#i32_arg1]] %[[#i32_arg2]]
+  %0 = call i32 @llvm.spv.sclamp.i32(i32 %a, i32 %b, i32 %c)
+  ret i32 %0
+}
+
+; CHECK-LABEL: Begin function test_sclamp_i64
+define noundef i64 @test_sclamp_i64(i64 noundef %a, i64 noundef %b, i64 
noundef %c) {
+entry:
+  ; CHECK: %[[#i64_arg0:]] = OpFunctionParameter %[[#int_64]]
+  ; CHECK: %[[#i64_arg1:]] = OpFunctionParameter %[[#int_64]]
+  ; CHECK: %[[#i64_arg2:]] = OpFunctionParameter %[[#int_64]]
+  ; CHECK: %[[#]] = OpExtInst %[[#int_64]] %[[#op_ext]] s_clamp %[[#i64_arg0]] 
%[[#i64_arg1]] %[[#i64_arg2]]
+  %0 = call i64 @llvm.spv.sclamp.i64(i64 %a, i64 %b, i64 %c)
+  ret i64 %0
+}
+
+; CHECK-LABEL: Begin function test_fclamp_half
+define noundef half @test_fclamp_half(half noundef %a, half noundef %b, half 
noundef %c) {
+entry:
+  ; CHECK: %[[#f16_arg0:]] = OpFunctionParameter %[[#float_16]]
+  ; CHECK: %[[#f16_arg1:]] = OpFunctionParameter %[[#float_16]]
+  ; CHECK: %[[#f16_arg2:]] = OpFunctionParameter %[[#float_16]]
+  ; CHECK: %[[#]] = OpExtInst %[[#float_16]] %[[#op_ext]] fclamp 
%[[#f16_arg0]] %[[#f16_arg1]] %[[#f16_arg2]]
+  %0 = call half @llvm.spv.fclamp.f16(half %a, half %b, half %c)
+  ret half %0
+}
+
+; CHECK-LABEL: Begin function test_fclamp_float
+define noundef float @test_fclamp_float(float noundef %a, float noundef %b, 
float noundef %c) {
+entry:
+  ; CHECK: %[[#f32_arg0:]] = OpFunctionParameter %[[#float_32]]
+  ; CHECK: %[[#f32_arg1:]] = OpFunctionParameter %[[#float_32]]
+  ; CHECK: %[[#f32_arg2:]] = OpFunctionParameter %[[#float_32]]
+  ; CHECK: %[[#]] = OpExtInst %[[#float_32]] %[[#op_ext]] fclamp 
%[[#f32_arg0]] %[[#f32_arg1]] %[[#f32_arg2]]
+  %0 = call float @llvm.spv.fclamp.f32(float %a, float %b, float %c)
+  ret float %0
+}
+
+; CHECK-LABEL: Begin function test_fclamp_double
+define noundef double @test_fclamp_double(double noundef %a, double noundef 
%b, double noundef %c) {
+entry:
+  ; CHECK: %[[#f64_arg0:]] = OpFunctionParameter %[[#float_64]]
+  ; CHECK: %[[#f64_arg1:]] = OpFunctionParameter %[[#float_64]]
+  ; CHECK: %[[#f64_arg2:]] = OpFunctionParameter %[[#float_64]]
+  ; CHECK: %[[#]] = OpExtInst %[[#float_64]] %[[#op_ext]] fclamp 
%[[#f64_arg0]] %[[#f64_arg1]] %[[#f64_arg2]]
+  %0 = call double @llvm.spv.fclamp.f64(double %a, double %b, double %c)
+  ret double %0
+}
+
+; CHECK-LABEL: Begin function test_uclamp_i16
+define noundef i16 @test_uclamp_i16(i16 noundef %a, i16 noundef %b, i16 
noundef %c) {
+entry:
+  ; CHECK: %[[#i16_arg0:]] = OpFunctionParameter %[[#int_16]]
+  ; CHECK: %[[#i16_arg1:]] = OpFunctionParameter %[[#int_16]]
+  ; CHECK: %[[#i16_arg2:]] = OpFunctionParameter %[[#int_16]]
+  ; CHECK: %[[#]] = OpExtInst %[[#int_16]] %[[#op_ext]] u_clamp %[[#i16_arg0]] 
%[[#i16_arg1]] %[[#i16_arg2]]
+  %0 = call i16 @llvm.spv.uclamp.i16(i16 %a, i16 %b, i16 %c)
+  ret i16 %0
+}
+
+; CHECK-LABEL: Begin function test_uclamp_i32
+define noundef i32 @test_uclamp_i32(i32 noundef %a, i32 noundef %b, i32 
noundef %c) {
+entry:
+  ; CHECK: %[[#i32_arg0:]] = OpFunctionParameter %[[#int_32]]
+  ; CHECK: %[[#i32_arg1:]] = OpFunctionParameter %[[#int_32]]
+  ; CHECK: %[[#i32_arg2:]] = OpFunctionParameter %[[#int_32]]
+  ; CHECK: %[[#]] = OpExtInst %[[#int_32]] %[[#op_ext]] u_clamp %[[#i32_arg0]] 
%[[#i32_arg1]] %[[#i32_arg2]]
+  %0 = call i32 @llvm.spv.uclamp.i32(i32 %a, i32 %b, i32 %c)
+  ret i32 %0
+}
+
+; CHECK-LABEL: Begin function test_uclamp_i64
+define noundef i64 @test_uclamp_i64(i64 noundef %a, i64 noundef %b, i64 
noundef %c) {
+entry:
+  ; CHECK: %[[#i64_arg0:]] = OpFunctionParameter %[[#int_64]]
+  ; CHECK: %[[#i64_arg1:]] = OpFunctionParameter %[[#int_64]]
+  ; CHECK: %[[#i64_arg2:]] = OpFunctionParameter %[[#int_64]]
+  ; CHECK: %[[#]] = OpExtInst %[[#int_64]] %[[#op_ext]] u_clamp %[[#i64_arg0]] 
%[[#i64_arg1]] %[[#i64_arg2]]
+  %0 = call i64 @llvm.spv.uclamp.i64(i64 %a, i64 %b, i64 %c)
+  ret i64 %0
+}
+
+declare half @llvm.spv.fclamp.f16(half, half, half)
+declare float @llvm.spv.fclamp.f32(float, float, float)
+declare double @llvm.spv.fclamp.f64(double, double, double)
+declare i16 @llvm.spv.sclamp.i16(i16, i16, i16)
+declare i32 @llvm.spv.sclamp.i32(i32, i32, i32)
+declare i64 @llvm.spv.sclamp.i64(i64, i64, i64)
+declare i16 @llvm.spv.uclamp.i16(i16, i16, i16)
+declare i32 @llvm.spv.uclamp.i32(i32, i32, i32)
+declare i64 @llvm.spv.uclamp.i64(i64, i64, i64)
+

>From 47b1e850b1c9f1b8bbede756b2b4413e29967627 Mon Sep 17 00:00:00 2001
From: Adam Yang <31109344+adam-y...@users.noreply.github.com>
Date: Tue, 22 Oct 2024 16:10:53 -0700
Subject: [PATCH 4/6] Fixed a weirdness in the CG

---
 clang/lib/CodeGen/CGBuiltin.cpp | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp
index 1087537ae4ee29..f6f6366cdccf1c 100644
--- a/clang/lib/CodeGen/CGBuiltin.cpp
+++ b/clang/lib/CodeGen/CGBuiltin.cpp
@@ -18661,10 +18661,9 @@ Value *CodeGenFunction::EmitHLSLBuiltinExpr(unsigned 
BuiltinID,
     Value *OpMax = EmitScalarExpr(E->getArg(2));
 
     QualType Ty = E->getArg(0)->getType();
-    bool IsUnsigned = false;
     if (auto *VecTy = Ty->getAs<VectorType>())
       Ty = VecTy->getElementType();
-    IsUnsigned = Ty->isUnsignedIntegerType();
+    bool IsUnsigned = Ty->isUnsignedIntegerType();
     switch (CGM.getTarget().getTriple().getArch()) {
     case llvm::Triple::dxil: {
       return Builder.CreateIntrinsic(

>From 549d95a40d991d4e2897cb76e7e6bd71ef6f5ee4 Mon Sep 17 00:00:00 2001
From: Adam Yang <31109344+adam-y...@users.noreply.github.com>
Date: Thu, 24 Oct 2024 16:35:56 -0700
Subject: [PATCH 5/6] Addressed feedback.

---
 clang/lib/CodeGen/CGBuiltin.cpp               |  44 ++---
 clang/lib/CodeGen/CGHLSLRuntime.h             |   3 +
 .../CodeGenHLSL/builtins/clamp-builtin.hlsl   |   4 +-
 clang/test/CodeGenHLSL/builtins/clamp.hlsl    | 168 +++++++++---------
 llvm/include/llvm/IR/IntrinsicsDirectX.td     |   3 +-
 llvm/include/llvm/IR/IntrinsicsSPIRV.td       |   6 +-
 .../Target/DirectX/DXILIntrinsicExpansion.cpp |  46 +++--
 .../Target/SPIRV/SPIRVInstructionSelector.cpp |   4 +-
 .../SPIRV/hlsl-intrinsics/clamp-vec.ll        |  30 ++--
 .../CodeGen/SPIRV/hlsl-intrinsics/clamp.ll    |  30 ++--
 llvm/test/CodeGen/SPIRV/opencl/clamp-vec.ll   |  24 +--
 llvm/test/CodeGen/SPIRV/opencl/clamp.ll       |  24 +--
 12 files changed, 189 insertions(+), 197 deletions(-)

diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp
index f6f6366cdccf1c..afa0bf04524903 100644
--- a/clang/lib/CodeGen/CGBuiltin.cpp
+++ b/clang/lib/CodeGen/CGBuiltin.cpp
@@ -18656,35 +18656,29 @@ Value *CodeGenFunction::EmitHLSLBuiltinExpr(unsigned 
BuiltinID,
         "hlsl.any");
   }
   case Builtin::BI__builtin_hlsl_elementwise_clamp: {
-    Value *OpX = EmitScalarExpr(E->getArg(0));
-    Value *OpMin = EmitScalarExpr(E->getArg(1));
-    Value *OpMax = EmitScalarExpr(E->getArg(2));
+    Value* OpX = EmitScalarExpr(E->getArg(0));
+    Value* OpMin = EmitScalarExpr(E->getArg(1));
+    Value* OpMax = EmitScalarExpr(E->getArg(2));
 
     QualType Ty = E->getArg(0)->getType();
-    if (auto *VecTy = Ty->getAs<VectorType>())
+    if (auto* VecTy = Ty->getAs<VectorType>())
       Ty = VecTy->getElementType();
-    bool IsUnsigned = Ty->isUnsignedIntegerType();
-    switch (CGM.getTarget().getTriple().getArch()) {
-    case llvm::Triple::dxil: {
-      return Builder.CreateIntrinsic(
-          /*ReturnType=*/OpX->getType(),
-          IsUnsigned ? Intrinsic::dx_uclamp : Intrinsic::dx_clamp,
-          ArrayRef<Value *>{OpX, OpMin, OpMax}, nullptr, "dx.clamp");
-    } break;
-    case llvm::Triple::spirv: {
-      Intrinsic::ID Intr = Intrinsic::spv_sclamp;
-      if (Ty->isFloatingType()) {
-        Intr = Intrinsic::spv_fclamp;
-      } else if (IsUnsigned) {
-        Intr = Intrinsic::spv_uclamp;
-      }
-      return Builder.CreateIntrinsic(OpX->getType(), Intr,
-                                     ArrayRef<Value *>{OpX, OpMin, OpMax},
-                                     nullptr, "spv.clamp");
-    } break;
-    default:
-      llvm_unreachable("Intrinsic clamp not supported by target architecture");
+
+    Intrinsic::ID Intr;
+    if (Ty->isFloatingType()) {
+      Intr = CGM.getHLSLRuntime().getNClampIntrinsic();
+    }
+    else if (Ty->isUnsignedIntegerType()) {
+      Intr = CGM.getHLSLRuntime().getUClampIntrinsic();
     }
+    else {
+      assert(Ty->isSignedIntegerType());
+      Intr = CGM.getHLSLRuntime().getSClampIntrinsic();
+    }
+    return Builder.CreateIntrinsic(
+      /*ReturnType=*/OpX->getType(),
+      Intr,
+      ArrayRef<Value*>{OpX, OpMin, OpMax}, nullptr, "hlsl.clamp");
   }
   case Builtin::BI__builtin_hlsl_cross: {
     Value *Op0 = EmitScalarExpr(E->getArg(0));
diff --git a/clang/lib/CodeGen/CGHLSLRuntime.h 
b/clang/lib/CodeGen/CGHLSLRuntime.h
index ff7df41b5c62e7..5fac7e45a5e5d6 100644
--- a/clang/lib/CodeGen/CGHLSLRuntime.h
+++ b/clang/lib/CodeGen/CGHLSLRuntime.h
@@ -91,6 +91,9 @@ class CGHLSLRuntime {
   GENERATE_HLSL_INTRINSIC_FUNCTION(UDot, udot)
   GENERATE_HLSL_INTRINSIC_FUNCTION(WaveIsFirstLane, wave_is_first_lane)
   GENERATE_HLSL_INTRINSIC_FUNCTION(WaveReadLaneAt, wave_readlane)
+  GENERATE_HLSL_INTRINSIC_FUNCTION(NClamp, nclamp)
+  GENERATE_HLSL_INTRINSIC_FUNCTION(SClamp, sclamp)
+  GENERATE_HLSL_INTRINSIC_FUNCTION(UClamp, uclamp)
 
   GENERATE_HLSL_INTRINSIC_FUNCTION(CreateHandleFromBinding, handle_fromBinding)
 
diff --git a/clang/test/CodeGenHLSL/builtins/clamp-builtin.hlsl 
b/clang/test/CodeGenHLSL/builtins/clamp-builtin.hlsl
index e3ef26429e7e40..62bada715a68ad 100644
--- a/clang/test/CodeGenHLSL/builtins/clamp-builtin.hlsl
+++ b/clang/test/CodeGenHLSL/builtins/clamp-builtin.hlsl
@@ -1,8 +1,8 @@
 // RUN: %clang_cc1 -finclude-default-header -x hlsl -triple 
dxil-pc-shadermodel6.3-library %s -fnative-half-type -emit-llvm 
-disable-llvm-passes -o - | FileCheck %s
 
 // CHECK-LABEL: builtin_test_clamp_int4
-// CHECK: %dx.clamp = call <4 x i32> @llvm.dx.clamp.v4i32(<4 x i32> %0, <4 x 
i32> %1, <4 x i32> %2)
-// CHECK: ret <4 x i32> %dx.clamp
+// CHECK: %hlsl.clamp = call <4 x i32> @llvm.dx.sclamp.v4i32(<4 x i32> %0, <4 
x i32> %1, <4 x i32> %2)
+// CHECK: ret <4 x i32> %hlsl.clamp
 int4 builtin_test_clamp_int4(int4 p0, int4 p1, int4 p2) {
   return __builtin_hlsl_elementwise_clamp(p0, p1, p2);
 }
diff --git a/clang/test/CodeGenHLSL/builtins/clamp.hlsl 
b/clang/test/CodeGenHLSL/builtins/clamp.hlsl
index 806e786ae70931..3489f3d3e2b09e 100644
--- a/clang/test/CodeGenHLSL/builtins/clamp.hlsl
+++ b/clang/test/CodeGenHLSL/builtins/clamp.hlsl
@@ -1,143 +1,143 @@
 // RUN: %clang_cc1 -finclude-default-header -triple 
dxil-pc-shadermodel6.3-library %s \
 // RUN:  -fnative-half-type -emit-llvm -disable-llvm-passes -o - | \
 // RUN:  FileCheck %s --check-prefixes=CHECK,NATIVE_HALF \
-// RUN:  -DSCLAMP="dx.clamp" -DUCLAMP="dx.uclamp" -DFCLAMP="dx.clamp" 
-DFNATTR="noundef"
+// RUN:  -DTARGET=dx -DFNATTRS=noundef
 // RUN: %clang_cc1 -finclude-default-header -triple 
dxil-pc-shadermodel6.3-library %s \
 // RUN:  -emit-llvm -disable-llvm-passes -o - | \
 // RUN:  FileCheck %s --check-prefixes=CHECK,NO_HALF \
-// RUN:  -DSCLAMP="dx.clamp" -DUCLAMP="dx.uclamp" -DFCLAMP="dx.clamp" 
-DFNATTR="noundef"
+// RUN:  -DTARGET=dx -DFNATTRS=noundef
 // RUN: %clang_cc1 -finclude-default-header -triple 
spirv-unknown-vulkan-compute %s \
 // RUN:  -fnative-half-type -emit-llvm -disable-llvm-passes -o - | \
 // RUN:  FileCheck %s --check-prefixes=CHECK,NATIVE_HALF \
-// RUN:  -DSCLAMP="spv.sclamp" -DUCLAMP="spv.uclamp" -DFCLAMP="spv.fclamp" 
-DFNATTR="spir_func noundef"
+// RUN:  -DTARGET=spv -DFNATTRS="spir_func noundef"
 // RUN: %clang_cc1 -finclude-default-header -triple 
spirv-unknown-vulkan-compute %s \
 // RUN:  -emit-llvm -disable-llvm-passes -o - | \
 // RUN:  FileCheck %s --check-prefixes=CHECK,NO_HALF \
-// RUN:  -DSCLAMP="spv.sclamp" -DUCLAMP="spv.uclamp" -DFCLAMP="spv.fclamp" 
-DFNATTR="spir_func noundef"
+// RUN:  -DTARGET=spv -DFNATTRS="spir_func noundef"
 
 #ifdef __HLSL_ENABLE_16_BIT
-// NATIVE_HALF: define [[FNATTR]] i16 @_Z16test_clamp_short
-// NATIVE_HALF: call i16 @llvm.[[SCLAMP]].i16(
+// NATIVE_HALF: define [[FNATTRS]] i16 @_Z16test_clamp_short
+// NATIVE_HALF: call i16 @llvm.[[TARGET]].sclamp.i16(
 int16_t test_clamp_short(int16_t p0, int16_t p1) { return clamp(p0, p1,p1); }
-// NATIVE_HALF: define [[FNATTR]] <2 x i16> @_Z17test_clamp_short2
-// NATIVE_HALF: call <2 x i16> @llvm.[[SCLAMP]].v2i16(
+// NATIVE_HALF: define [[FNATTRS]] <2 x i16> @_Z17test_clamp_short2
+// NATIVE_HALF: call <2 x i16> @llvm.[[TARGET]].sclamp.v2i16(
 int16_t2 test_clamp_short2(int16_t2 p0, int16_t2 p1) { return clamp(p0, 
p1,p1); }
-// NATIVE_HALF: define [[FNATTR]] <3 x i16> @_Z17test_clamp_short3
-// NATIVE_HALF: call <3 x i16> @llvm.[[SCLAMP]].v3i16
+// NATIVE_HALF: define [[FNATTRS]] <3 x i16> @_Z17test_clamp_short3
+// NATIVE_HALF: call <3 x i16> @llvm.[[TARGET]].sclamp.v3i16
 int16_t3 test_clamp_short3(int16_t3 p0, int16_t3 p1) { return clamp(p0, 
p1,p1); }
-// NATIVE_HALF: define [[FNATTR]] <4 x i16> @_Z17test_clamp_short4
-// NATIVE_HALF: call <4 x i16> @llvm.[[SCLAMP]].v4i16
+// NATIVE_HALF: define [[FNATTRS]] <4 x i16> @_Z17test_clamp_short4
+// NATIVE_HALF: call <4 x i16> @llvm.[[TARGET]].sclamp.v4i16
 int16_t4 test_clamp_short4(int16_t4 p0, int16_t4 p1) { return clamp(p0, 
p1,p1); }
 
-// NATIVE_HALF: define [[FNATTR]] i16 @_Z17test_clamp_ushort
-// NATIVE_HALF: call i16 @llvm.[[UCLAMP]].i16(
+// NATIVE_HALF: define [[FNATTRS]] i16 @_Z17test_clamp_ushort
+// NATIVE_HALF: call i16 @llvm.[[TARGET]].uclamp.i16(
 uint16_t test_clamp_ushort(uint16_t p0, uint16_t p1) { return clamp(p0, 
p1,p1); }
-// NATIVE_HALF: define [[FNATTR]] <2 x i16> @_Z18test_clamp_ushort2
-// NATIVE_HALF: call <2 x i16> @llvm.[[UCLAMP]].v2i16
+// NATIVE_HALF: define [[FNATTRS]] <2 x i16> @_Z18test_clamp_ushort2
+// NATIVE_HALF: call <2 x i16> @llvm.[[TARGET]].uclamp.v2i16
 uint16_t2 test_clamp_ushort2(uint16_t2 p0, uint16_t2 p1) { return clamp(p0, 
p1,p1); }
-// NATIVE_HALF: define [[FNATTR]] <3 x i16> @_Z18test_clamp_ushort3
-// NATIVE_HALF: call <3 x i16> @llvm.[[UCLAMP]].v3i16
+// NATIVE_HALF: define [[FNATTRS]] <3 x i16> @_Z18test_clamp_ushort3
+// NATIVE_HALF: call <3 x i16> @llvm.[[TARGET]].uclamp.v3i16
 uint16_t3 test_clamp_ushort3(uint16_t3 p0, uint16_t3 p1) { return clamp(p0, 
p1,p1); }
-// NATIVE_HALF: define [[FNATTR]] <4 x i16> @_Z18test_clamp_ushort4
-// NATIVE_HALF: call <4 x i16> @llvm.[[UCLAMP]].v4i16
+// NATIVE_HALF: define [[FNATTRS]] <4 x i16> @_Z18test_clamp_ushort4
+// NATIVE_HALF: call <4 x i16> @llvm.[[TARGET]].uclamp.v4i16
 uint16_t4 test_clamp_ushort4(uint16_t4 p0, uint16_t4 p1) { return clamp(p0, 
p1,p1); }
 #endif
 
-// CHECK: define [[FNATTR]] i32 @_Z14test_clamp_int
-// CHECK: call i32 @llvm.[[SCLAMP]].i32(
+// CHECK: define [[FNATTRS]] i32 @_Z14test_clamp_int
+// CHECK: call i32 @llvm.[[TARGET]].sclamp.i32(
 int test_clamp_int(int p0, int p1) { return clamp(p0, p1,p1); }
-// CHECK: define [[FNATTR]] <2 x i32> @_Z15test_clamp_int2
-// CHECK: call <2 x i32> @llvm.[[SCLAMP]].v2i32
+// CHECK: define [[FNATTRS]] <2 x i32> @_Z15test_clamp_int2
+// CHECK: call <2 x i32> @llvm.[[TARGET]].sclamp.v2i32
 int2 test_clamp_int2(int2 p0, int2 p1) { return clamp(p0, p1,p1); }
-// CHECK: define [[FNATTR]] <3 x i32> @_Z15test_clamp_int3
-// CHECK: call <3 x i32> @llvm.[[SCLAMP]].v3i32
+// CHECK: define [[FNATTRS]] <3 x i32> @_Z15test_clamp_int3
+// CHECK: call <3 x i32> @llvm.[[TARGET]].sclamp.v3i32
 int3 test_clamp_int3(int3 p0, int3 p1) { return clamp(p0, p1,p1); }
-// CHECK: define [[FNATTR]] <4 x i32> @_Z15test_clamp_int4
-// CHECK: call <4 x i32> @llvm.[[SCLAMP]].v4i32
+// CHECK: define [[FNATTRS]] <4 x i32> @_Z15test_clamp_int4
+// CHECK: call <4 x i32> @llvm.[[TARGET]].sclamp.v4i32
 int4 test_clamp_int4(int4 p0, int4 p1) { return clamp(p0, p1,p1); }
 
-// CHECK: define [[FNATTR]] i32 @_Z15test_clamp_uint
-// CHECK: call i32 @llvm.[[UCLAMP]].i32(
+// CHECK: define [[FNATTRS]] i32 @_Z15test_clamp_uint
+// CHECK: call i32 @llvm.[[TARGET]].uclamp.i32(
 int test_clamp_uint(uint p0, uint p1) { return clamp(p0, p1,p1); }
-// CHECK: define [[FNATTR]] <2 x i32> @_Z16test_clamp_uint2
-// CHECK: call <2 x i32> @llvm.[[UCLAMP]].v2i32
+// CHECK: define [[FNATTRS]] <2 x i32> @_Z16test_clamp_uint2
+// CHECK: call <2 x i32> @llvm.[[TARGET]].uclamp.v2i32
 uint2 test_clamp_uint2(uint2 p0, uint2 p1) { return clamp(p0, p1,p1); }
-// CHECK: define [[FNATTR]] <3 x i32> @_Z16test_clamp_uint3
-// CHECK: call <3 x i32> @llvm.[[UCLAMP]].v3i32
+// CHECK: define [[FNATTRS]] <3 x i32> @_Z16test_clamp_uint3
+// CHECK: call <3 x i32> @llvm.[[TARGET]].uclamp.v3i32
 uint3 test_clamp_uint3(uint3 p0, uint3 p1) { return clamp(p0, p1,p1); }
-// CHECK: define [[FNATTR]] <4 x i32> @_Z16test_clamp_uint4
-// CHECK: call <4 x i32> @llvm.[[UCLAMP]].v4i32
+// CHECK: define [[FNATTRS]] <4 x i32> @_Z16test_clamp_uint4
+// CHECK: call <4 x i32> @llvm.[[TARGET]].uclamp.v4i32
 uint4 test_clamp_uint4(uint4 p0, uint4 p1) { return clamp(p0, p1,p1); }
 
-// CHECK: define [[FNATTR]] i64 @_Z15test_clamp_long
-// CHECK: call i64 @llvm.[[SCLAMP]].i64(
+// CHECK: define [[FNATTRS]] i64 @_Z15test_clamp_long
+// CHECK: call i64 @llvm.[[TARGET]].sclamp.i64(
 int64_t test_clamp_long(int64_t p0, int64_t p1) { return clamp(p0, p1,p1); }
-// CHECK: define [[FNATTR]] <2 x i64> @_Z16test_clamp_long2
-// CHECK: call <2 x i64> @llvm.[[SCLAMP]].v2i64
+// CHECK: define [[FNATTRS]] <2 x i64> @_Z16test_clamp_long2
+// CHECK: call <2 x i64> @llvm.[[TARGET]].sclamp.v2i64
 int64_t2 test_clamp_long2(int64_t2 p0, int64_t2 p1) { return clamp(p0, p1,p1); 
}
-// CHECK: define [[FNATTR]] <3 x i64> @_Z16test_clamp_long3
-// CHECK: call <3 x i64> @llvm.[[SCLAMP]].v3i64
+// CHECK: define [[FNATTRS]] <3 x i64> @_Z16test_clamp_long3
+// CHECK: call <3 x i64> @llvm.[[TARGET]].sclamp.v3i64
 int64_t3 test_clamp_long3(int64_t3 p0, int64_t3 p1) { return clamp(p0, p1,p1); 
}
-// CHECK: define [[FNATTR]] <4 x i64> @_Z16test_clamp_long4
-// CHECK: call <4 x i64> @llvm.[[SCLAMP]].v4i64
+// CHECK: define [[FNATTRS]] <4 x i64> @_Z16test_clamp_long4
+// CHECK: call <4 x i64> @llvm.[[TARGET]].sclamp.v4i64
 int64_t4 test_clamp_long4(int64_t4 p0, int64_t4 p1) { return clamp(p0, p1,p1); 
}
 
-// CHECK: define [[FNATTR]] i64 @_Z16test_clamp_ulong
-// CHECK: call i64 @llvm.[[UCLAMP]].i64(
+// CHECK: define [[FNATTRS]] i64 @_Z16test_clamp_ulong
+// CHECK: call i64 @llvm.[[TARGET]].uclamp.i64(
 uint64_t test_clamp_ulong(uint64_t p0, uint64_t p1) { return clamp(p0, p1,p1); 
}
-// CHECK: define [[FNATTR]] <2 x i64> @_Z17test_clamp_ulong2
-// CHECK: call <2 x i64> @llvm.[[UCLAMP]].v2i64
+// CHECK: define [[FNATTRS]] <2 x i64> @_Z17test_clamp_ulong2
+// CHECK: call <2 x i64> @llvm.[[TARGET]].uclamp.v2i64
 uint64_t2 test_clamp_ulong2(uint64_t2 p0, uint64_t2 p1) { return clamp(p0, 
p1,p1); }
-// CHECK: define [[FNATTR]] <3 x i64> @_Z17test_clamp_ulong3
-// CHECK: call <3 x i64> @llvm.[[UCLAMP]].v3i64
+// CHECK: define [[FNATTRS]] <3 x i64> @_Z17test_clamp_ulong3
+// CHECK: call <3 x i64> @llvm.[[TARGET]].uclamp.v3i64
 uint64_t3 test_clamp_ulong3(uint64_t3 p0, uint64_t3 p1) { return clamp(p0, 
p1,p1); }
-// CHECK: define [[FNATTR]] <4 x i64> @_Z17test_clamp_ulong4
-// CHECK: call <4 x i64> @llvm.[[UCLAMP]].v4i64
+// CHECK: define [[FNATTRS]] <4 x i64> @_Z17test_clamp_ulong4
+// CHECK: call <4 x i64> @llvm.[[TARGET]].uclamp.v4i64
 uint64_t4 test_clamp_ulong4(uint64_t4 p0, uint64_t4 p1) { return clamp(p0, 
p1,p1); }
 
-// NATIVE_HALF: define [[FNATTR]] half @_Z15test_clamp_half
-// NATIVE_HALF: call half @llvm.[[FCLAMP]].f16(
-// NO_HALF: define [[FNATTR]] float @_Z15test_clamp_half
-// NO_HALF: call float @llvm.[[FCLAMP]].f32(
+// NATIVE_HALF: define [[FNATTRS]] half @_Z15test_clamp_half
+// NATIVE_HALF: call half @llvm.[[TARGET]].nclamp.f16(
+// NO_HALF: define [[FNATTRS]] float @_Z15test_clamp_half
+// NO_HALF: call float @llvm.[[TARGET]].nclamp.f32(
 half test_clamp_half(half p0, half p1) { return clamp(p0, p1,p1); }
-// NATIVE_HALF: define [[FNATTR]] <2 x half> @_Z16test_clamp_half2
-// NATIVE_HALF: call <2 x half> @llvm.[[FCLAMP]].v2f16
-// NO_HALF: define [[FNATTR]] <2 x float> @_Z16test_clamp_half2
-// NO_HALF: call <2 x float> @llvm.[[FCLAMP]].v2f32(
+// NATIVE_HALF: define [[FNATTRS]] <2 x half> @_Z16test_clamp_half2
+// NATIVE_HALF: call <2 x half> @llvm.[[TARGET]].nclamp.v2f16
+// NO_HALF: define [[FNATTRS]] <2 x float> @_Z16test_clamp_half2
+// NO_HALF: call <2 x float> @llvm.[[TARGET]].nclamp.v2f32(
 half2 test_clamp_half2(half2 p0, half2 p1) { return clamp(p0, p1,p1); }
-// NATIVE_HALF: define [[FNATTR]] <3 x half> @_Z16test_clamp_half3
-// NATIVE_HALF: call <3 x half> @llvm.[[FCLAMP]].v3f16
-// NO_HALF: define [[FNATTR]] <3 x float> @_Z16test_clamp_half3
-// NO_HALF: call <3 x float> @llvm.[[FCLAMP]].v3f32(
+// NATIVE_HALF: define [[FNATTRS]] <3 x half> @_Z16test_clamp_half3
+// NATIVE_HALF: call <3 x half> @llvm.[[TARGET]].nclamp.v3f16
+// NO_HALF: define [[FNATTRS]] <3 x float> @_Z16test_clamp_half3
+// NO_HALF: call <3 x float> @llvm.[[TARGET]].nclamp.v3f32(
 half3 test_clamp_half3(half3 p0, half3 p1) { return clamp(p0, p1,p1); }
-// NATIVE_HALF: define [[FNATTR]] <4 x half> @_Z16test_clamp_half4
-// NATIVE_HALF: call <4 x half> @llvm.[[FCLAMP]].v4f16
-// NO_HALF: define [[FNATTR]] <4 x float> @_Z16test_clamp_half4
-// NO_HALF: call <4 x float> @llvm.[[FCLAMP]].v4f32(
+// NATIVE_HALF: define [[FNATTRS]] <4 x half> @_Z16test_clamp_half4
+// NATIVE_HALF: call <4 x half> @llvm.[[TARGET]].nclamp.v4f16
+// NO_HALF: define [[FNATTRS]] <4 x float> @_Z16test_clamp_half4
+// NO_HALF: call <4 x float> @llvm.[[TARGET]].nclamp.v4f32(
 half4 test_clamp_half4(half4 p0, half4 p1) { return clamp(p0, p1,p1); }
 
-// CHECK: define [[FNATTR]] float @_Z16test_clamp_float
-// CHECK: call float @llvm.[[FCLAMP]].f32(
+// CHECK: define [[FNATTRS]] float @_Z16test_clamp_float
+// CHECK: call float @llvm.[[TARGET]].nclamp.f32(
 float test_clamp_float(float p0, float p1) { return clamp(p0, p1,p1); }
-// CHECK: define [[FNATTR]] <2 x float> @_Z17test_clamp_float2
-// CHECK: call <2 x float> @llvm.[[FCLAMP]].v2f32
+// CHECK: define [[FNATTRS]] <2 x float> @_Z17test_clamp_float2
+// CHECK: call <2 x float> @llvm.[[TARGET]].nclamp.v2f32
 float2 test_clamp_float2(float2 p0, float2 p1) { return clamp(p0, p1,p1); }
-// CHECK: define [[FNATTR]] <3 x float> @_Z17test_clamp_float3
-// CHECK: call <3 x float> @llvm.[[FCLAMP]].v3f32
+// CHECK: define [[FNATTRS]] <3 x float> @_Z17test_clamp_float3
+// CHECK: call <3 x float> @llvm.[[TARGET]].nclamp.v3f32
 float3 test_clamp_float3(float3 p0, float3 p1) { return clamp(p0, p1,p1); }
-// CHECK: define [[FNATTR]] <4 x float> @_Z17test_clamp_float4
-// CHECK: call <4 x float> @llvm.[[FCLAMP]].v4f32
+// CHECK: define [[FNATTRS]] <4 x float> @_Z17test_clamp_float4
+// CHECK: call <4 x float> @llvm.[[TARGET]].nclamp.v4f32
 float4 test_clamp_float4(float4 p0, float4 p1) { return clamp(p0, p1,p1); }
 
-// CHECK: define [[FNATTR]] double @_Z17test_clamp_double
-// CHECK: call double @llvm.[[FCLAMP]].f64(
+// CHECK: define [[FNATTRS]] double @_Z17test_clamp_double
+// CHECK: call double @llvm.[[TARGET]].nclamp.f64(
 double test_clamp_double(double p0, double p1) { return clamp(p0, p1,p1); }
-// CHECK: define [[FNATTR]] <2 x double> @_Z18test_clamp_double2
-// CHECK: call <2 x double> @llvm.[[FCLAMP]].v2f64
+// CHECK: define [[FNATTRS]] <2 x double> @_Z18test_clamp_double2
+// CHECK: call <2 x double> @llvm.[[TARGET]].nclamp.v2f64
 double2 test_clamp_double2(double2 p0, double2 p1) { return clamp(p0, p1,p1); }
-// CHECK: define [[FNATTR]] <3 x double> @_Z18test_clamp_double3
-// CHECK: call <3 x double> @llvm.[[FCLAMP]].v3f64
+// CHECK: define [[FNATTRS]] <3 x double> @_Z18test_clamp_double3
+// CHECK: call <3 x double> @llvm.[[TARGET]].nclamp.v3f64
 double3 test_clamp_double3(double3 p0, double3 p1) { return clamp(p0, p1,p1); }
-// CHECK: define [[FNATTR]] <4 x double> @_Z18test_clamp_double4
-// CHECK: call <4 x double> @llvm.[[FCLAMP]].v4f64
+// CHECK: define [[FNATTRS]] <4 x double> @_Z18test_clamp_double4
+// CHECK: call <4 x double> @llvm.[[TARGET]].nclamp.v4f64
 double4 test_clamp_double4(double4 p0, double4 p1) { return clamp(p0, p1,p1); }
diff --git a/llvm/include/llvm/IR/IntrinsicsDirectX.td 
b/llvm/include/llvm/IR/IntrinsicsDirectX.td
index e30d37f69f781e..f1c0e39f994e1d 100644
--- a/llvm/include/llvm/IR/IntrinsicsDirectX.td
+++ b/llvm/include/llvm/IR/IntrinsicsDirectX.td
@@ -40,8 +40,9 @@ def int_dx_cast_handle : Intrinsic<[llvm_any_ty], 
[llvm_any_ty]>;
 
 def int_dx_all : DefaultAttrsIntrinsic<[llvm_i1_ty], [llvm_any_ty], 
[IntrNoMem]>;
 def int_dx_any : DefaultAttrsIntrinsic<[llvm_i1_ty], [llvm_any_ty], 
[IntrNoMem]>;
-def int_dx_clamp : DefaultAttrsIntrinsic<[llvm_any_ty], [LLVMMatchType<0>, 
LLVMMatchType<0>, LLVMMatchType<0>], [IntrNoMem]>;
 def int_dx_uclamp : DefaultAttrsIntrinsic<[llvm_anyint_ty], [LLVMMatchType<0>, 
LLVMMatchType<0>, LLVMMatchType<0>], [IntrNoMem]>;
+def int_dx_sclamp : DefaultAttrsIntrinsic<[llvm_anyint_ty], [LLVMMatchType<0>, 
LLVMMatchType<0>, LLVMMatchType<0>], [IntrNoMem]>;
+def int_dx_nclamp : DefaultAttrsIntrinsic<[llvm_anyfloat_ty], 
[LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>], [IntrNoMem]>;
 def int_dx_cross : DefaultAttrsIntrinsic<[llvm_anyfloat_ty], 
[LLVMMatchType<0>, LLVMMatchType<0>], [IntrNoMem]>;
 def int_dx_saturate : DefaultAttrsIntrinsic<[llvm_anyfloat_ty], 
[LLVMMatchType<0>], [IntrNoMem]>;
 
diff --git a/llvm/include/llvm/IR/IntrinsicsSPIRV.td 
b/llvm/include/llvm/IR/IntrinsicsSPIRV.td
index b19d2a299a6eeb..c410fb3bf5985f 100644
--- a/llvm/include/llvm/IR/IntrinsicsSPIRV.td
+++ b/llvm/include/llvm/IR/IntrinsicsSPIRV.td
@@ -87,9 +87,9 @@ let TargetPrefix = "spv" in {
   def int_spv_wave_readlane : DefaultAttrsIntrinsic<[llvm_any_ty], 
[LLVMMatchType<0>, llvm_i32_ty], [IntrConvergent, IntrNoMem]>;
   def int_spv_sign : DefaultAttrsIntrinsic<[LLVMScalarOrSameVectorWidth<0, 
llvm_i32_ty>], [llvm_any_ty], [IntrNoMem]>;
   def int_spv_radians : DefaultAttrsIntrinsic<[LLVMMatchType<0>], 
[llvm_anyfloat_ty], [IntrNoMem]>;
-  def int_spv_uclamp : DefaultAttrsIntrinsic<[llvm_any_ty], [LLVMMatchType<0>, 
LLVMMatchType<0>, LLVMMatchType<0>], [IntrNoMem]>;
-  def int_spv_sclamp : DefaultAttrsIntrinsic<[llvm_any_ty], [LLVMMatchType<0>, 
LLVMMatchType<0>, LLVMMatchType<0>], [IntrNoMem]>;
-  def int_spv_fclamp : DefaultAttrsIntrinsic<[llvm_anyfloat_ty], 
[LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>], [IntrNoMem]>;
+  def int_spv_uclamp : DefaultAttrsIntrinsic<[llvm_anyint_ty], 
[LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>], [IntrNoMem]>;
+  def int_spv_sclamp : DefaultAttrsIntrinsic<[llvm_anyint_ty], 
[LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>], [IntrNoMem]>;
+  def int_spv_nclamp : DefaultAttrsIntrinsic<[llvm_anyfloat_ty], 
[LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>], [IntrNoMem]>;
 
   // Create resource handle given the binding information. Returns a 
   // type appropriate for the kind of resource given the set id, binding id,
diff --git a/llvm/lib/Target/DirectX/DXILIntrinsicExpansion.cpp 
b/llvm/lib/Target/DirectX/DXILIntrinsicExpansion.cpp
index fb5383b3514a5a..8908a1205fdd03 100644
--- a/llvm/lib/Target/DirectX/DXILIntrinsicExpansion.cpp
+++ b/llvm/lib/Target/DirectX/DXILIntrinsicExpansion.cpp
@@ -53,9 +53,10 @@ static bool isIntrinsicExpansion(Function &F) {
   case Intrinsic::pow:
   case Intrinsic::dx_all:
   case Intrinsic::dx_any:
-  case Intrinsic::dx_clamp:
   case Intrinsic::dx_cross:
   case Intrinsic::dx_uclamp:
+  case Intrinsic::dx_sclamp:
+  case Intrinsic::dx_nclamp:
   case Intrinsic::dx_degrees:
   case Intrinsic::dx_lerp:
   case Intrinsic::dx_length:
@@ -452,43 +453,35 @@ static Value *expandRadiansIntrinsic(CallInst *Orig) {
   return Builder.CreateFMul(X, PiOver180);
 }
 
-static Intrinsic::ID getMaxForClamp(Type *ElemTy,
-                                    Intrinsic::ID ClampIntrinsic) {
+static Intrinsic::ID getMaxForClamp(Intrinsic::ID ClampIntrinsic) {
   if (ClampIntrinsic == Intrinsic::dx_uclamp)
     return Intrinsic::umax;
-  assert(ClampIntrinsic == Intrinsic::dx_clamp);
-  if (ElemTy->isVectorTy())
-    ElemTy = ElemTy->getScalarType();
-  if (ElemTy->isIntegerTy())
+  if (ClampIntrinsic == Intrinsic::dx_sclamp)
     return Intrinsic::smax;
-  assert(ElemTy->isFloatingPointTy());
+  assert(ClampIntrinsic == Intrinsic::dx_nclamp);
   return Intrinsic::maxnum;
 }
 
-static Intrinsic::ID getMinForClamp(Type *ElemTy,
-                                    Intrinsic::ID ClampIntrinsic) {
+static Intrinsic::ID getMinForClamp(Intrinsic::ID ClampIntrinsic) {
   if (ClampIntrinsic == Intrinsic::dx_uclamp)
     return Intrinsic::umin;
-  assert(ClampIntrinsic == Intrinsic::dx_clamp);
-  if (ElemTy->isVectorTy())
-    ElemTy = ElemTy->getScalarType();
-  if (ElemTy->isIntegerTy())
+  if (ClampIntrinsic == Intrinsic::dx_sclamp)
     return Intrinsic::smin;
-  assert(ElemTy->isFloatingPointTy());
+  assert(ClampIntrinsic == Intrinsic::dx_nclamp);
   return Intrinsic::minnum;
 }
 
-static Value *expandClampIntrinsic(CallInst *Orig,
-                                   Intrinsic::ID ClampIntrinsic) {
-  Value *X = Orig->getOperand(0);
-  Value *Min = Orig->getOperand(1);
-  Value *Max = Orig->getOperand(2);
-  Type *Ty = X->getType();
+static Value* expandClampIntrinsic(CallInst* Orig,
+  Intrinsic::ID ClampIntrinsic) {
+  Value* X = Orig->getOperand(0);
+  Value* Min = Orig->getOperand(1);
+  Value* Max = Orig->getOperand(2);
+  Type* Ty = X->getType();
   IRBuilder<> Builder(Orig);
-  auto *MaxCall = Builder.CreateIntrinsic(
-      Ty, getMaxForClamp(Ty, ClampIntrinsic), {X, Min}, nullptr, "dx.max");
-  return Builder.CreateIntrinsic(Ty, getMinForClamp(Ty, ClampIntrinsic),
-                                 {MaxCall, Max}, nullptr, "dx.min");
+  auto* MaxCall = Builder.CreateIntrinsic(
+    Ty, getMaxForClamp(ClampIntrinsic), { X, Min }, nullptr, "dx.max");
+  return Builder.CreateIntrinsic(Ty, getMinForClamp(ClampIntrinsic),
+    { MaxCall, Max }, nullptr, "dx.min");
 }
 
 static Value *expandDegreesIntrinsic(CallInst *Orig) {
@@ -555,7 +548,8 @@ static bool expandIntrinsic(Function &F, CallInst *Orig) {
     Result = expandCrossIntrinsic(Orig);
     break;
   case Intrinsic::dx_uclamp:
-  case Intrinsic::dx_clamp:
+  case Intrinsic::dx_sclamp:
+  case Intrinsic::dx_nclamp:
     Result = expandClampIntrinsic(Orig, IntrinsicId);
     break;
   case Intrinsic::dx_degrees:
diff --git a/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp 
b/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
index ca668941d0231d..3a0f2fe74ce8df 100644
--- a/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
@@ -2559,8 +2559,8 @@ bool SPIRVInstructionSelector::selectIntrinsic(Register 
ResVReg,
   } break;
   case Intrinsic::spv_saturate:
     return selectSaturate(ResVReg, ResType, I);
-  case Intrinsic::spv_fclamp:
-    return selectExtInst(ResVReg, ResType, I, CL::fclamp, GL::FClamp);
+  case Intrinsic::spv_nclamp:
+    return selectExtInst(ResVReg, ResType, I, CL::fclamp, GL::NClamp);
   case Intrinsic::spv_uclamp:
     return selectExtInst(ResVReg, ResType, I, CL::u_clamp, GL::UClamp);
   case Intrinsic::spv_sclamp:
diff --git a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/clamp-vec.ll 
b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/clamp-vec.ll
index cd0111c399abf7..089b76c575807a 100644
--- a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/clamp-vec.ll
+++ b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/clamp-vec.ll
@@ -52,36 +52,36 @@ entry:
   ret <4 x i64> %0
 }
 
-; CHECK-LABEL: Begin function test_fclamp_v4half
-define noundef <4 x half> @test_fclamp_v4half(<4 x half> noundef %a, <4 x 
half> noundef %b, <4 x half> noundef %c) {
+; CHECK-LABEL: Begin function test_nclamp_v4half
+define noundef <4 x half> @test_nclamp_v4half(<4 x half> noundef %a, <4 x 
half> noundef %b, <4 x half> noundef %c) {
 entry:
   ; CHECK: %[[#vec4_f16_arg0:]] = OpFunctionParameter %[[#vec4_float_16]]
   ; CHECK: %[[#vec4_f16_arg1:]] = OpFunctionParameter %[[#vec4_float_16]]
   ; CHECK: %[[#vec4_f16_arg2:]] = OpFunctionParameter %[[#vec4_float_16]]
-  ; CHECK: %[[#]] = OpExtInst %[[#vec4_float_16]] %[[#op_ext]] FClamp 
%[[#vec4_f16_arg0]] %[[#vec4_f16_arg1]] %[[#vec4_f16_arg2]]
-  %0 = call <4 x half> @llvm.spv.fclamp.v4f16(<4 x half> %a, <4 x half> %b, <4 
x half> %c)
+  ; CHECK: %[[#]] = OpExtInst %[[#vec4_float_16]] %[[#op_ext]] NClamp 
%[[#vec4_f16_arg0]] %[[#vec4_f16_arg1]] %[[#vec4_f16_arg2]]
+  %0 = call <4 x half> @llvm.spv.nclamp.v4f16(<4 x half> %a, <4 x half> %b, <4 
x half> %c)
   ret <4 x half> %0
 }
 
-; CHECK-LABEL: Begin function test_fclamp_v4float
-define noundef <4 x float> @test_fclamp_v4float(<4 x float> noundef %a, <4 x 
float> noundef %b, <4 x float> noundef %c) {
+; CHECK-LABEL: Begin function test_nclamp_v4float
+define noundef <4 x float> @test_nclamp_v4float(<4 x float> noundef %a, <4 x 
float> noundef %b, <4 x float> noundef %c) {
 entry:
   ; CHECK: %[[#vec4_f32_arg0:]] = OpFunctionParameter %[[#vec4_float_32]]
   ; CHECK: %[[#vec4_f32_arg1:]] = OpFunctionParameter %[[#vec4_float_32]]
   ; CHECK: %[[#vec4_f32_arg2:]] = OpFunctionParameter %[[#vec4_float_32]]
-  ; CHECK: %[[#]] = OpExtInst %[[#vec4_float_32]] %[[#op_ext]] FClamp 
%[[#vec4_f32_arg0]] %[[#vec4_f32_arg1]] %[[#vec4_f32_arg2]]
-  %0 = call <4 x float> @llvm.spv.fclamp.v4f32(<4 x float> %a, <4 x float> %b, 
<4 x float> %c)
+  ; CHECK: %[[#]] = OpExtInst %[[#vec4_float_32]] %[[#op_ext]] NClamp 
%[[#vec4_f32_arg0]] %[[#vec4_f32_arg1]] %[[#vec4_f32_arg2]]
+  %0 = call <4 x float> @llvm.spv.nclamp.v4f32(<4 x float> %a, <4 x float> %b, 
<4 x float> %c)
   ret <4 x float> %0
 }
 
-; CHECK-LABEL: Begin function test_fclamp_v4double
-define noundef <4 x double> @test_fclamp_v4double(<4 x double> noundef %a, <4 
x double> noundef %b, <4 x double> noundef %c) {
+; CHECK-LABEL: Begin function test_nclamp_v4double
+define noundef <4 x double> @test_nclamp_v4double(<4 x double> noundef %a, <4 
x double> noundef %b, <4 x double> noundef %c) {
 entry:
   ; CHECK: %[[#vec4_f64_arg0:]] = OpFunctionParameter %[[#vec4_float_64]]
   ; CHECK: %[[#vec4_f64_arg1:]] = OpFunctionParameter %[[#vec4_float_64]]
   ; CHECK: %[[#vec4_f64_arg2:]] = OpFunctionParameter %[[#vec4_float_64]]
-  ; CHECK: %[[#]] = OpExtInst %[[#vec4_float_64]] %[[#op_ext]] FClamp 
%[[#vec4_f64_arg0]] %[[#vec4_f64_arg1]] %[[#vec4_f64_arg2]]
-  %0 = call <4 x double> @llvm.spv.fclamp.v4f64(<4 x double> %a, <4 x double> 
%b, <4 x double> %c)
+  ; CHECK: %[[#]] = OpExtInst %[[#vec4_float_64]] %[[#op_ext]] NClamp 
%[[#vec4_f64_arg0]] %[[#vec4_f64_arg1]] %[[#vec4_f64_arg2]]
+  %0 = call <4 x double> @llvm.spv.nclamp.v4f64(<4 x double> %a, <4 x double> 
%b, <4 x double> %c)
   ret <4 x double> %0
 }
 
@@ -118,9 +118,9 @@ entry:
   ret <4 x i64> %0
 }
 
-declare <4 x half> @llvm.spv.fclamp.v4f16(<4 x half>, <4 x half>, <4 x half>)
-declare <4 x float> @llvm.spv.fclamp.v4f32(<4 x float>, <4 x float>, <4 x 
float>)
-declare <4 x double> @llvm.spv.fclamp.v4f64(<4 x double>, <4 x double>, <4 x 
double>)
+declare <4 x half> @llvm.spv.nclamp.v4f16(<4 x half>, <4 x half>, <4 x half>)
+declare <4 x float> @llvm.spv.nclamp.v4f32(<4 x float>, <4 x float>, <4 x 
float>)
+declare <4 x double> @llvm.spv.nclamp.v4f64(<4 x double>, <4 x double>, <4 x 
double>)
 declare <4 x i16> @llvm.spv.sclamp.v4i16(<4 x i16>, <4 x i16>, <4 x i16>)
 declare <4 x i32> @llvm.spv.sclamp.v4i32(<4 x i32>, <4 x i32>, <4 x i32>)
 declare <4 x i64> @llvm.spv.sclamp.v4i64(<4 x i64>, <4 x i64>, <4 x i64>)
diff --git a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/clamp.ll 
b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/clamp.ll
index 61b89e16f2bd48..444ae41bbec282 100644
--- a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/clamp.ll
+++ b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/clamp.ll
@@ -44,36 +44,36 @@ entry:
   ret i64 %0
 }
 
-; CHECK-LABEL: Begin function test_fclamp_half
-define noundef half @test_fclamp_half(half noundef %a, half noundef %b, half 
noundef %c) {
+; CHECK-LABEL: Begin function test_nclamp_half
+define noundef half @test_nclamp_half(half noundef %a, half noundef %b, half 
noundef %c) {
 entry:
   ; CHECK: %[[#f16_arg0:]] = OpFunctionParameter %[[#float_16]]
   ; CHECK: %[[#f16_arg1:]] = OpFunctionParameter %[[#float_16]]
   ; CHECK: %[[#f16_arg2:]] = OpFunctionParameter %[[#float_16]]
-  ; CHECK: %[[#]] = OpExtInst %[[#float_16]] %[[#op_ext]] FClamp 
%[[#f16_arg0]] %[[#f16_arg1]] %[[#f16_arg2]]
-  %0 = call half @llvm.spv.fclamp.f16(half %a, half %b, half %c)
+  ; CHECK: %[[#]] = OpExtInst %[[#float_16]] %[[#op_ext]] NClamp 
%[[#f16_arg0]] %[[#f16_arg1]] %[[#f16_arg2]]
+  %0 = call half @llvm.spv.nclamp.f16(half %a, half %b, half %c)
   ret half %0
 }
 
-; CHECK-LABEL: Begin function test_fclamp_float
-define noundef float @test_fclamp_float(float noundef %a, float noundef %b, 
float noundef %c) {
+; CHECK-LABEL: Begin function test_nclamp_float
+define noundef float @test_nclamp_float(float noundef %a, float noundef %b, 
float noundef %c) {
 entry:
   ; CHECK: %[[#f32_arg0:]] = OpFunctionParameter %[[#float_32]]
   ; CHECK: %[[#f32_arg1:]] = OpFunctionParameter %[[#float_32]]
   ; CHECK: %[[#f32_arg2:]] = OpFunctionParameter %[[#float_32]]
-  ; CHECK: %[[#]] = OpExtInst %[[#float_32]] %[[#op_ext]] FClamp 
%[[#f32_arg0]] %[[#f32_arg1]] %[[#f32_arg2]]
-  %0 = call float @llvm.spv.fclamp.f32(float %a, float %b, float %c)
+  ; CHECK: %[[#]] = OpExtInst %[[#float_32]] %[[#op_ext]] NClamp 
%[[#f32_arg0]] %[[#f32_arg1]] %[[#f32_arg2]]
+  %0 = call float @llvm.spv.nclamp.f32(float %a, float %b, float %c)
   ret float %0
 }
 
-; CHECK-LABEL: Begin function test_fclamp_double
-define noundef double @test_fclamp_double(double noundef %a, double noundef 
%b, double noundef %c) {
+; CHECK-LABEL: Begin function test_nclamp_double
+define noundef double @test_nclamp_double(double noundef %a, double noundef 
%b, double noundef %c) {
 entry:
   ; CHECK: %[[#f64_arg0:]] = OpFunctionParameter %[[#float_64]]
   ; CHECK: %[[#f64_arg1:]] = OpFunctionParameter %[[#float_64]]
   ; CHECK: %[[#f64_arg2:]] = OpFunctionParameter %[[#float_64]]
-  ; CHECK: %[[#]] = OpExtInst %[[#float_64]] %[[#op_ext]] FClamp 
%[[#f64_arg0]] %[[#f64_arg1]] %[[#f64_arg2]]
-  %0 = call double @llvm.spv.fclamp.f64(double %a, double %b, double %c)
+  ; CHECK: %[[#]] = OpExtInst %[[#float_64]] %[[#op_ext]] NClamp 
%[[#f64_arg0]] %[[#f64_arg1]] %[[#f64_arg2]]
+  %0 = call double @llvm.spv.nclamp.f64(double %a, double %b, double %c)
   ret double %0
 }
 
@@ -110,9 +110,9 @@ entry:
   ret i64 %0
 }
 
-declare half @llvm.spv.fclamp.f16(half, half, half)
-declare float @llvm.spv.fclamp.f32(float, float, float)
-declare double @llvm.spv.fclamp.f64(double, double, double)
+declare half @llvm.spv.nclamp.f16(half, half, half)
+declare float @llvm.spv.nclamp.f32(float, float, float)
+declare double @llvm.spv.nclamp.f64(double, double, double)
 declare i16 @llvm.spv.sclamp.i16(i16, i16, i16)
 declare i32 @llvm.spv.sclamp.i32(i32, i32, i32)
 declare i64 @llvm.spv.sclamp.i64(i64, i64, i64)
diff --git a/llvm/test/CodeGen/SPIRV/opencl/clamp-vec.ll 
b/llvm/test/CodeGen/SPIRV/opencl/clamp-vec.ll
index 35f5559c46921e..8f6af7b5de1e97 100644
--- a/llvm/test/CodeGen/SPIRV/opencl/clamp-vec.ll
+++ b/llvm/test/CodeGen/SPIRV/opencl/clamp-vec.ll
@@ -54,36 +54,36 @@ entry:
   ret <4 x i64> %0
 }
 
-; CHECK-LABEL: Begin function test_fclamp_v4half
-define noundef <4 x half> @test_fclamp_v4half(<4 x half> noundef %a, <4 x 
half> noundef %b, <4 x half> noundef %c) {
+; CHECK-LABEL: Begin function test_nclamp_v4half
+define noundef <4 x half> @test_nclamp_v4half(<4 x half> noundef %a, <4 x 
half> noundef %b, <4 x half> noundef %c) {
 entry:
   ; CHECK: %[[#vec4_f16_arg0:]] = OpFunctionParameter %[[#vec4_float_16]]
   ; CHECK: %[[#vec4_f16_arg1:]] = OpFunctionParameter %[[#vec4_float_16]]
   ; CHECK: %[[#vec4_f16_arg2:]] = OpFunctionParameter %[[#vec4_float_16]]
   ; CHECK: %[[#]] = OpExtInst %[[#vec4_float_16]] %[[#op_ext]] fclamp 
%[[#vec4_f16_arg0]] %[[#vec4_f16_arg1]] %[[#vec4_f16_arg2]]
-  %0 = call <4 x half> @llvm.spv.fclamp.v4f16(<4 x half> %a, <4 x half> %b, <4 
x half> %c)
+  %0 = call <4 x half> @llvm.spv.nclamp.v4f16(<4 x half> %a, <4 x half> %b, <4 
x half> %c)
   ret <4 x half> %0
 }
 
-; CHECK-LABEL: Begin function test_fclamp_v4float
-define noundef <4 x float> @test_fclamp_v4float(<4 x float> noundef %a, <4 x 
float> noundef %b, <4 x float> noundef %c) {
+; CHECK-LABEL: Begin function test_nclamp_v4float
+define noundef <4 x float> @test_nclamp_v4float(<4 x float> noundef %a, <4 x 
float> noundef %b, <4 x float> noundef %c) {
 entry:
   ; CHECK: %[[#vec4_f32_arg0:]] = OpFunctionParameter %[[#vec4_float_32]]
   ; CHECK: %[[#vec4_f32_arg1:]] = OpFunctionParameter %[[#vec4_float_32]]
   ; CHECK: %[[#vec4_f32_arg2:]] = OpFunctionParameter %[[#vec4_float_32]]
   ; CHECK: %[[#]] = OpExtInst %[[#vec4_float_32]] %[[#op_ext]] fclamp 
%[[#vec4_f32_arg0]] %[[#vec4_f32_arg1]] %[[#vec4_f32_arg2]]
-  %0 = call <4 x float> @llvm.spv.fclamp.v4f32(<4 x float> %a, <4 x float> %b, 
<4 x float> %c)
+  %0 = call <4 x float> @llvm.spv.nclamp.v4f32(<4 x float> %a, <4 x float> %b, 
<4 x float> %c)
   ret <4 x float> %0
 }
 
-; CHECK-LABEL: Begin function test_fclamp_v4double
-define noundef <4 x double> @test_fclamp_v4double(<4 x double> noundef %a, <4 
x double> noundef %b, <4 x double> noundef %c) {
+; CHECK-LABEL: Begin function test_nclamp_v4double
+define noundef <4 x double> @test_nclamp_v4double(<4 x double> noundef %a, <4 
x double> noundef %b, <4 x double> noundef %c) {
 entry:
   ; CHECK: %[[#vec4_f64_arg0:]] = OpFunctionParameter %[[#vec4_float_64]]
   ; CHECK: %[[#vec4_f64_arg1:]] = OpFunctionParameter %[[#vec4_float_64]]
   ; CHECK: %[[#vec4_f64_arg2:]] = OpFunctionParameter %[[#vec4_float_64]]
   ; CHECK: %[[#]] = OpExtInst %[[#vec4_float_64]] %[[#op_ext]] fclamp 
%[[#vec4_f64_arg0]] %[[#vec4_f64_arg1]] %[[#vec4_f64_arg2]]
-  %0 = call <4 x double> @llvm.spv.fclamp.v4f64(<4 x double> %a, <4 x double> 
%b, <4 x double> %c)
+  %0 = call <4 x double> @llvm.spv.nclamp.v4f64(<4 x double> %a, <4 x double> 
%b, <4 x double> %c)
   ret <4 x double> %0
 }
 
@@ -120,9 +120,9 @@ entry:
   ret <4 x i64> %0
 }
 
-declare <4 x half> @llvm.spv.fclamp.v4f16(<4 x half>, <4 x half>, <4 x half>)
-declare <4 x float> @llvm.spv.fclamp.v4f32(<4 x float>, <4 x float>, <4 x 
float>)
-declare <4 x double> @llvm.spv.fclamp.v4f64(<4 x double>, <4 x double>, <4 x 
double>)
+declare <4 x half> @llvm.spv.nclamp.v4f16(<4 x half>, <4 x half>, <4 x half>)
+declare <4 x float> @llvm.spv.nclamp.v4f32(<4 x float>, <4 x float>, <4 x 
float>)
+declare <4 x double> @llvm.spv.nclamp.v4f64(<4 x double>, <4 x double>, <4 x 
double>)
 declare <4 x i16> @llvm.spv.sclamp.v4i16(<4 x i16>, <4 x i16>, <4 x i16>)
 declare <4 x i32> @llvm.spv.sclamp.v4i32(<4 x i32>, <4 x i32>, <4 x i32>)
 declare <4 x i64> @llvm.spv.sclamp.v4i64(<4 x i64>, <4 x i64>, <4 x i64>)
diff --git a/llvm/test/CodeGen/SPIRV/opencl/clamp.ll 
b/llvm/test/CodeGen/SPIRV/opencl/clamp.ll
index f6500442042cd9..8c6945e7bf9cfa 100644
--- a/llvm/test/CodeGen/SPIRV/opencl/clamp.ll
+++ b/llvm/test/CodeGen/SPIRV/opencl/clamp.ll
@@ -46,36 +46,36 @@ entry:
   ret i64 %0
 }
 
-; CHECK-LABEL: Begin function test_fclamp_half
-define noundef half @test_fclamp_half(half noundef %a, half noundef %b, half 
noundef %c) {
+; CHECK-LABEL: Begin function test_nclamp_half
+define noundef half @test_nclamp_half(half noundef %a, half noundef %b, half 
noundef %c) {
 entry:
   ; CHECK: %[[#f16_arg0:]] = OpFunctionParameter %[[#float_16]]
   ; CHECK: %[[#f16_arg1:]] = OpFunctionParameter %[[#float_16]]
   ; CHECK: %[[#f16_arg2:]] = OpFunctionParameter %[[#float_16]]
   ; CHECK: %[[#]] = OpExtInst %[[#float_16]] %[[#op_ext]] fclamp 
%[[#f16_arg0]] %[[#f16_arg1]] %[[#f16_arg2]]
-  %0 = call half @llvm.spv.fclamp.f16(half %a, half %b, half %c)
+  %0 = call half @llvm.spv.nclamp.f16(half %a, half %b, half %c)
   ret half %0
 }
 
-; CHECK-LABEL: Begin function test_fclamp_float
-define noundef float @test_fclamp_float(float noundef %a, float noundef %b, 
float noundef %c) {
+; CHECK-LABEL: Begin function test_nclamp_float
+define noundef float @test_nclamp_float(float noundef %a, float noundef %b, 
float noundef %c) {
 entry:
   ; CHECK: %[[#f32_arg0:]] = OpFunctionParameter %[[#float_32]]
   ; CHECK: %[[#f32_arg1:]] = OpFunctionParameter %[[#float_32]]
   ; CHECK: %[[#f32_arg2:]] = OpFunctionParameter %[[#float_32]]
   ; CHECK: %[[#]] = OpExtInst %[[#float_32]] %[[#op_ext]] fclamp 
%[[#f32_arg0]] %[[#f32_arg1]] %[[#f32_arg2]]
-  %0 = call float @llvm.spv.fclamp.f32(float %a, float %b, float %c)
+  %0 = call float @llvm.spv.nclamp.f32(float %a, float %b, float %c)
   ret float %0
 }
 
-; CHECK-LABEL: Begin function test_fclamp_double
-define noundef double @test_fclamp_double(double noundef %a, double noundef 
%b, double noundef %c) {
+; CHECK-LABEL: Begin function test_nclamp_double
+define noundef double @test_nclamp_double(double noundef %a, double noundef 
%b, double noundef %c) {
 entry:
   ; CHECK: %[[#f64_arg0:]] = OpFunctionParameter %[[#float_64]]
   ; CHECK: %[[#f64_arg1:]] = OpFunctionParameter %[[#float_64]]
   ; CHECK: %[[#f64_arg2:]] = OpFunctionParameter %[[#float_64]]
   ; CHECK: %[[#]] = OpExtInst %[[#float_64]] %[[#op_ext]] fclamp 
%[[#f64_arg0]] %[[#f64_arg1]] %[[#f64_arg2]]
-  %0 = call double @llvm.spv.fclamp.f64(double %a, double %b, double %c)
+  %0 = call double @llvm.spv.nclamp.f64(double %a, double %b, double %c)
   ret double %0
 }
 
@@ -112,9 +112,9 @@ entry:
   ret i64 %0
 }
 
-declare half @llvm.spv.fclamp.f16(half, half, half)
-declare float @llvm.spv.fclamp.f32(float, float, float)
-declare double @llvm.spv.fclamp.f64(double, double, double)
+declare half @llvm.spv.nclamp.f16(half, half, half)
+declare float @llvm.spv.nclamp.f32(float, float, float)
+declare double @llvm.spv.nclamp.f64(double, double, double)
 declare i16 @llvm.spv.sclamp.i16(i16, i16, i16)
 declare i32 @llvm.spv.sclamp.i32(i32, i32, i32)
 declare i64 @llvm.spv.sclamp.i64(i64, i64, i64)

>From f9b7e3022156072f5f1f799fa88c5eb40944253e Mon Sep 17 00:00:00 2001
From: Adam Yang <31109344+adam-y...@users.noreply.github.com>
Date: Thu, 24 Oct 2024 16:39:13 -0700
Subject: [PATCH 6/6] Formatting

---
 clang/lib/CodeGen/CGBuiltin.cpp               | 19 ++++++++-----------
 .../Target/DirectX/DXILIntrinsicExpansion.cpp | 18 +++++++++---------
 2 files changed, 17 insertions(+), 20 deletions(-)

diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp
index afa0bf04524903..19cefb988b5417 100644
--- a/clang/lib/CodeGen/CGBuiltin.cpp
+++ b/clang/lib/CodeGen/CGBuiltin.cpp
@@ -18656,29 +18656,26 @@ Value *CodeGenFunction::EmitHLSLBuiltinExpr(unsigned 
BuiltinID,
         "hlsl.any");
   }
   case Builtin::BI__builtin_hlsl_elementwise_clamp: {
-    Value* OpX = EmitScalarExpr(E->getArg(0));
-    Value* OpMin = EmitScalarExpr(E->getArg(1));
-    Value* OpMax = EmitScalarExpr(E->getArg(2));
+    Value *OpX = EmitScalarExpr(E->getArg(0));
+    Value *OpMin = EmitScalarExpr(E->getArg(1));
+    Value *OpMax = EmitScalarExpr(E->getArg(2));
 
     QualType Ty = E->getArg(0)->getType();
-    if (auto* VecTy = Ty->getAs<VectorType>())
+    if (auto *VecTy = Ty->getAs<VectorType>())
       Ty = VecTy->getElementType();
 
     Intrinsic::ID Intr;
     if (Ty->isFloatingType()) {
       Intr = CGM.getHLSLRuntime().getNClampIntrinsic();
-    }
-    else if (Ty->isUnsignedIntegerType()) {
+    } else if (Ty->isUnsignedIntegerType()) {
       Intr = CGM.getHLSLRuntime().getUClampIntrinsic();
-    }
-    else {
+    } else {
       assert(Ty->isSignedIntegerType());
       Intr = CGM.getHLSLRuntime().getSClampIntrinsic();
     }
     return Builder.CreateIntrinsic(
-      /*ReturnType=*/OpX->getType(),
-      Intr,
-      ArrayRef<Value*>{OpX, OpMin, OpMax}, nullptr, "hlsl.clamp");
+        /*ReturnType=*/OpX->getType(), Intr,
+        ArrayRef<Value *>{OpX, OpMin, OpMax}, nullptr, "hlsl.clamp");
   }
   case Builtin::BI__builtin_hlsl_cross: {
     Value *Op0 = EmitScalarExpr(E->getArg(0));
diff --git a/llvm/lib/Target/DirectX/DXILIntrinsicExpansion.cpp 
b/llvm/lib/Target/DirectX/DXILIntrinsicExpansion.cpp
index 8908a1205fdd03..d2bfca1fada559 100644
--- a/llvm/lib/Target/DirectX/DXILIntrinsicExpansion.cpp
+++ b/llvm/lib/Target/DirectX/DXILIntrinsicExpansion.cpp
@@ -471,17 +471,17 @@ static Intrinsic::ID getMinForClamp(Intrinsic::ID 
ClampIntrinsic) {
   return Intrinsic::minnum;
 }
 
-static Value* expandClampIntrinsic(CallInst* Orig,
-  Intrinsic::ID ClampIntrinsic) {
-  Value* X = Orig->getOperand(0);
-  Value* Min = Orig->getOperand(1);
-  Value* Max = Orig->getOperand(2);
-  Type* Ty = X->getType();
+static Value *expandClampIntrinsic(CallInst *Orig,
+                                   Intrinsic::ID ClampIntrinsic) {
+  Value *X = Orig->getOperand(0);
+  Value *Min = Orig->getOperand(1);
+  Value *Max = Orig->getOperand(2);
+  Type *Ty = X->getType();
   IRBuilder<> Builder(Orig);
-  auto* MaxCall = Builder.CreateIntrinsic(
-    Ty, getMaxForClamp(ClampIntrinsic), { X, Min }, nullptr, "dx.max");
+  auto *MaxCall = Builder.CreateIntrinsic(Ty, getMaxForClamp(ClampIntrinsic),
+                                          {X, Min}, nullptr, "dx.max");
   return Builder.CreateIntrinsic(Ty, getMinForClamp(ClampIntrinsic),
-    { MaxCall, Max }, nullptr, "dx.min");
+                                 {MaxCall, Max}, nullptr, "dx.min");
 }
 
 static Value *expandDegreesIntrinsic(CallInst *Orig) {

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