https://github.com/adam-yang created
https://github.com/llvm/llvm-project/pull/113394
Fixes #88052
- Added the following intrinsics:
- `int_spv_uclamp`
- `int_spv_sclamp`
- `int_spv_fclamp`
- Update the clamp.hlsl unit tests to include SPIRV
- Added the SPIRV specific tests
>From 8cf5032a5580b97c4c4965e577374f627fbe0643 Mon Sep 17 00:00:00 2001
From: Adam Yang <31109344+adam-y...@users.noreply.github.com>
Date: Mon, 14 Oct 2024 16:35:45 -0700
Subject: [PATCH 1/3] Added the intrinsics and modified the clang test
---
clang/lib/CodeGen/CGBuiltin.cpp | 25 ++-
clang/test/CodeGenHLSL/builtins/clamp.hlsl | 174 +++++++++---------
llvm/include/llvm/IR/IntrinsicsSPIRV.td | 3 +
.../Target/SPIRV/SPIRVInstructionSelector.cpp | 6 +
4 files changed, 122 insertions(+), 86 deletions(-)
diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp
index 1ad950798c2118..1087537ae4ee29 100644
--- a/clang/lib/CodeGen/CGBuiltin.cpp
+++ b/clang/lib/CodeGen/CGBuiltin.cpp
@@ -18665,10 +18665,27 @@ Value *CodeGenFunction::EmitHLSLBuiltinExpr(unsigned
BuiltinID,
if (auto *VecTy = Ty->getAs<VectorType>())
Ty = VecTy->getElementType();
IsUnsigned = Ty->isUnsignedIntegerType();
- return Builder.CreateIntrinsic(
- /*ReturnType=*/OpX->getType(),
- IsUnsigned ? Intrinsic::dx_uclamp : Intrinsic::dx_clamp,
- ArrayRef<Value *>{OpX, OpMin, OpMax}, nullptr, "dx.clamp");
+ switch (CGM.getTarget().getTriple().getArch()) {
+ case llvm::Triple::dxil: {
+ return Builder.CreateIntrinsic(
+ /*ReturnType=*/OpX->getType(),
+ IsUnsigned ? Intrinsic::dx_uclamp : Intrinsic::dx_clamp,
+ ArrayRef<Value *>{OpX, OpMin, OpMax}, nullptr, "dx.clamp");
+ } break;
+ case llvm::Triple::spirv: {
+ Intrinsic::ID Intr = Intrinsic::spv_sclamp;
+ if (Ty->isFloatingType()) {
+ Intr = Intrinsic::spv_fclamp;
+ } else if (IsUnsigned) {
+ Intr = Intrinsic::spv_uclamp;
+ }
+ return Builder.CreateIntrinsic(OpX->getType(), Intr,
+ ArrayRef<Value *>{OpX, OpMin, OpMax},
+ nullptr, "spv.clamp");
+ } break;
+ default:
+ llvm_unreachable("Intrinsic clamp not supported by target architecture");
+ }
}
case Builtin::BI__builtin_hlsl_cross: {
Value *Op0 = EmitScalarExpr(E->getArg(0));
diff --git a/clang/test/CodeGenHLSL/builtins/clamp.hlsl
b/clang/test/CodeGenHLSL/builtins/clamp.hlsl
index af8f6b9733a071..806e786ae70931 100644
--- a/clang/test/CodeGenHLSL/builtins/clamp.hlsl
+++ b/clang/test/CodeGenHLSL/builtins/clamp.hlsl
@@ -1,133 +1,143 @@
// RUN: %clang_cc1 -finclude-default-header -triple
dxil-pc-shadermodel6.3-library %s \
// RUN: -fnative-half-type -emit-llvm -disable-llvm-passes -o - | \
-// RUN: FileCheck %s --check-prefixes=CHECK,NATIVE_HALF
+// RUN: FileCheck %s --check-prefixes=CHECK,NATIVE_HALF \
+// RUN: -DSCLAMP="dx.clamp" -DUCLAMP="dx.uclamp" -DFCLAMP="dx.clamp"
-DFNATTR="noundef"
// RUN: %clang_cc1 -finclude-default-header -triple
dxil-pc-shadermodel6.3-library %s \
// RUN: -emit-llvm -disable-llvm-passes -o - | \
-// RUN: FileCheck %s --check-prefixes=CHECK,NO_HALF
+// RUN: FileCheck %s --check-prefixes=CHECK,NO_HALF \
+// RUN: -DSCLAMP="dx.clamp" -DUCLAMP="dx.uclamp" -DFCLAMP="dx.clamp"
-DFNATTR="noundef"
+// RUN: %clang_cc1 -finclude-default-header -triple
spirv-unknown-vulkan-compute %s \
+// RUN: -fnative-half-type -emit-llvm -disable-llvm-passes -o - | \
+// RUN: FileCheck %s --check-prefixes=CHECK,NATIVE_HALF \
+// RUN: -DSCLAMP="spv.sclamp" -DUCLAMP="spv.uclamp" -DFCLAMP="spv.fclamp"
-DFNATTR="spir_func noundef"
+// RUN: %clang_cc1 -finclude-default-header -triple
spirv-unknown-vulkan-compute %s \
+// RUN: -emit-llvm -disable-llvm-passes -o - | \
+// RUN: FileCheck %s --check-prefixes=CHECK,NO_HALF \
+// RUN: -DSCLAMP="spv.sclamp" -DUCLAMP="spv.uclamp" -DFCLAMP="spv.fclamp"
-DFNATTR="spir_func noundef"
#ifdef __HLSL_ENABLE_16_BIT
-// NATIVE_HALF-LABEL: define noundef i16 @_Z16test_clamp_short
-// NATIVE_HALF: call i16 @llvm.dx.clamp.i16(
+// NATIVE_HALF: define [[FNATTR]] i16 @_Z16test_clamp_short
+// NATIVE_HALF: call i16 @llvm.[[SCLAMP]].i16(
int16_t test_clamp_short(int16_t p0, int16_t p1) { return clamp(p0, p1,p1); }
-// NATIVE_HALF-LABEL: define noundef <2 x i16> @_Z17test_clamp_short2
-// NATIVE_HALF: call <2 x i16> @llvm.dx.clamp.v2i16(
+// NATIVE_HALF: define [[FNATTR]] <2 x i16> @_Z17test_clamp_short2
+// NATIVE_HALF: call <2 x i16> @llvm.[[SCLAMP]].v2i16(
int16_t2 test_clamp_short2(int16_t2 p0, int16_t2 p1) { return clamp(p0,
p1,p1); }
-// NATIVE_HALF-LABEL: define noundef <3 x i16> @_Z17test_clamp_short3
-// NATIVE_HALF: call <3 x i16> @llvm.dx.clamp.v3i16
+// NATIVE_HALF: define [[FNATTR]] <3 x i16> @_Z17test_clamp_short3
+// NATIVE_HALF: call <3 x i16> @llvm.[[SCLAMP]].v3i16
int16_t3 test_clamp_short3(int16_t3 p0, int16_t3 p1) { return clamp(p0,
p1,p1); }
-// NATIVE_HALF-LABEL: define noundef <4 x i16> @_Z17test_clamp_short4
-// NATIVE_HALF: call <4 x i16> @llvm.dx.clamp.v4i16
+// NATIVE_HALF: define [[FNATTR]] <4 x i16> @_Z17test_clamp_short4
+// NATIVE_HALF: call <4 x i16> @llvm.[[SCLAMP]].v4i16
int16_t4 test_clamp_short4(int16_t4 p0, int16_t4 p1) { return clamp(p0,
p1,p1); }
-// NATIVE_HALF-LABEL: define noundef i16 @_Z17test_clamp_ushort
-// NATIVE_HALF: call i16 @llvm.dx.uclamp.i16(
+// NATIVE_HALF: define [[FNATTR]] i16 @_Z17test_clamp_ushort
+// NATIVE_HALF: call i16 @llvm.[[UCLAMP]].i16(
uint16_t test_clamp_ushort(uint16_t p0, uint16_t p1) { return clamp(p0,
p1,p1); }
-// NATIVE_HALF-LABEL: define noundef <2 x i16> @_Z18test_clamp_ushort2
-// NATIVE_HALF: call <2 x i16> @llvm.dx.uclamp.v2i16
+// NATIVE_HALF: define [[FNATTR]] <2 x i16> @_Z18test_clamp_ushort2
+// NATIVE_HALF: call <2 x i16> @llvm.[[UCLAMP]].v2i16
uint16_t2 test_clamp_ushort2(uint16_t2 p0, uint16_t2 p1) { return clamp(p0,
p1,p1); }
-// NATIVE_HALF-LABEL: define noundef <3 x i16> @_Z18test_clamp_ushort3
-// NATIVE_HALF: call <3 x i16> @llvm.dx.uclamp.v3i16
+// NATIVE_HALF: define [[FNATTR]] <3 x i16> @_Z18test_clamp_ushort3
+// NATIVE_HALF: call <3 x i16> @llvm.[[UCLAMP]].v3i16
uint16_t3 test_clamp_ushort3(uint16_t3 p0, uint16_t3 p1) { return clamp(p0,
p1,p1); }
-// NATIVE_HALF-LABEL: define noundef <4 x i16> @_Z18test_clamp_ushort4
-// NATIVE_HALF: call <4 x i16> @llvm.dx.uclamp.v4i16
+// NATIVE_HALF: define [[FNATTR]] <4 x i16> @_Z18test_clamp_ushort4
+// NATIVE_HALF: call <4 x i16> @llvm.[[UCLAMP]].v4i16
uint16_t4 test_clamp_ushort4(uint16_t4 p0, uint16_t4 p1) { return clamp(p0,
p1,p1); }
#endif
-// CHECK-LABEL: define noundef i32 @_Z14test_clamp_int
-// CHECK: call i32 @llvm.dx.clamp.i32(
+// CHECK: define [[FNATTR]] i32 @_Z14test_clamp_int
+// CHECK: call i32 @llvm.[[SCLAMP]].i32(
int test_clamp_int(int p0, int p1) { return clamp(p0, p1,p1); }
-// CHECK-LABEL: define noundef <2 x i32> @_Z15test_clamp_int2
-// CHECK: call <2 x i32> @llvm.dx.clamp.v2i32
+// CHECK: define [[FNATTR]] <2 x i32> @_Z15test_clamp_int2
+// CHECK: call <2 x i32> @llvm.[[SCLAMP]].v2i32
int2 test_clamp_int2(int2 p0, int2 p1) { return clamp(p0, p1,p1); }
-// CHECK-LABEL: define noundef <3 x i32> @_Z15test_clamp_int3
-// CHECK: call <3 x i32> @llvm.dx.clamp.v3i32
+// CHECK: define [[FNATTR]] <3 x i32> @_Z15test_clamp_int3
+// CHECK: call <3 x i32> @llvm.[[SCLAMP]].v3i32
int3 test_clamp_int3(int3 p0, int3 p1) { return clamp(p0, p1,p1); }
-// CHECK-LABEL: define noundef <4 x i32> @_Z15test_clamp_int4
-// CHECK: call <4 x i32> @llvm.dx.clamp.v4i32
+// CHECK: define [[FNATTR]] <4 x i32> @_Z15test_clamp_int4
+// CHECK: call <4 x i32> @llvm.[[SCLAMP]].v4i32
int4 test_clamp_int4(int4 p0, int4 p1) { return clamp(p0, p1,p1); }
-// CHECK-LABEL: define noundef i32 @_Z15test_clamp_uint
-// CHECK: call i32 @llvm.dx.uclamp.i32(
+// CHECK: define [[FNATTR]] i32 @_Z15test_clamp_uint
+// CHECK: call i32 @llvm.[[UCLAMP]].i32(
int test_clamp_uint(uint p0, uint p1) { return clamp(p0, p1,p1); }
-// CHECK-LABEL: define noundef <2 x i32> @_Z16test_clamp_uint2
-// CHECK: call <2 x i32> @llvm.dx.uclamp.v2i32
+// CHECK: define [[FNATTR]] <2 x i32> @_Z16test_clamp_uint2
+// CHECK: call <2 x i32> @llvm.[[UCLAMP]].v2i32
uint2 test_clamp_uint2(uint2 p0, uint2 p1) { return clamp(p0, p1,p1); }
-// CHECK-LABEL: define noundef <3 x i32> @_Z16test_clamp_uint3
-// CHECK: call <3 x i32> @llvm.dx.uclamp.v3i32
+// CHECK: define [[FNATTR]] <3 x i32> @_Z16test_clamp_uint3
+// CHECK: call <3 x i32> @llvm.[[UCLAMP]].v3i32
uint3 test_clamp_uint3(uint3 p0, uint3 p1) { return clamp(p0, p1,p1); }
-// CHECK-LABEL: define noundef <4 x i32> @_Z16test_clamp_uint4
-// CHECK: call <4 x i32> @llvm.dx.uclamp.v4i32
+// CHECK: define [[FNATTR]] <4 x i32> @_Z16test_clamp_uint4
+// CHECK: call <4 x i32> @llvm.[[UCLAMP]].v4i32
uint4 test_clamp_uint4(uint4 p0, uint4 p1) { return clamp(p0, p1,p1); }
-// CHECK-LABEL: define noundef i64 @_Z15test_clamp_long
-// CHECK: call i64 @llvm.dx.clamp.i64(
+// CHECK: define [[FNATTR]] i64 @_Z15test_clamp_long
+// CHECK: call i64 @llvm.[[SCLAMP]].i64(
int64_t test_clamp_long(int64_t p0, int64_t p1) { return clamp(p0, p1,p1); }
-// CHECK-LABEL: define noundef <2 x i64> @_Z16test_clamp_long2
-// CHECK: call <2 x i64> @llvm.dx.clamp.v2i64
+// CHECK: define [[FNATTR]] <2 x i64> @_Z16test_clamp_long2
+// CHECK: call <2 x i64> @llvm.[[SCLAMP]].v2i64
int64_t2 test_clamp_long2(int64_t2 p0, int64_t2 p1) { return clamp(p0, p1,p1);
}
-// CHECK-LABEL: define noundef <3 x i64> @_Z16test_clamp_long3
-// CHECK: call <3 x i64> @llvm.dx.clamp.v3i64
+// CHECK: define [[FNATTR]] <3 x i64> @_Z16test_clamp_long3
+// CHECK: call <3 x i64> @llvm.[[SCLAMP]].v3i64
int64_t3 test_clamp_long3(int64_t3 p0, int64_t3 p1) { return clamp(p0, p1,p1);
}
-// CHECK-LABEL: define noundef <4 x i64> @_Z16test_clamp_long4
-// CHECK: call <4 x i64> @llvm.dx.clamp.v4i64
+// CHECK: define [[FNATTR]] <4 x i64> @_Z16test_clamp_long4
+// CHECK: call <4 x i64> @llvm.[[SCLAMP]].v4i64
int64_t4 test_clamp_long4(int64_t4 p0, int64_t4 p1) { return clamp(p0, p1,p1);
}
-// CHECK-LABEL: define noundef i64 @_Z16test_clamp_ulong
-// CHECK: call i64 @llvm.dx.uclamp.i64(
+// CHECK: define [[FNATTR]] i64 @_Z16test_clamp_ulong
+// CHECK: call i64 @llvm.[[UCLAMP]].i64(
uint64_t test_clamp_ulong(uint64_t p0, uint64_t p1) { return clamp(p0, p1,p1);
}
-// CHECK-LABEL: define noundef <2 x i64> @_Z17test_clamp_ulong2
-// CHECK: call <2 x i64> @llvm.dx.uclamp.v2i64
+// CHECK: define [[FNATTR]] <2 x i64> @_Z17test_clamp_ulong2
+// CHECK: call <2 x i64> @llvm.[[UCLAMP]].v2i64
uint64_t2 test_clamp_ulong2(uint64_t2 p0, uint64_t2 p1) { return clamp(p0,
p1,p1); }
-// CHECK-LABEL: define noundef <3 x i64> @_Z17test_clamp_ulong3
-// CHECK: call <3 x i64> @llvm.dx.uclamp.v3i64
+// CHECK: define [[FNATTR]] <3 x i64> @_Z17test_clamp_ulong3
+// CHECK: call <3 x i64> @llvm.[[UCLAMP]].v3i64
uint64_t3 test_clamp_ulong3(uint64_t3 p0, uint64_t3 p1) { return clamp(p0,
p1,p1); }
-// CHECK-LABEL: define noundef <4 x i64> @_Z17test_clamp_ulong4
-// CHECK: call <4 x i64> @llvm.dx.uclamp.v4i64
+// CHECK: define [[FNATTR]] <4 x i64> @_Z17test_clamp_ulong4
+// CHECK: call <4 x i64> @llvm.[[UCLAMP]].v4i64
uint64_t4 test_clamp_ulong4(uint64_t4 p0, uint64_t4 p1) { return clamp(p0,
p1,p1); }
-// NATIVE_HALF-LABEL: define noundef half @_Z15test_clamp_half
-// NATIVE_HALF: call half @llvm.dx.clamp.f16(
-// NO_HALF-LABEL: define noundef float @_Z15test_clamp_half
-// NO_HALF: call float @llvm.dx.clamp.f32(
+// NATIVE_HALF: define [[FNATTR]] half @_Z15test_clamp_half
+// NATIVE_HALF: call half @llvm.[[FCLAMP]].f16(
+// NO_HALF: define [[FNATTR]] float @_Z15test_clamp_half
+// NO_HALF: call float @llvm.[[FCLAMP]].f32(
half test_clamp_half(half p0, half p1) { return clamp(p0, p1,p1); }
-// NATIVE_HALF-LABEL: define noundef <2 x half> @_Z16test_clamp_half2
-// NATIVE_HALF: call <2 x half> @llvm.dx.clamp.v2f16
-// NO_HALF-LABEL: define noundef <2 x float> @_Z16test_clamp_half2
-// NO_HALF: call <2 x float> @llvm.dx.clamp.v2f32(
+// NATIVE_HALF: define [[FNATTR]] <2 x half> @_Z16test_clamp_half2
+// NATIVE_HALF: call <2 x half> @llvm.[[FCLAMP]].v2f16
+// NO_HALF: define [[FNATTR]] <2 x float> @_Z16test_clamp_half2
+// NO_HALF: call <2 x float> @llvm.[[FCLAMP]].v2f32(
half2 test_clamp_half2(half2 p0, half2 p1) { return clamp(p0, p1,p1); }
-// NATIVE_HALF-LABEL: define noundef <3 x half> @_Z16test_clamp_half3
-// NATIVE_HALF: call <3 x half> @llvm.dx.clamp.v3f16
-// NO_HALF-LABEL: define noundef <3 x float> @_Z16test_clamp_half3
-// NO_HALF: call <3 x float> @llvm.dx.clamp.v3f32(
+// NATIVE_HALF: define [[FNATTR]] <3 x half> @_Z16test_clamp_half3
+// NATIVE_HALF: call <3 x half> @llvm.[[FCLAMP]].v3f16
+// NO_HALF: define [[FNATTR]] <3 x float> @_Z16test_clamp_half3
+// NO_HALF: call <3 x float> @llvm.[[FCLAMP]].v3f32(
half3 test_clamp_half3(half3 p0, half3 p1) { return clamp(p0, p1,p1); }
-// NATIVE_HALF-LABEL: define noundef <4 x half> @_Z16test_clamp_half4
-// NATIVE_HALF: call <4 x half> @llvm.dx.clamp.v4f16
-// NO_HALF-LABEL: define noundef <4 x float> @_Z16test_clamp_half4
-// NO_HALF: call <4 x float> @llvm.dx.clamp.v4f32(
+// NATIVE_HALF: define [[FNATTR]] <4 x half> @_Z16test_clamp_half4
+// NATIVE_HALF: call <4 x half> @llvm.[[FCLAMP]].v4f16
+// NO_HALF: define [[FNATTR]] <4 x float> @_Z16test_clamp_half4
+// NO_HALF: call <4 x float> @llvm.[[FCLAMP]].v4f32(
half4 test_clamp_half4(half4 p0, half4 p1) { return clamp(p0, p1,p1); }
-// CHECK-LABEL: define noundef float @_Z16test_clamp_float
-// CHECK: call float @llvm.dx.clamp.f32(
+// CHECK: define [[FNATTR]] float @_Z16test_clamp_float
+// CHECK: call float @llvm.[[FCLAMP]].f32(
float test_clamp_float(float p0, float p1) { return clamp(p0, p1,p1); }
-// CHECK-LABEL: define noundef <2 x float> @_Z17test_clamp_float2
-// CHECK: call <2 x float> @llvm.dx.clamp.v2f32
+// CHECK: define [[FNATTR]] <2 x float> @_Z17test_clamp_float2
+// CHECK: call <2 x float> @llvm.[[FCLAMP]].v2f32
float2 test_clamp_float2(float2 p0, float2 p1) { return clamp(p0, p1,p1); }
-// CHECK-LABEL: define noundef <3 x float> @_Z17test_clamp_float3
-// CHECK: call <3 x float> @llvm.dx.clamp.v3f32
+// CHECK: define [[FNATTR]] <3 x float> @_Z17test_clamp_float3
+// CHECK: call <3 x float> @llvm.[[FCLAMP]].v3f32
float3 test_clamp_float3(float3 p0, float3 p1) { return clamp(p0, p1,p1); }
-// CHECK-LABEL: define noundef <4 x float> @_Z17test_clamp_float4
-// CHECK: call <4 x float> @llvm.dx.clamp.v4f32
+// CHECK: define [[FNATTR]] <4 x float> @_Z17test_clamp_float4
+// CHECK: call <4 x float> @llvm.[[FCLAMP]].v4f32
float4 test_clamp_float4(float4 p0, float4 p1) { return clamp(p0, p1,p1); }
-// CHECK-LABEL: define noundef double @_Z17test_clamp_double
-// CHECK: call double @llvm.dx.clamp.f64(
+// CHECK: define [[FNATTR]] double @_Z17test_clamp_double
+// CHECK: call double @llvm.[[FCLAMP]].f64(
double test_clamp_double(double p0, double p1) { return clamp(p0, p1,p1); }
-// CHECK-LABEL: define noundef <2 x double> @_Z18test_clamp_double2
-// CHECK: call <2 x double> @llvm.dx.clamp.v2f64
+// CHECK: define [[FNATTR]] <2 x double> @_Z18test_clamp_double2
+// CHECK: call <2 x double> @llvm.[[FCLAMP]].v2f64
double2 test_clamp_double2(double2 p0, double2 p1) { return clamp(p0, p1,p1); }
-// CHECK-LABEL: define noundef <3 x double> @_Z18test_clamp_double3
-// CHECK: call <3 x double> @llvm.dx.clamp.v3f64
+// CHECK: define [[FNATTR]] <3 x double> @_Z18test_clamp_double3
+// CHECK: call <3 x double> @llvm.[[FCLAMP]].v3f64
double3 test_clamp_double3(double3 p0, double3 p1) { return clamp(p0, p1,p1); }
-// CHECK-LABEL: define noundef <4 x double> @_Z18test_clamp_double4
-// CHECK: call <4 x double> @llvm.dx.clamp.v4f64
+// CHECK: define [[FNATTR]] <4 x double> @_Z18test_clamp_double4
+// CHECK: call <4 x double> @llvm.[[FCLAMP]].v4f64
double4 test_clamp_double4(double4 p0, double4 p1) { return clamp(p0, p1,p1); }
diff --git a/llvm/include/llvm/IR/IntrinsicsSPIRV.td
b/llvm/include/llvm/IR/IntrinsicsSPIRV.td
index 6df2eb156a0774..b19d2a299a6eeb 100644
--- a/llvm/include/llvm/IR/IntrinsicsSPIRV.td
+++ b/llvm/include/llvm/IR/IntrinsicsSPIRV.td
@@ -87,6 +87,9 @@ let TargetPrefix = "spv" in {
def int_spv_wave_readlane : DefaultAttrsIntrinsic<[llvm_any_ty],
[LLVMMatchType<0>, llvm_i32_ty], [IntrConvergent, IntrNoMem]>;
def int_spv_sign : DefaultAttrsIntrinsic<[LLVMScalarOrSameVectorWidth<0,
llvm_i32_ty>], [llvm_any_ty], [IntrNoMem]>;
def int_spv_radians : DefaultAttrsIntrinsic<[LLVMMatchType<0>],
[llvm_anyfloat_ty], [IntrNoMem]>;
+ def int_spv_uclamp : DefaultAttrsIntrinsic<[llvm_any_ty], [LLVMMatchType<0>,
LLVMMatchType<0>, LLVMMatchType<0>], [IntrNoMem]>;
+ def int_spv_sclamp : DefaultAttrsIntrinsic<[llvm_any_ty], [LLVMMatchType<0>,
LLVMMatchType<0>, LLVMMatchType<0>], [IntrNoMem]>;
+ def int_spv_fclamp : DefaultAttrsIntrinsic<[llvm_anyfloat_ty],
[LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>], [IntrNoMem]>;
// Create resource handle given the binding information. Returns a
// type appropriate for the kind of resource given the set id, binding id,
diff --git a/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
b/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
index d9377fe4b91a1a..ca668941d0231d 100644
--- a/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
@@ -2559,6 +2559,12 @@ bool SPIRVInstructionSelector::selectIntrinsic(Register
ResVReg,
} break;
case Intrinsic::spv_saturate:
return selectSaturate(ResVReg, ResType, I);
+ case Intrinsic::spv_fclamp:
+ return selectExtInst(ResVReg, ResType, I, CL::fclamp, GL::FClamp);
+ case Intrinsic::spv_uclamp:
+ return selectExtInst(ResVReg, ResType, I, CL::u_clamp, GL::UClamp);
+ case Intrinsic::spv_sclamp:
+ return selectExtInst(ResVReg, ResType, I, CL::s_clamp, GL::SClamp);
case Intrinsic::spv_wave_is_first_lane: {
SPIRVType *IntTy = GR.getOrCreateSPIRVIntegerType(32, I, TII);
return BuildMI(BB, I, I.getDebugLoc(),
>From 15897bacfdb71d277e1a74cc12cb3a5d80d6f949 Mon Sep 17 00:00:00 2001
From: Adam Yang <31109344+adam-y...@users.noreply.github.com>
Date: Tue, 22 Oct 2024 15:57:52 -0700
Subject: [PATCH 2/3] LLC tests
---
.../SPIRV/hlsl-intrinsics/clamp-vec.ll | 130 ++++++++++++++++++
.../CodeGen/SPIRV/hlsl-intrinsics/clamp.ll | 122 ++++++++++++++++
2 files changed, 252 insertions(+)
create mode 100644 llvm/test/CodeGen/SPIRV/hlsl-intrinsics/clamp-vec.ll
create mode 100644 llvm/test/CodeGen/SPIRV/hlsl-intrinsics/clamp.ll
diff --git a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/clamp-vec.ll
b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/clamp-vec.ll
new file mode 100644
index 00000000000000..6af5bf2fc1812b
--- /dev/null
+++ b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/clamp-vec.ll
@@ -0,0 +1,130 @@
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-unknown-unknown %s -o - |
FileCheck %s
+; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o -
-filetype=obj | spirv-val %}
+
+; CHECK-DAG: %[[#op_ext_glsl:]] = OpExtInstImport "GLSL.std.450"
+
+; CHECK-DAG: %[[#float_64:]] = OpTypeFloat 64
+; CHECK-DAG: %[[#float_32:]] = OpTypeFloat 32
+; CHECK-DAG: %[[#float_16:]] = OpTypeFloat 16
+
+; CHECK-DAG: %[[#int_64:]] = OpTypeInt 64
+; CHECK-DAG: %[[#int_32:]] = OpTypeInt 32
+; CHECK-DAG: %[[#int_16:]] = OpTypeInt 16
+
+; CHECK-DAG: %[[#vec4_float_64:]] = OpTypeVector %[[#float_64]] 4
+; CHECK-DAG: %[[#vec4_float_32:]] = OpTypeVector %[[#float_32]] 4
+; CHECK-DAG: %[[#vec4_float_16:]] = OpTypeVector %[[#float_16]] 4
+
+; CHECK-DAG: %[[#vec4_int_64:]] = OpTypeVector %[[#int_64]] 4
+; CHECK-DAG: %[[#vec4_int_32:]] = OpTypeVector %[[#int_32]] 4
+; CHECK-DAG: %[[#vec4_int_16:]] = OpTypeVector %[[#int_16]] 4
+
+; CHECK-LABEL: Begin function test_sclamp_v4i16
+define noundef <4 x i16> @test_sclamp_v4i16(<4 x i16> noundef %a, <4 x i16>
noundef %b, <4 x i16> noundef %c) {
+entry:
+ ; CHECK: %[[#vec4_i16_arg0:]] = OpFunctionParameter %[[#vec4_int_16]]
+ ; CHECK: %[[#vec4_i16_arg1:]] = OpFunctionParameter %[[#vec4_int_16]]
+ ; CHECK: %[[#vec4_i16_arg2:]] = OpFunctionParameter %[[#vec4_int_16]]
+ ; CHECK: %[[#]] = OpExtInst %[[#vec4_int_16]] %[[#op_ext_glsl]] SClamp
%[[#vec4_i16_arg0]] %[[#vec4_i16_arg1]] %[[#vec4_i16_arg2]]
+ %0 = call <4 x i16> @llvm.spv.sclamp.v4i16(<4 x i16> %a, <4 x i16> %b, <4 x
i16> %c)
+ ret <4 x i16> %0
+}
+
+; CHECK-LABEL: Begin function test_sclamp_v4i32
+define noundef <4 x i32> @test_sclamp_v4i32(<4 x i32> noundef %a, <4 x i32>
noundef %b, <4 x i32> noundef %c) {
+entry:
+ ; CHECK: %[[#vec4_i32_arg0:]] = OpFunctionParameter %[[#vec4_int_32]]
+ ; CHECK: %[[#vec4_i32_arg1:]] = OpFunctionParameter %[[#vec4_int_32]]
+ ; CHECK: %[[#vec4_i32_arg2:]] = OpFunctionParameter %[[#vec4_int_32]]
+ ; CHECK: %[[#]] = OpExtInst %[[#vec4_int_32]] %[[#op_ext_glsl]] SClamp
%[[#vec4_i32_arg0]] %[[#vec4_i32_arg1]] %[[#vec4_i32_arg2]]
+ %0 = call <4 x i32> @llvm.spv.sclamp.v4i32(<4 x i32> %a, <4 x i32> %b, <4 x
i32> %c)
+ ret <4 x i32> %0
+}
+
+; CHECK-LABEL: Begin function test_sclamp_v4i64
+define noundef <4 x i64> @test_sclamp_v4i64(<4 x i64> noundef %a, <4 x i64>
noundef %b, <4 x i64> noundef %c) {
+entry:
+ ; CHECK: %[[#vec4_i64_arg0:]] = OpFunctionParameter %[[#vec4_int_64]]
+ ; CHECK: %[[#vec4_i64_arg1:]] = OpFunctionParameter %[[#vec4_int_64]]
+ ; CHECK: %[[#vec4_i64_arg2:]] = OpFunctionParameter %[[#vec4_int_64]]
+ ; CHECK: %[[#]] = OpExtInst %[[#vec4_int_64]] %[[#op_ext_glsl]] SClamp
%[[#vec4_i64_arg0]] %[[#vec4_i64_arg1]] %[[#vec4_i64_arg2]]
+ %0 = call <4 x i64> @llvm.spv.sclamp.v4i64(<4 x i64> %a, <4 x i64> %b, <4 x
i64> %c)
+ ret <4 x i64> %0
+}
+
+; CHECK-LABEL: Begin function test_fclamp_v4half
+define noundef <4 x half> @test_fclamp_v4half(<4 x half> noundef %a, <4 x
half> noundef %b, <4 x half> noundef %c) {
+entry:
+ ; CHECK: %[[#vec4_f16_arg0:]] = OpFunctionParameter %[[#vec4_float_16]]
+ ; CHECK: %[[#vec4_f16_arg1:]] = OpFunctionParameter %[[#vec4_float_16]]
+ ; CHECK: %[[#vec4_f16_arg2:]] = OpFunctionParameter %[[#vec4_float_16]]
+ ; CHECK: %[[#]] = OpExtInst %[[#vec4_float_16]] %[[#op_ext_glsl]] FClamp
%[[#vec4_f16_arg0]] %[[#vec4_f16_arg1]] %[[#vec4_f16_arg2]]
+ %0 = call <4 x half> @llvm.spv.fclamp.v4f16(<4 x half> %a, <4 x half> %b, <4
x half> %c)
+ ret <4 x half> %0
+}
+
+; CHECK-LABEL: Begin function test_fclamp_v4float
+define noundef <4 x float> @test_fclamp_v4float(<4 x float> noundef %a, <4 x
float> noundef %b, <4 x float> noundef %c) {
+entry:
+ ; CHECK: %[[#vec4_f32_arg0:]] = OpFunctionParameter %[[#vec4_float_32]]
+ ; CHECK: %[[#vec4_f32_arg1:]] = OpFunctionParameter %[[#vec4_float_32]]
+ ; CHECK: %[[#vec4_f32_arg2:]] = OpFunctionParameter %[[#vec4_float_32]]
+ ; CHECK: %[[#]] = OpExtInst %[[#vec4_float_32]] %[[#op_ext_glsl]] FClamp
%[[#vec4_f32_arg0]] %[[#vec4_f32_arg1]] %[[#vec4_f32_arg2]]
+ %0 = call <4 x float> @llvm.spv.fclamp.v4f32(<4 x float> %a, <4 x float> %b,
<4 x float> %c)
+ ret <4 x float> %0
+}
+
+; CHECK-LABEL: Begin function test_fclamp_v4double
+define noundef <4 x double> @test_fclamp_v4double(<4 x double> noundef %a, <4
x double> noundef %b, <4 x double> noundef %c) {
+entry:
+ ; CHECK: %[[#vec4_f64_arg0:]] = OpFunctionParameter %[[#vec4_float_64]]
+ ; CHECK: %[[#vec4_f64_arg1:]] = OpFunctionParameter %[[#vec4_float_64]]
+ ; CHECK: %[[#vec4_f64_arg2:]] = OpFunctionParameter %[[#vec4_float_64]]
+ ; CHECK: %[[#]] = OpExtInst %[[#vec4_float_64]] %[[#op_ext_glsl]] FClamp
%[[#vec4_f64_arg0]] %[[#vec4_f64_arg1]] %[[#vec4_f64_arg2]]
+ %0 = call <4 x double> @llvm.spv.fclamp.v4f64(<4 x double> %a, <4 x double>
%b, <4 x double> %c)
+ ret <4 x double> %0
+}
+
+; CHECK-LABEL: Begin function test_uclamp_v4i16
+define noundef <4 x i16> @test_uclamp_v4i16(<4 x i16> noundef %a, <4 x i16>
noundef %b, <4 x i16> noundef %c) {
+entry:
+ ; CHECK: %[[#vec4_i16_arg0:]] = OpFunctionParameter %[[#vec4_int_16]]
+ ; CHECK: %[[#vec4_i16_arg1:]] = OpFunctionParameter %[[#vec4_int_16]]
+ ; CHECK: %[[#vec4_i16_arg2:]] = OpFunctionParameter %[[#vec4_int_16]]
+ ; CHECK: %[[#]] = OpExtInst %[[#vec4_int_16]] %[[#op_ext_glsl]] UClamp
%[[#vec4_i16_arg0]] %[[#vec4_i16_arg1]] %[[#vec4_i16_arg2]]
+ %0 = call <4 x i16> @llvm.spv.uclamp.v4i16(<4 x i16> %a, <4 x i16> %b, <4 x
i16> %c)
+ ret <4 x i16> %0
+}
+
+; CHECK-LABEL: Begin function test_uclamp_v4i32
+define noundef <4 x i32> @test_uclamp_v4i32(<4 x i32> noundef %a, <4 x i32>
noundef %b, <4 x i32> noundef %c) {
+entry:
+ ; CHECK: %[[#vec4_i32_arg0:]] = OpFunctionParameter %[[#vec4_int_32]]
+ ; CHECK: %[[#vec4_i32_arg1:]] = OpFunctionParameter %[[#vec4_int_32]]
+ ; CHECK: %[[#vec4_i32_arg2:]] = OpFunctionParameter %[[#vec4_int_32]]
+ ; CHECK: %[[#]] = OpExtInst %[[#vec4_int_32]] %[[#op_ext_glsl]] UClamp
%[[#vec4_i32_arg0]] %[[#vec4_i32_arg1]] %[[#vec4_i32_arg2]]
+ %0 = call <4 x i32> @llvm.spv.uclamp.v4i32(<4 x i32> %a, <4 x i32> %b, <4 x
i32> %c)
+ ret <4 x i32> %0
+}
+
+; CHECK-LABEL: Begin function test_uclamp_v4i64
+define noundef <4 x i64> @test_uclamp_v4i64(<4 x i64> noundef %a, <4 x i64>
noundef %b, <4 x i64> noundef %c) {
+entry:
+ ; CHECK: %[[#vec4_i64_arg0:]] = OpFunctionParameter %[[#vec4_int_64]]
+ ; CHECK: %[[#vec4_i64_arg1:]] = OpFunctionParameter %[[#vec4_int_64]]
+ ; CHECK: %[[#vec4_i64_arg2:]] = OpFunctionParameter %[[#vec4_int_64]]
+ ; CHECK: %[[#]] = OpExtInst %[[#vec4_int_64]] %[[#op_ext_glsl]] UClamp
%[[#vec4_i64_arg0]] %[[#vec4_i64_arg1]] %[[#vec4_i64_arg2]]
+ %0 = call <4 x i64> @llvm.spv.uclamp.v4i64(<4 x i64> %a, <4 x i64> %b, <4 x
i64> %c)
+ ret <4 x i64> %0
+}
+
+declare <4 x half> @llvm.spv.fclamp.v4f16(<4 x half>, <4 x half>, <4 x half>)
+declare <4 x float> @llvm.spv.fclamp.v4f32(<4 x float>, <4 x float>, <4 x
float>)
+declare <4 x double> @llvm.spv.fclamp.v4f64(<4 x double>, <4 x double>, <4 x
double>)
+declare <4 x i16> @llvm.spv.sclamp.v4i16(<4 x i16>, <4 x i16>, <4 x i16>)
+declare <4 x i32> @llvm.spv.sclamp.v4i32(<4 x i32>, <4 x i32>, <4 x i32>)
+declare <4 x i64> @llvm.spv.sclamp.v4i64(<4 x i64>, <4 x i64>, <4 x i64>)
+declare <4 x i16> @llvm.spv.uclamp.v4i16(<4 x i16>, <4 x i16>, <4 x i16>)
+declare <4 x i32> @llvm.spv.uclamp.v4i32(<4 x i32>, <4 x i32>, <4 x i32>)
+declare <4 x i64> @llvm.spv.uclamp.v4i64(<4 x i64>, <4 x i64>, <4 x i64>)
+
diff --git a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/clamp.ll
b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/clamp.ll
new file mode 100644
index 00000000000000..cdc58f7b742505
--- /dev/null
+++ b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/clamp.ll
@@ -0,0 +1,122 @@
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-unknown-unknown %s -o - |
FileCheck %s
+; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o -
-filetype=obj | spirv-val %}
+
+; CHECK-DAG: %[[#op_ext_glsl:]] = OpExtInstImport "GLSL.std.450"
+
+; CHECK-DAG: %[[#float_64:]] = OpTypeFloat 64
+; CHECK-DAG: %[[#float_32:]] = OpTypeFloat 32
+; CHECK-DAG: %[[#float_16:]] = OpTypeFloat 16
+
+; CHECK-DAG: %[[#int_64:]] = OpTypeInt 64
+; CHECK-DAG: %[[#int_32:]] = OpTypeInt 32
+; CHECK-DAG: %[[#int_16:]] = OpTypeInt 16
+
+; CHECK-LABEL: Begin function test_sclamp_i16
+define noundef i16 @test_sclamp_i16(i16 noundef %a, i16 noundef %b, i16
noundef %c) {
+entry:
+ ; CHECK: %[[#i16_arg0:]] = OpFunctionParameter %[[#int_16]]
+ ; CHECK: %[[#i16_arg1:]] = OpFunctionParameter %[[#int_16]]
+ ; CHECK: %[[#i16_arg2:]] = OpFunctionParameter %[[#int_16]]
+ ; CHECK: %[[#]] = OpExtInst %[[#int_16]] %[[#op_ext_glsl]] SClamp
%[[#i16_arg0]] %[[#i16_arg1]] %[[#i16_arg2]]
+ %0 = call i16 @llvm.spv.sclamp.i16(i16 %a, i16 %b, i16 %c)
+ ret i16 %0
+}
+
+; CHECK-LABEL: Begin function test_sclamp_i32
+define noundef i32 @test_sclamp_i32(i32 noundef %a, i32 noundef %b, i32
noundef %c) {
+entry:
+ ; CHECK: %[[#i32_arg0:]] = OpFunctionParameter %[[#int_32]]
+ ; CHECK: %[[#i32_arg1:]] = OpFunctionParameter %[[#int_32]]
+ ; CHECK: %[[#i32_arg2:]] = OpFunctionParameter %[[#int_32]]
+ ; CHECK: %[[#]] = OpExtInst %[[#int_32]] %[[#op_ext_glsl]] SClamp
%[[#i32_arg0]] %[[#i32_arg1]] %[[#i32_arg2]]
+ %0 = call i32 @llvm.spv.sclamp.i32(i32 %a, i32 %b, i32 %c)
+ ret i32 %0
+}
+
+; CHECK-LABEL: Begin function test_sclamp_i64
+define noundef i64 @test_sclamp_i64(i64 noundef %a, i64 noundef %b, i64
noundef %c) {
+entry:
+ ; CHECK: %[[#i64_arg0:]] = OpFunctionParameter %[[#int_64]]
+ ; CHECK: %[[#i64_arg1:]] = OpFunctionParameter %[[#int_64]]
+ ; CHECK: %[[#i64_arg2:]] = OpFunctionParameter %[[#int_64]]
+ ; CHECK: %[[#]] = OpExtInst %[[#int_64]] %[[#op_ext_glsl]] SClamp
%[[#i64_arg0]] %[[#i64_arg1]] %[[#i64_arg2]]
+ %0 = call i64 @llvm.spv.sclamp.i64(i64 %a, i64 %b, i64 %c)
+ ret i64 %0
+}
+
+; CHECK-LABEL: Begin function test_fclamp_half
+define noundef half @test_fclamp_half(half noundef %a, half noundef %b, half
noundef %c) {
+entry:
+ ; CHECK: %[[#f16_arg0:]] = OpFunctionParameter %[[#float_16]]
+ ; CHECK: %[[#f16_arg1:]] = OpFunctionParameter %[[#float_16]]
+ ; CHECK: %[[#f16_arg2:]] = OpFunctionParameter %[[#float_16]]
+ ; CHECK: %[[#]] = OpExtInst %[[#float_16]] %[[#op_ext_glsl]] FClamp
%[[#f16_arg0]] %[[#f16_arg1]] %[[#f16_arg2]]
+ %0 = call half @llvm.spv.fclamp.f16(half %a, half %b, half %c)
+ ret half %0
+}
+
+; CHECK-LABEL: Begin function test_fclamp_float
+define noundef float @test_fclamp_float(float noundef %a, float noundef %b,
float noundef %c) {
+entry:
+ ; CHECK: %[[#f32_arg0:]] = OpFunctionParameter %[[#float_32]]
+ ; CHECK: %[[#f32_arg1:]] = OpFunctionParameter %[[#float_32]]
+ ; CHECK: %[[#f32_arg2:]] = OpFunctionParameter %[[#float_32]]
+ ; CHECK: %[[#]] = OpExtInst %[[#float_32]] %[[#op_ext_glsl]] FClamp
%[[#f32_arg0]] %[[#f32_arg1]] %[[#f32_arg2]]
+ %0 = call float @llvm.spv.fclamp.f32(float %a, float %b, float %c)
+ ret float %0
+}
+
+; CHECK-LABEL: Begin function test_fclamp_double
+define noundef double @test_fclamp_double(double noundef %a, double noundef
%b, double noundef %c) {
+entry:
+ ; CHECK: %[[#f64_arg0:]] = OpFunctionParameter %[[#float_64]]
+ ; CHECK: %[[#f64_arg1:]] = OpFunctionParameter %[[#float_64]]
+ ; CHECK: %[[#f64_arg2:]] = OpFunctionParameter %[[#float_64]]
+ ; CHECK: %[[#]] = OpExtInst %[[#float_64]] %[[#op_ext_glsl]] FClamp
%[[#f64_arg0]] %[[#f64_arg1]] %[[#f64_arg2]]
+ %0 = call double @llvm.spv.fclamp.f64(double %a, double %b, double %c)
+ ret double %0
+}
+
+; CHECK-LABEL: Begin function test_uclamp_i16
+define noundef i16 @test_uclamp_i16(i16 noundef %a, i16 noundef %b, i16
noundef %c) {
+entry:
+ ; CHECK: %[[#i16_arg0:]] = OpFunctionParameter %[[#int_16]]
+ ; CHECK: %[[#i16_arg1:]] = OpFunctionParameter %[[#int_16]]
+ ; CHECK: %[[#i16_arg2:]] = OpFunctionParameter %[[#int_16]]
+ ; CHECK: %[[#]] = OpExtInst %[[#int_16]] %[[#op_ext_glsl]] UClamp
%[[#i16_arg0]] %[[#i16_arg1]] %[[#i16_arg2]]
+ %0 = call i16 @llvm.spv.uclamp.i16(i16 %a, i16 %b, i16 %c)
+ ret i16 %0
+}
+
+; CHECK-LABEL: Begin function test_uclamp_i32
+define noundef i32 @test_uclamp_i32(i32 noundef %a, i32 noundef %b, i32
noundef %c) {
+entry:
+ ; CHECK: %[[#i32_arg0:]] = OpFunctionParameter %[[#int_32]]
+ ; CHECK: %[[#i32_arg1:]] = OpFunctionParameter %[[#int_32]]
+ ; CHECK: %[[#i32_arg2:]] = OpFunctionParameter %[[#int_32]]
+ ; CHECK: %[[#]] = OpExtInst %[[#int_32]] %[[#op_ext_glsl]] UClamp
%[[#i32_arg0]] %[[#i32_arg1]] %[[#i32_arg2]]
+ %0 = call i32 @llvm.spv.uclamp.i32(i32 %a, i32 %b, i32 %c)
+ ret i32 %0
+}
+
+; CHECK-LABEL: Begin function test_uclamp_i64
+define noundef i64 @test_uclamp_i64(i64 noundef %a, i64 noundef %b, i64
noundef %c) {
+entry:
+ ; CHECK: %[[#i64_arg0:]] = OpFunctionParameter %[[#int_64]]
+ ; CHECK: %[[#i64_arg1:]] = OpFunctionParameter %[[#int_64]]
+ ; CHECK: %[[#i64_arg2:]] = OpFunctionParameter %[[#int_64]]
+ ; CHECK: %[[#]] = OpExtInst %[[#int_64]] %[[#op_ext_glsl]] UClamp
%[[#i64_arg0]] %[[#i64_arg1]] %[[#i64_arg2]]
+ %0 = call i64 @llvm.spv.uclamp.i64(i64 %a, i64 %b, i64 %c)
+ ret i64 %0
+}
+
+declare half @llvm.spv.fclamp.f16(half, half, half)
+declare float @llvm.spv.fclamp.f32(float, float, float)
+declare double @llvm.spv.fclamp.f64(double, double, double)
+declare i16 @llvm.spv.sclamp.i16(i16, i16, i16)
+declare i32 @llvm.spv.sclamp.i32(i32, i32, i32)
+declare i64 @llvm.spv.sclamp.i64(i64, i64, i64)
+declare i16 @llvm.spv.uclamp.i16(i16, i16, i16)
+declare i32 @llvm.spv.uclamp.i32(i32, i32, i32)
+declare i64 @llvm.spv.uclamp.i64(i64, i64, i64)
+
>From b669cfb5e90a34146cd5a3a8d8d9cb612e3e0fbf Mon Sep 17 00:00:00 2001
From: Adam Yang <31109344+adam-y...@users.noreply.github.com>
Date: Tue, 22 Oct 2024 16:02:27 -0700
Subject: [PATCH 3/3] Testing opencl too
---
.../SPIRV/hlsl-intrinsics/clamp-vec.ll | 20 +--
.../CodeGen/SPIRV/hlsl-intrinsics/clamp.ll | 20 +--
llvm/test/CodeGen/SPIRV/opencl/clamp-vec.ll | 132 ++++++++++++++++++
llvm/test/CodeGen/SPIRV/opencl/clamp.ll | 124 ++++++++++++++++
4 files changed, 276 insertions(+), 20 deletions(-)
create mode 100644 llvm/test/CodeGen/SPIRV/opencl/clamp-vec.ll
create mode 100644 llvm/test/CodeGen/SPIRV/opencl/clamp.ll
diff --git a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/clamp-vec.ll
b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/clamp-vec.ll
index 6af5bf2fc1812b..cd0111c399abf7 100644
--- a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/clamp-vec.ll
+++ b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/clamp-vec.ll
@@ -1,7 +1,7 @@
; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-unknown-unknown %s -o - |
FileCheck %s
; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o -
-filetype=obj | spirv-val %}
-; CHECK-DAG: %[[#op_ext_glsl:]] = OpExtInstImport "GLSL.std.450"
+; CHECK-DAG: %[[#op_ext:]] = OpExtInstImport "GLSL.std.450"
; CHECK-DAG: %[[#float_64:]] = OpTypeFloat 64
; CHECK-DAG: %[[#float_32:]] = OpTypeFloat 32
@@ -25,7 +25,7 @@ entry:
; CHECK: %[[#vec4_i16_arg0:]] = OpFunctionParameter %[[#vec4_int_16]]
; CHECK: %[[#vec4_i16_arg1:]] = OpFunctionParameter %[[#vec4_int_16]]
; CHECK: %[[#vec4_i16_arg2:]] = OpFunctionParameter %[[#vec4_int_16]]
- ; CHECK: %[[#]] = OpExtInst %[[#vec4_int_16]] %[[#op_ext_glsl]] SClamp
%[[#vec4_i16_arg0]] %[[#vec4_i16_arg1]] %[[#vec4_i16_arg2]]
+ ; CHECK: %[[#]] = OpExtInst %[[#vec4_int_16]] %[[#op_ext]] SClamp
%[[#vec4_i16_arg0]] %[[#vec4_i16_arg1]] %[[#vec4_i16_arg2]]
%0 = call <4 x i16> @llvm.spv.sclamp.v4i16(<4 x i16> %a, <4 x i16> %b, <4 x
i16> %c)
ret <4 x i16> %0
}
@@ -36,7 +36,7 @@ entry:
; CHECK: %[[#vec4_i32_arg0:]] = OpFunctionParameter %[[#vec4_int_32]]
; CHECK: %[[#vec4_i32_arg1:]] = OpFunctionParameter %[[#vec4_int_32]]
; CHECK: %[[#vec4_i32_arg2:]] = OpFunctionParameter %[[#vec4_int_32]]
- ; CHECK: %[[#]] = OpExtInst %[[#vec4_int_32]] %[[#op_ext_glsl]] SClamp
%[[#vec4_i32_arg0]] %[[#vec4_i32_arg1]] %[[#vec4_i32_arg2]]
+ ; CHECK: %[[#]] = OpExtInst %[[#vec4_int_32]] %[[#op_ext]] SClamp
%[[#vec4_i32_arg0]] %[[#vec4_i32_arg1]] %[[#vec4_i32_arg2]]
%0 = call <4 x i32> @llvm.spv.sclamp.v4i32(<4 x i32> %a, <4 x i32> %b, <4 x
i32> %c)
ret <4 x i32> %0
}
@@ -47,7 +47,7 @@ entry:
; CHECK: %[[#vec4_i64_arg0:]] = OpFunctionParameter %[[#vec4_int_64]]
; CHECK: %[[#vec4_i64_arg1:]] = OpFunctionParameter %[[#vec4_int_64]]
; CHECK: %[[#vec4_i64_arg2:]] = OpFunctionParameter %[[#vec4_int_64]]
- ; CHECK: %[[#]] = OpExtInst %[[#vec4_int_64]] %[[#op_ext_glsl]] SClamp
%[[#vec4_i64_arg0]] %[[#vec4_i64_arg1]] %[[#vec4_i64_arg2]]
+ ; CHECK: %[[#]] = OpExtInst %[[#vec4_int_64]] %[[#op_ext]] SClamp
%[[#vec4_i64_arg0]] %[[#vec4_i64_arg1]] %[[#vec4_i64_arg2]]
%0 = call <4 x i64> @llvm.spv.sclamp.v4i64(<4 x i64> %a, <4 x i64> %b, <4 x
i64> %c)
ret <4 x i64> %0
}
@@ -58,7 +58,7 @@ entry:
; CHECK: %[[#vec4_f16_arg0:]] = OpFunctionParameter %[[#vec4_float_16]]
; CHECK: %[[#vec4_f16_arg1:]] = OpFunctionParameter %[[#vec4_float_16]]
; CHECK: %[[#vec4_f16_arg2:]] = OpFunctionParameter %[[#vec4_float_16]]
- ; CHECK: %[[#]] = OpExtInst %[[#vec4_float_16]] %[[#op_ext_glsl]] FClamp
%[[#vec4_f16_arg0]] %[[#vec4_f16_arg1]] %[[#vec4_f16_arg2]]
+ ; CHECK: %[[#]] = OpExtInst %[[#vec4_float_16]] %[[#op_ext]] FClamp
%[[#vec4_f16_arg0]] %[[#vec4_f16_arg1]] %[[#vec4_f16_arg2]]
%0 = call <4 x half> @llvm.spv.fclamp.v4f16(<4 x half> %a, <4 x half> %b, <4
x half> %c)
ret <4 x half> %0
}
@@ -69,7 +69,7 @@ entry:
; CHECK: %[[#vec4_f32_arg0:]] = OpFunctionParameter %[[#vec4_float_32]]
; CHECK: %[[#vec4_f32_arg1:]] = OpFunctionParameter %[[#vec4_float_32]]
; CHECK: %[[#vec4_f32_arg2:]] = OpFunctionParameter %[[#vec4_float_32]]
- ; CHECK: %[[#]] = OpExtInst %[[#vec4_float_32]] %[[#op_ext_glsl]] FClamp
%[[#vec4_f32_arg0]] %[[#vec4_f32_arg1]] %[[#vec4_f32_arg2]]
+ ; CHECK: %[[#]] = OpExtInst %[[#vec4_float_32]] %[[#op_ext]] FClamp
%[[#vec4_f32_arg0]] %[[#vec4_f32_arg1]] %[[#vec4_f32_arg2]]
%0 = call <4 x float> @llvm.spv.fclamp.v4f32(<4 x float> %a, <4 x float> %b,
<4 x float> %c)
ret <4 x float> %0
}
@@ -80,7 +80,7 @@ entry:
; CHECK: %[[#vec4_f64_arg0:]] = OpFunctionParameter %[[#vec4_float_64]]
; CHECK: %[[#vec4_f64_arg1:]] = OpFunctionParameter %[[#vec4_float_64]]
; CHECK: %[[#vec4_f64_arg2:]] = OpFunctionParameter %[[#vec4_float_64]]
- ; CHECK: %[[#]] = OpExtInst %[[#vec4_float_64]] %[[#op_ext_glsl]] FClamp
%[[#vec4_f64_arg0]] %[[#vec4_f64_arg1]] %[[#vec4_f64_arg2]]
+ ; CHECK: %[[#]] = OpExtInst %[[#vec4_float_64]] %[[#op_ext]] FClamp
%[[#vec4_f64_arg0]] %[[#vec4_f64_arg1]] %[[#vec4_f64_arg2]]
%0 = call <4 x double> @llvm.spv.fclamp.v4f64(<4 x double> %a, <4 x double>
%b, <4 x double> %c)
ret <4 x double> %0
}
@@ -91,7 +91,7 @@ entry:
; CHECK: %[[#vec4_i16_arg0:]] = OpFunctionParameter %[[#vec4_int_16]]
; CHECK: %[[#vec4_i16_arg1:]] = OpFunctionParameter %[[#vec4_int_16]]
; CHECK: %[[#vec4_i16_arg2:]] = OpFunctionParameter %[[#vec4_int_16]]
- ; CHECK: %[[#]] = OpExtInst %[[#vec4_int_16]] %[[#op_ext_glsl]] UClamp
%[[#vec4_i16_arg0]] %[[#vec4_i16_arg1]] %[[#vec4_i16_arg2]]
+ ; CHECK: %[[#]] = OpExtInst %[[#vec4_int_16]] %[[#op_ext]] UClamp
%[[#vec4_i16_arg0]] %[[#vec4_i16_arg1]] %[[#vec4_i16_arg2]]
%0 = call <4 x i16> @llvm.spv.uclamp.v4i16(<4 x i16> %a, <4 x i16> %b, <4 x
i16> %c)
ret <4 x i16> %0
}
@@ -102,7 +102,7 @@ entry:
; CHECK: %[[#vec4_i32_arg0:]] = OpFunctionParameter %[[#vec4_int_32]]
; CHECK: %[[#vec4_i32_arg1:]] = OpFunctionParameter %[[#vec4_int_32]]
; CHECK: %[[#vec4_i32_arg2:]] = OpFunctionParameter %[[#vec4_int_32]]
- ; CHECK: %[[#]] = OpExtInst %[[#vec4_int_32]] %[[#op_ext_glsl]] UClamp
%[[#vec4_i32_arg0]] %[[#vec4_i32_arg1]] %[[#vec4_i32_arg2]]
+ ; CHECK: %[[#]] = OpExtInst %[[#vec4_int_32]] %[[#op_ext]] UClamp
%[[#vec4_i32_arg0]] %[[#vec4_i32_arg1]] %[[#vec4_i32_arg2]]
%0 = call <4 x i32> @llvm.spv.uclamp.v4i32(<4 x i32> %a, <4 x i32> %b, <4 x
i32> %c)
ret <4 x i32> %0
}
@@ -113,7 +113,7 @@ entry:
; CHECK: %[[#vec4_i64_arg0:]] = OpFunctionParameter %[[#vec4_int_64]]
; CHECK: %[[#vec4_i64_arg1:]] = OpFunctionParameter %[[#vec4_int_64]]
; CHECK: %[[#vec4_i64_arg2:]] = OpFunctionParameter %[[#vec4_int_64]]
- ; CHECK: %[[#]] = OpExtInst %[[#vec4_int_64]] %[[#op_ext_glsl]] UClamp
%[[#vec4_i64_arg0]] %[[#vec4_i64_arg1]] %[[#vec4_i64_arg2]]
+ ; CHECK: %[[#]] = OpExtInst %[[#vec4_int_64]] %[[#op_ext]] UClamp
%[[#vec4_i64_arg0]] %[[#vec4_i64_arg1]] %[[#vec4_i64_arg2]]
%0 = call <4 x i64> @llvm.spv.uclamp.v4i64(<4 x i64> %a, <4 x i64> %b, <4 x
i64> %c)
ret <4 x i64> %0
}
diff --git a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/clamp.ll
b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/clamp.ll
index cdc58f7b742505..61b89e16f2bd48 100644
--- a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/clamp.ll
+++ b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/clamp.ll
@@ -1,7 +1,7 @@
; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-unknown-unknown %s -o - |
FileCheck %s
; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o -
-filetype=obj | spirv-val %}
-; CHECK-DAG: %[[#op_ext_glsl:]] = OpExtInstImport "GLSL.std.450"
+; CHECK-DAG: %[[#op_ext:]] = OpExtInstImport "GLSL.std.450"
; CHECK-DAG: %[[#float_64:]] = OpTypeFloat 64
; CHECK-DAG: %[[#float_32:]] = OpTypeFloat 32
@@ -17,7 +17,7 @@ entry:
; CHECK: %[[#i16_arg0:]] = OpFunctionParameter %[[#int_16]]
; CHECK: %[[#i16_arg1:]] = OpFunctionParameter %[[#int_16]]
; CHECK: %[[#i16_arg2:]] = OpFunctionParameter %[[#int_16]]
- ; CHECK: %[[#]] = OpExtInst %[[#int_16]] %[[#op_ext_glsl]] SClamp
%[[#i16_arg0]] %[[#i16_arg1]] %[[#i16_arg2]]
+ ; CHECK: %[[#]] = OpExtInst %[[#int_16]] %[[#op_ext]] SClamp %[[#i16_arg0]]
%[[#i16_arg1]] %[[#i16_arg2]]
%0 = call i16 @llvm.spv.sclamp.i16(i16 %a, i16 %b, i16 %c)
ret i16 %0
}
@@ -28,7 +28,7 @@ entry:
; CHECK: %[[#i32_arg0:]] = OpFunctionParameter %[[#int_32]]
; CHECK: %[[#i32_arg1:]] = OpFunctionParameter %[[#int_32]]
; CHECK: %[[#i32_arg2:]] = OpFunctionParameter %[[#int_32]]
- ; CHECK: %[[#]] = OpExtInst %[[#int_32]] %[[#op_ext_glsl]] SClamp
%[[#i32_arg0]] %[[#i32_arg1]] %[[#i32_arg2]]
+ ; CHECK: %[[#]] = OpExtInst %[[#int_32]] %[[#op_ext]] SClamp %[[#i32_arg0]]
%[[#i32_arg1]] %[[#i32_arg2]]
%0 = call i32 @llvm.spv.sclamp.i32(i32 %a, i32 %b, i32 %c)
ret i32 %0
}
@@ -39,7 +39,7 @@ entry:
; CHECK: %[[#i64_arg0:]] = OpFunctionParameter %[[#int_64]]
; CHECK: %[[#i64_arg1:]] = OpFunctionParameter %[[#int_64]]
; CHECK: %[[#i64_arg2:]] = OpFunctionParameter %[[#int_64]]
- ; CHECK: %[[#]] = OpExtInst %[[#int_64]] %[[#op_ext_glsl]] SClamp
%[[#i64_arg0]] %[[#i64_arg1]] %[[#i64_arg2]]
+ ; CHECK: %[[#]] = OpExtInst %[[#int_64]] %[[#op_ext]] SClamp %[[#i64_arg0]]
%[[#i64_arg1]] %[[#i64_arg2]]
%0 = call i64 @llvm.spv.sclamp.i64(i64 %a, i64 %b, i64 %c)
ret i64 %0
}
@@ -50,7 +50,7 @@ entry:
; CHECK: %[[#f16_arg0:]] = OpFunctionParameter %[[#float_16]]
; CHECK: %[[#f16_arg1:]] = OpFunctionParameter %[[#float_16]]
; CHECK: %[[#f16_arg2:]] = OpFunctionParameter %[[#float_16]]
- ; CHECK: %[[#]] = OpExtInst %[[#float_16]] %[[#op_ext_glsl]] FClamp
%[[#f16_arg0]] %[[#f16_arg1]] %[[#f16_arg2]]
+ ; CHECK: %[[#]] = OpExtInst %[[#float_16]] %[[#op_ext]] FClamp
%[[#f16_arg0]] %[[#f16_arg1]] %[[#f16_arg2]]
%0 = call half @llvm.spv.fclamp.f16(half %a, half %b, half %c)
ret half %0
}
@@ -61,7 +61,7 @@ entry:
; CHECK: %[[#f32_arg0:]] = OpFunctionParameter %[[#float_32]]
; CHECK: %[[#f32_arg1:]] = OpFunctionParameter %[[#float_32]]
; CHECK: %[[#f32_arg2:]] = OpFunctionParameter %[[#float_32]]
- ; CHECK: %[[#]] = OpExtInst %[[#float_32]] %[[#op_ext_glsl]] FClamp
%[[#f32_arg0]] %[[#f32_arg1]] %[[#f32_arg2]]
+ ; CHECK: %[[#]] = OpExtInst %[[#float_32]] %[[#op_ext]] FClamp
%[[#f32_arg0]] %[[#f32_arg1]] %[[#f32_arg2]]
%0 = call float @llvm.spv.fclamp.f32(float %a, float %b, float %c)
ret float %0
}
@@ -72,7 +72,7 @@ entry:
; CHECK: %[[#f64_arg0:]] = OpFunctionParameter %[[#float_64]]
; CHECK: %[[#f64_arg1:]] = OpFunctionParameter %[[#float_64]]
; CHECK: %[[#f64_arg2:]] = OpFunctionParameter %[[#float_64]]
- ; CHECK: %[[#]] = OpExtInst %[[#float_64]] %[[#op_ext_glsl]] FClamp
%[[#f64_arg0]] %[[#f64_arg1]] %[[#f64_arg2]]
+ ; CHECK: %[[#]] = OpExtInst %[[#float_64]] %[[#op_ext]] FClamp
%[[#f64_arg0]] %[[#f64_arg1]] %[[#f64_arg2]]
%0 = call double @llvm.spv.fclamp.f64(double %a, double %b, double %c)
ret double %0
}
@@ -83,7 +83,7 @@ entry:
; CHECK: %[[#i16_arg0:]] = OpFunctionParameter %[[#int_16]]
; CHECK: %[[#i16_arg1:]] = OpFunctionParameter %[[#int_16]]
; CHECK: %[[#i16_arg2:]] = OpFunctionParameter %[[#int_16]]
- ; CHECK: %[[#]] = OpExtInst %[[#int_16]] %[[#op_ext_glsl]] UClamp
%[[#i16_arg0]] %[[#i16_arg1]] %[[#i16_arg2]]
+ ; CHECK: %[[#]] = OpExtInst %[[#int_16]] %[[#op_ext]] UClamp %[[#i16_arg0]]
%[[#i16_arg1]] %[[#i16_arg2]]
%0 = call i16 @llvm.spv.uclamp.i16(i16 %a, i16 %b, i16 %c)
ret i16 %0
}
@@ -94,7 +94,7 @@ entry:
; CHECK: %[[#i32_arg0:]] = OpFunctionParameter %[[#int_32]]
; CHECK: %[[#i32_arg1:]] = OpFunctionParameter %[[#int_32]]
; CHECK: %[[#i32_arg2:]] = OpFunctionParameter %[[#int_32]]
- ; CHECK: %[[#]] = OpExtInst %[[#int_32]] %[[#op_ext_glsl]] UClamp
%[[#i32_arg0]] %[[#i32_arg1]] %[[#i32_arg2]]
+ ; CHECK: %[[#]] = OpExtInst %[[#int_32]] %[[#op_ext]] UClamp %[[#i32_arg0]]
%[[#i32_arg1]] %[[#i32_arg2]]
%0 = call i32 @llvm.spv.uclamp.i32(i32 %a, i32 %b, i32 %c)
ret i32 %0
}
@@ -105,7 +105,7 @@ entry:
; CHECK: %[[#i64_arg0:]] = OpFunctionParameter %[[#int_64]]
; CHECK: %[[#i64_arg1:]] = OpFunctionParameter %[[#int_64]]
; CHECK: %[[#i64_arg2:]] = OpFunctionParameter %[[#int_64]]
- ; CHECK: %[[#]] = OpExtInst %[[#int_64]] %[[#op_ext_glsl]] UClamp
%[[#i64_arg0]] %[[#i64_arg1]] %[[#i64_arg2]]
+ ; CHECK: %[[#]] = OpExtInst %[[#int_64]] %[[#op_ext]] UClamp %[[#i64_arg0]]
%[[#i64_arg1]] %[[#i64_arg2]]
%0 = call i64 @llvm.spv.uclamp.i64(i64 %a, i64 %b, i64 %c)
ret i64 %0
}
diff --git a/llvm/test/CodeGen/SPIRV/opencl/clamp-vec.ll
b/llvm/test/CodeGen/SPIRV/opencl/clamp-vec.ll
new file mode 100644
index 00000000000000..35f5559c46921e
--- /dev/null
+++ b/llvm/test/CodeGen/SPIRV/opencl/clamp-vec.ll
@@ -0,0 +1,132 @@
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv64-unknown-unknown %s -o -
| FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown %s -o -
| FileCheck %s
+; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o -
-filetype=obj | spirv-val %}
+; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv32-unknown-unknown %s -o -
-filetype=obj | spirv-val %}
+
+; CHECK-DAG: %[[#op_ext:]] = OpExtInstImport "OpenCL.std"
+
+; CHECK-DAG: %[[#float_64:]] = OpTypeFloat 64
+; CHECK-DAG: %[[#float_32:]] = OpTypeFloat 32
+; CHECK-DAG: %[[#float_16:]] = OpTypeFloat 16
+
+; CHECK-DAG: %[[#int_64:]] = OpTypeInt 64
+; CHECK-DAG: %[[#int_32:]] = OpTypeInt 32
+; CHECK-DAG: %[[#int_16:]] = OpTypeInt 16
+
+; CHECK-DAG: %[[#vec4_float_64:]] = OpTypeVector %[[#float_64]] 4
+; CHECK-DAG: %[[#vec4_float_32:]] = OpTypeVector %[[#float_32]] 4
+; CHECK-DAG: %[[#vec4_float_16:]] = OpTypeVector %[[#float_16]] 4
+
+; CHECK-DAG: %[[#vec4_int_64:]] = OpTypeVector %[[#int_64]] 4
+; CHECK-DAG: %[[#vec4_int_32:]] = OpTypeVector %[[#int_32]] 4
+; CHECK-DAG: %[[#vec4_int_16:]] = OpTypeVector %[[#int_16]] 4
+
+; CHECK-LABEL: Begin function test_sclamp_v4i16
+define noundef <4 x i16> @test_sclamp_v4i16(<4 x i16> noundef %a, <4 x i16>
noundef %b, <4 x i16> noundef %c) {
+entry:
+ ; CHECK: %[[#vec4_i16_arg0:]] = OpFunctionParameter %[[#vec4_int_16]]
+ ; CHECK: %[[#vec4_i16_arg1:]] = OpFunctionParameter %[[#vec4_int_16]]
+ ; CHECK: %[[#vec4_i16_arg2:]] = OpFunctionParameter %[[#vec4_int_16]]
+ ; CHECK: %[[#]] = OpExtInst %[[#vec4_int_16]] %[[#op_ext]] s_clamp
%[[#vec4_i16_arg0]] %[[#vec4_i16_arg1]] %[[#vec4_i16_arg2]]
+ %0 = call <4 x i16> @llvm.spv.sclamp.v4i16(<4 x i16> %a, <4 x i16> %b, <4 x
i16> %c)
+ ret <4 x i16> %0
+}
+
+; CHECK-LABEL: Begin function test_sclamp_v4i32
+define noundef <4 x i32> @test_sclamp_v4i32(<4 x i32> noundef %a, <4 x i32>
noundef %b, <4 x i32> noundef %c) {
+entry:
+ ; CHECK: %[[#vec4_i32_arg0:]] = OpFunctionParameter %[[#vec4_int_32]]
+ ; CHECK: %[[#vec4_i32_arg1:]] = OpFunctionParameter %[[#vec4_int_32]]
+ ; CHECK: %[[#vec4_i32_arg2:]] = OpFunctionParameter %[[#vec4_int_32]]
+ ; CHECK: %[[#]] = OpExtInst %[[#vec4_int_32]] %[[#op_ext]] s_clamp
%[[#vec4_i32_arg0]] %[[#vec4_i32_arg1]] %[[#vec4_i32_arg2]]
+ %0 = call <4 x i32> @llvm.spv.sclamp.v4i32(<4 x i32> %a, <4 x i32> %b, <4 x
i32> %c)
+ ret <4 x i32> %0
+}
+
+; CHECK-LABEL: Begin function test_sclamp_v4i64
+define noundef <4 x i64> @test_sclamp_v4i64(<4 x i64> noundef %a, <4 x i64>
noundef %b, <4 x i64> noundef %c) {
+entry:
+ ; CHECK: %[[#vec4_i64_arg0:]] = OpFunctionParameter %[[#vec4_int_64]]
+ ; CHECK: %[[#vec4_i64_arg1:]] = OpFunctionParameter %[[#vec4_int_64]]
+ ; CHECK: %[[#vec4_i64_arg2:]] = OpFunctionParameter %[[#vec4_int_64]]
+ ; CHECK: %[[#]] = OpExtInst %[[#vec4_int_64]] %[[#op_ext]] s_clamp
%[[#vec4_i64_arg0]] %[[#vec4_i64_arg1]] %[[#vec4_i64_arg2]]
+ %0 = call <4 x i64> @llvm.spv.sclamp.v4i64(<4 x i64> %a, <4 x i64> %b, <4 x
i64> %c)
+ ret <4 x i64> %0
+}
+
+; CHECK-LABEL: Begin function test_fclamp_v4half
+define noundef <4 x half> @test_fclamp_v4half(<4 x half> noundef %a, <4 x
half> noundef %b, <4 x half> noundef %c) {
+entry:
+ ; CHECK: %[[#vec4_f16_arg0:]] = OpFunctionParameter %[[#vec4_float_16]]
+ ; CHECK: %[[#vec4_f16_arg1:]] = OpFunctionParameter %[[#vec4_float_16]]
+ ; CHECK: %[[#vec4_f16_arg2:]] = OpFunctionParameter %[[#vec4_float_16]]
+ ; CHECK: %[[#]] = OpExtInst %[[#vec4_float_16]] %[[#op_ext]] fclamp
%[[#vec4_f16_arg0]] %[[#vec4_f16_arg1]] %[[#vec4_f16_arg2]]
+ %0 = call <4 x half> @llvm.spv.fclamp.v4f16(<4 x half> %a, <4 x half> %b, <4
x half> %c)
+ ret <4 x half> %0
+}
+
+; CHECK-LABEL: Begin function test_fclamp_v4float
+define noundef <4 x float> @test_fclamp_v4float(<4 x float> noundef %a, <4 x
float> noundef %b, <4 x float> noundef %c) {
+entry:
+ ; CHECK: %[[#vec4_f32_arg0:]] = OpFunctionParameter %[[#vec4_float_32]]
+ ; CHECK: %[[#vec4_f32_arg1:]] = OpFunctionParameter %[[#vec4_float_32]]
+ ; CHECK: %[[#vec4_f32_arg2:]] = OpFunctionParameter %[[#vec4_float_32]]
+ ; CHECK: %[[#]] = OpExtInst %[[#vec4_float_32]] %[[#op_ext]] fclamp
%[[#vec4_f32_arg0]] %[[#vec4_f32_arg1]] %[[#vec4_f32_arg2]]
+ %0 = call <4 x float> @llvm.spv.fclamp.v4f32(<4 x float> %a, <4 x float> %b,
<4 x float> %c)
+ ret <4 x float> %0
+}
+
+; CHECK-LABEL: Begin function test_fclamp_v4double
+define noundef <4 x double> @test_fclamp_v4double(<4 x double> noundef %a, <4
x double> noundef %b, <4 x double> noundef %c) {
+entry:
+ ; CHECK: %[[#vec4_f64_arg0:]] = OpFunctionParameter %[[#vec4_float_64]]
+ ; CHECK: %[[#vec4_f64_arg1:]] = OpFunctionParameter %[[#vec4_float_64]]
+ ; CHECK: %[[#vec4_f64_arg2:]] = OpFunctionParameter %[[#vec4_float_64]]
+ ; CHECK: %[[#]] = OpExtInst %[[#vec4_float_64]] %[[#op_ext]] fclamp
%[[#vec4_f64_arg0]] %[[#vec4_f64_arg1]] %[[#vec4_f64_arg2]]
+ %0 = call <4 x double> @llvm.spv.fclamp.v4f64(<4 x double> %a, <4 x double>
%b, <4 x double> %c)
+ ret <4 x double> %0
+}
+
+; CHECK-LABEL: Begin function test_uclamp_v4i16
+define noundef <4 x i16> @test_uclamp_v4i16(<4 x i16> noundef %a, <4 x i16>
noundef %b, <4 x i16> noundef %c) {
+entry:
+ ; CHECK: %[[#vec4_i16_arg0:]] = OpFunctionParameter %[[#vec4_int_16]]
+ ; CHECK: %[[#vec4_i16_arg1:]] = OpFunctionParameter %[[#vec4_int_16]]
+ ; CHECK: %[[#vec4_i16_arg2:]] = OpFunctionParameter %[[#vec4_int_16]]
+ ; CHECK: %[[#]] = OpExtInst %[[#vec4_int_16]] %[[#op_ext]] u_clamp
%[[#vec4_i16_arg0]] %[[#vec4_i16_arg1]] %[[#vec4_i16_arg2]]
+ %0 = call <4 x i16> @llvm.spv.uclamp.v4i16(<4 x i16> %a, <4 x i16> %b, <4 x
i16> %c)
+ ret <4 x i16> %0
+}
+
+; CHECK-LABEL: Begin function test_uclamp_v4i32
+define noundef <4 x i32> @test_uclamp_v4i32(<4 x i32> noundef %a, <4 x i32>
noundef %b, <4 x i32> noundef %c) {
+entry:
+ ; CHECK: %[[#vec4_i32_arg0:]] = OpFunctionParameter %[[#vec4_int_32]]
+ ; CHECK: %[[#vec4_i32_arg1:]] = OpFunctionParameter %[[#vec4_int_32]]
+ ; CHECK: %[[#vec4_i32_arg2:]] = OpFunctionParameter %[[#vec4_int_32]]
+ ; CHECK: %[[#]] = OpExtInst %[[#vec4_int_32]] %[[#op_ext]] u_clamp
%[[#vec4_i32_arg0]] %[[#vec4_i32_arg1]] %[[#vec4_i32_arg2]]
+ %0 = call <4 x i32> @llvm.spv.uclamp.v4i32(<4 x i32> %a, <4 x i32> %b, <4 x
i32> %c)
+ ret <4 x i32> %0
+}
+
+; CHECK-LABEL: Begin function test_uclamp_v4i64
+define noundef <4 x i64> @test_uclamp_v4i64(<4 x i64> noundef %a, <4 x i64>
noundef %b, <4 x i64> noundef %c) {
+entry:
+ ; CHECK: %[[#vec4_i64_arg0:]] = OpFunctionParameter %[[#vec4_int_64]]
+ ; CHECK: %[[#vec4_i64_arg1:]] = OpFunctionParameter %[[#vec4_int_64]]
+ ; CHECK: %[[#vec4_i64_arg2:]] = OpFunctionParameter %[[#vec4_int_64]]
+ ; CHECK: %[[#]] = OpExtInst %[[#vec4_int_64]] %[[#op_ext]] u_clamp
%[[#vec4_i64_arg0]] %[[#vec4_i64_arg1]] %[[#vec4_i64_arg2]]
+ %0 = call <4 x i64> @llvm.spv.uclamp.v4i64(<4 x i64> %a, <4 x i64> %b, <4 x
i64> %c)
+ ret <4 x i64> %0
+}
+
+declare <4 x half> @llvm.spv.fclamp.v4f16(<4 x half>, <4 x half>, <4 x half>)
+declare <4 x float> @llvm.spv.fclamp.v4f32(<4 x float>, <4 x float>, <4 x
float>)
+declare <4 x double> @llvm.spv.fclamp.v4f64(<4 x double>, <4 x double>, <4 x
double>)
+declare <4 x i16> @llvm.spv.sclamp.v4i16(<4 x i16>, <4 x i16>, <4 x i16>)
+declare <4 x i32> @llvm.spv.sclamp.v4i32(<4 x i32>, <4 x i32>, <4 x i32>)
+declare <4 x i64> @llvm.spv.sclamp.v4i64(<4 x i64>, <4 x i64>, <4 x i64>)
+declare <4 x i16> @llvm.spv.uclamp.v4i16(<4 x i16>, <4 x i16>, <4 x i16>)
+declare <4 x i32> @llvm.spv.uclamp.v4i32(<4 x i32>, <4 x i32>, <4 x i32>)
+declare <4 x i64> @llvm.spv.uclamp.v4i64(<4 x i64>, <4 x i64>, <4 x i64>)
+
diff --git a/llvm/test/CodeGen/SPIRV/opencl/clamp.ll
b/llvm/test/CodeGen/SPIRV/opencl/clamp.ll
new file mode 100644
index 00000000000000..f6500442042cd9
--- /dev/null
+++ b/llvm/test/CodeGen/SPIRV/opencl/clamp.ll
@@ -0,0 +1,124 @@
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv64-unknown-unknown %s -o -
| FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown %s -o -
| FileCheck %s
+; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o -
-filetype=obj | spirv-val %}
+; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv32-unknown-unknown %s -o -
-filetype=obj | spirv-val %}
+
+; CHECK-DAG: %[[#op_ext:]] = OpExtInstImport "OpenCL.std"
+
+; CHECK-DAG: %[[#float_64:]] = OpTypeFloat 64
+; CHECK-DAG: %[[#float_32:]] = OpTypeFloat 32
+; CHECK-DAG: %[[#float_16:]] = OpTypeFloat 16
+
+; CHECK-DAG: %[[#int_64:]] = OpTypeInt 64
+; CHECK-DAG: %[[#int_32:]] = OpTypeInt 32
+; CHECK-DAG: %[[#int_16:]] = OpTypeInt 16
+
+; CHECK-LABEL: Begin function test_sclamp_i16
+define noundef i16 @test_sclamp_i16(i16 noundef %a, i16 noundef %b, i16
noundef %c) {
+entry:
+ ; CHECK: %[[#i16_arg0:]] = OpFunctionParameter %[[#int_16]]
+ ; CHECK: %[[#i16_arg1:]] = OpFunctionParameter %[[#int_16]]
+ ; CHECK: %[[#i16_arg2:]] = OpFunctionParameter %[[#int_16]]
+ ; CHECK: %[[#]] = OpExtInst %[[#int_16]] %[[#op_ext]] s_clamp %[[#i16_arg0]]
%[[#i16_arg1]] %[[#i16_arg2]]
+ %0 = call i16 @llvm.spv.sclamp.i16(i16 %a, i16 %b, i16 %c)
+ ret i16 %0
+}
+
+; CHECK-LABEL: Begin function test_sclamp_i32
+define noundef i32 @test_sclamp_i32(i32 noundef %a, i32 noundef %b, i32
noundef %c) {
+entry:
+ ; CHECK: %[[#i32_arg0:]] = OpFunctionParameter %[[#int_32]]
+ ; CHECK: %[[#i32_arg1:]] = OpFunctionParameter %[[#int_32]]
+ ; CHECK: %[[#i32_arg2:]] = OpFunctionParameter %[[#int_32]]
+ ; CHECK: %[[#]] = OpExtInst %[[#int_32]] %[[#op_ext]] s_clamp %[[#i32_arg0]]
%[[#i32_arg1]] %[[#i32_arg2]]
+ %0 = call i32 @llvm.spv.sclamp.i32(i32 %a, i32 %b, i32 %c)
+ ret i32 %0
+}
+
+; CHECK-LABEL: Begin function test_sclamp_i64
+define noundef i64 @test_sclamp_i64(i64 noundef %a, i64 noundef %b, i64
noundef %c) {
+entry:
+ ; CHECK: %[[#i64_arg0:]] = OpFunctionParameter %[[#int_64]]
+ ; CHECK: %[[#i64_arg1:]] = OpFunctionParameter %[[#int_64]]
+ ; CHECK: %[[#i64_arg2:]] = OpFunctionParameter %[[#int_64]]
+ ; CHECK: %[[#]] = OpExtInst %[[#int_64]] %[[#op_ext]] s_clamp %[[#i64_arg0]]
%[[#i64_arg1]] %[[#i64_arg2]]
+ %0 = call i64 @llvm.spv.sclamp.i64(i64 %a, i64 %b, i64 %c)
+ ret i64 %0
+}
+
+; CHECK-LABEL: Begin function test_fclamp_half
+define noundef half @test_fclamp_half(half noundef %a, half noundef %b, half
noundef %c) {
+entry:
+ ; CHECK: %[[#f16_arg0:]] = OpFunctionParameter %[[#float_16]]
+ ; CHECK: %[[#f16_arg1:]] = OpFunctionParameter %[[#float_16]]
+ ; CHECK: %[[#f16_arg2:]] = OpFunctionParameter %[[#float_16]]
+ ; CHECK: %[[#]] = OpExtInst %[[#float_16]] %[[#op_ext]] fclamp
%[[#f16_arg0]] %[[#f16_arg1]] %[[#f16_arg2]]
+ %0 = call half @llvm.spv.fclamp.f16(half %a, half %b, half %c)
+ ret half %0
+}
+
+; CHECK-LABEL: Begin function test_fclamp_float
+define noundef float @test_fclamp_float(float noundef %a, float noundef %b,
float noundef %c) {
+entry:
+ ; CHECK: %[[#f32_arg0:]] = OpFunctionParameter %[[#float_32]]
+ ; CHECK: %[[#f32_arg1:]] = OpFunctionParameter %[[#float_32]]
+ ; CHECK: %[[#f32_arg2:]] = OpFunctionParameter %[[#float_32]]
+ ; CHECK: %[[#]] = OpExtInst %[[#float_32]] %[[#op_ext]] fclamp
%[[#f32_arg0]] %[[#f32_arg1]] %[[#f32_arg2]]
+ %0 = call float @llvm.spv.fclamp.f32(float %a, float %b, float %c)
+ ret float %0
+}
+
+; CHECK-LABEL: Begin function test_fclamp_double
+define noundef double @test_fclamp_double(double noundef %a, double noundef
%b, double noundef %c) {
+entry:
+ ; CHECK: %[[#f64_arg0:]] = OpFunctionParameter %[[#float_64]]
+ ; CHECK: %[[#f64_arg1:]] = OpFunctionParameter %[[#float_64]]
+ ; CHECK: %[[#f64_arg2:]] = OpFunctionParameter %[[#float_64]]
+ ; CHECK: %[[#]] = OpExtInst %[[#float_64]] %[[#op_ext]] fclamp
%[[#f64_arg0]] %[[#f64_arg1]] %[[#f64_arg2]]
+ %0 = call double @llvm.spv.fclamp.f64(double %a, double %b, double %c)
+ ret double %0
+}
+
+; CHECK-LABEL: Begin function test_uclamp_i16
+define noundef i16 @test_uclamp_i16(i16 noundef %a, i16 noundef %b, i16
noundef %c) {
+entry:
+ ; CHECK: %[[#i16_arg0:]] = OpFunctionParameter %[[#int_16]]
+ ; CHECK: %[[#i16_arg1:]] = OpFunctionParameter %[[#int_16]]
+ ; CHECK: %[[#i16_arg2:]] = OpFunctionParameter %[[#int_16]]
+ ; CHECK: %[[#]] = OpExtInst %[[#int_16]] %[[#op_ext]] u_clamp %[[#i16_arg0]]
%[[#i16_arg1]] %[[#i16_arg2]]
+ %0 = call i16 @llvm.spv.uclamp.i16(i16 %a, i16 %b, i16 %c)
+ ret i16 %0
+}
+
+; CHECK-LABEL: Begin function test_uclamp_i32
+define noundef i32 @test_uclamp_i32(i32 noundef %a, i32 noundef %b, i32
noundef %c) {
+entry:
+ ; CHECK: %[[#i32_arg0:]] = OpFunctionParameter %[[#int_32]]
+ ; CHECK: %[[#i32_arg1:]] = OpFunctionParameter %[[#int_32]]
+ ; CHECK: %[[#i32_arg2:]] = OpFunctionParameter %[[#int_32]]
+ ; CHECK: %[[#]] = OpExtInst %[[#int_32]] %[[#op_ext]] u_clamp %[[#i32_arg0]]
%[[#i32_arg1]] %[[#i32_arg2]]
+ %0 = call i32 @llvm.spv.uclamp.i32(i32 %a, i32 %b, i32 %c)
+ ret i32 %0
+}
+
+; CHECK-LABEL: Begin function test_uclamp_i64
+define noundef i64 @test_uclamp_i64(i64 noundef %a, i64 noundef %b, i64
noundef %c) {
+entry:
+ ; CHECK: %[[#i64_arg0:]] = OpFunctionParameter %[[#int_64]]
+ ; CHECK: %[[#i64_arg1:]] = OpFunctionParameter %[[#int_64]]
+ ; CHECK: %[[#i64_arg2:]] = OpFunctionParameter %[[#int_64]]
+ ; CHECK: %[[#]] = OpExtInst %[[#int_64]] %[[#op_ext]] u_clamp %[[#i64_arg0]]
%[[#i64_arg1]] %[[#i64_arg2]]
+ %0 = call i64 @llvm.spv.uclamp.i64(i64 %a, i64 %b, i64 %c)
+ ret i64 %0
+}
+
+declare half @llvm.spv.fclamp.f16(half, half, half)
+declare float @llvm.spv.fclamp.f32(float, float, float)
+declare double @llvm.spv.fclamp.f64(double, double, double)
+declare i16 @llvm.spv.sclamp.i16(i16, i16, i16)
+declare i32 @llvm.spv.sclamp.i32(i32, i32, i32)
+declare i64 @llvm.spv.sclamp.i64(i64, i64, i64)
+declare i16 @llvm.spv.uclamp.i16(i16, i16, i16)
+declare i32 @llvm.spv.uclamp.i32(i32, i32, i32)
+declare i64 @llvm.spv.uclamp.i64(i64, i64, i64)
+
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