https://github.com/AlbertHuang-CPU updated
https://github.com/llvm/llvm-project/pull/110085
>From a0c620f312382391cdc5e444a0c847cb2ebd23aa Mon Sep 17 00:00:00 2001
From: albhua01 <albert.hu...@armchina.com>
Date: Thu, 26 Sep 2024 15:22:09 +0800
Subject: [PATCH 1/4] [ARM] [AArch32] Add support for Arm China STAR-MC1 CPU
---
llvm/include/llvm/TargetParser/ARMTargetParser.def | 1 +
llvm/lib/Target/ARM/ARMProcessors.td | 10 ++++++++++
llvm/lib/TargetParser/Host.cpp | 6 ++++++
llvm/unittests/TargetParser/TargetParserTest.cpp | 5 ++++-
4 files changed, 21 insertions(+), 1 deletion(-)
diff --git a/llvm/include/llvm/TargetParser/ARMTargetParser.def
b/llvm/include/llvm/TargetParser/ARMTargetParser.def
index e5a1ce54fd46a7..95dc24931e00c0 100644
--- a/llvm/include/llvm/TargetParser/ARMTargetParser.def
+++ b/llvm/include/llvm/TargetParser/ARMTargetParser.def
@@ -337,6 +337,7 @@ ARM_CPU_NAME("cortex-m4", ARMV7EM, FK_FPV4_SP_D16, true,
ARM::AEK_NONE)
ARM_CPU_NAME("cortex-m7", ARMV7EM, FK_FPV5_D16, false, ARM::AEK_NONE)
ARM_CPU_NAME("cortex-m23", ARMV8MBaseline, FK_NONE, false, ARM::AEK_NONE)
ARM_CPU_NAME("cortex-m33", ARMV8MMainline, FK_FPV5_SP_D16, false, ARM::AEK_DSP)
+ARM_CPU_NAME("star-mc1", ARMV8MMainline, FK_FPV5_SP_D16, false, ARM::AEK_DSP)
ARM_CPU_NAME("cortex-m35p", ARMV8MMainline, FK_FPV5_SP_D16, false,
ARM::AEK_DSP)
ARM_CPU_NAME("cortex-m55", ARMV8_1MMainline, FK_FP_ARMV8_FULLFP16_D16, false,
(ARM::AEK_DSP | ARM::AEK_SIMD | ARM::AEK_FP | ARM::AEK_FP16))
diff --git a/llvm/lib/Target/ARM/ARMProcessors.td
b/llvm/lib/Target/ARM/ARMProcessors.td
index a66a2c0b1981d8..293f1fabda7b4c 100644
--- a/llvm/lib/Target/ARM/ARMProcessors.td
+++ b/llvm/lib/Target/ARM/ARMProcessors.td
@@ -362,6 +362,16 @@ def : ProcessorModel<"cortex-m33", CortexM4Model,
[ARMv8mMainline,
FeatureHasNoBranchPredictor,
FeatureFixCMSE_CVE_2021_35465]>;
+def : ProcessorModel<"star-mc1", CortexM4Model, [ARMv8mMainline,
+ FeatureDSP,
+ FeatureFPARMv8_D16_SP,
+
FeaturePrefLoopAlign32,
+ FeatureHasSlowFPVMLx,
+ FeatureHasSlowFPVFMx,
+ FeatureUseMISched,
+
FeatureHasNoBranchPredictor,
+
FeatureFixCMSE_CVE_2021_35465]>;
+
def : ProcessorModel<"cortex-m35p", CortexM4Model, [ARMv8mMainline,
FeatureDSP,
FeatureFPARMv8_D16_SP,
diff --git a/llvm/lib/TargetParser/Host.cpp b/llvm/lib/TargetParser/Host.cpp
index 616e4eda1dd29d..1500c71f4039b5 100644
--- a/llvm/lib/TargetParser/Host.cpp
+++ b/llvm/lib/TargetParser/Host.cpp
@@ -342,6 +342,12 @@ StringRef sys::detail::getHostCPUNameForARM(StringRef
ProcCpuinfoContent) {
}
}
+ if (Implementer == "0x63") { // Arm China.
+ return StringSwitch<const char *>(Part)
+ .Case("0x132", "star-mc1")
+ .Default("generic");
+ }
+
if (Implementer == "0x6d") { // Microsoft Corporation.
// The Microsoft Azure Cobalt 100 CPU is handled as a Neoverse N2.
return StringSwitch<const char *>(Part)
diff --git a/llvm/unittests/TargetParser/TargetParserTest.cpp
b/llvm/unittests/TargetParser/TargetParserTest.cpp
index 13db80ab5c68ea..7b86290a71ee4a 100644
--- a/llvm/unittests/TargetParser/TargetParserTest.cpp
+++ b/llvm/unittests/TargetParser/TargetParserTest.cpp
@@ -490,6 +490,9 @@ INSTANTIATE_TEST_SUITE_P(
ARMCPUTestParams<uint64_t>("cortex-m33", "armv8-m.main", "fpv5-sp-d16",
ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP,
"8-M.Mainline"),
+ ARMCPUTestParams<uint64_t>("star-mc1", "armv8-m.main", "fpv5-sp-d16",
+ ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP,
+ "8-M.Mainline"),
ARMCPUTestParams<uint64_t>("cortex-m35p", "armv8-m.main",
"fpv5-sp-d16",
ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP,
"8-M.Mainline"),
@@ -518,7 +521,7 @@ INSTANTIATE_TEST_SUITE_P(
"7-S")),
ARMCPUTestParams<uint64_t>::PrintToStringParamName);
-static constexpr unsigned NumARMCPUArchs = 92;
+static constexpr unsigned NumARMCPUArchs = 93;
TEST(TargetParserTest, testARMCPUArchList) {
SmallVector<StringRef, NumARMCPUArchs> List;
>From 2cdf4d670f6e958baa1f2450e34c4060d4d4aee1 Mon Sep 17 00:00:00 2001
From: albhua01 <albert.hu...@armchina.com>
Date: Thu, 26 Sep 2024 18:03:47 +0800
Subject: [PATCH 2/4] amending for review comment
---
clang/test/Misc/target-invalid-cpu-note/arm.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/clang/test/Misc/target-invalid-cpu-note/arm.c
b/clang/test/Misc/target-invalid-cpu-note/arm.c
index 27608cc6eb29fc..17280a9edd221d 100644
--- a/clang/test/Misc/target-invalid-cpu-note/arm.c
+++ b/clang/test/Misc/target-invalid-cpu-note/arm.c
@@ -65,6 +65,7 @@
// CHECK-SAME: {{^}}, cortex-m7
// CHECK-SAME: {{^}}, cortex-m23
// CHECK-SAME: {{^}}, cortex-m33
+// CHECK-SAME: {{^}}, star-mc1
// CHECK-SAME: {{^}}, cortex-m35p
// CHECK-SAME: {{^}}, cortex-m55
// CHECK-SAME: {{^}}, cortex-m85
>From fb301dc3cdc70423923c21581cf7d8573dab8d2f Mon Sep 17 00:00:00 2001
From: AlbertHuang-CPU <albert.hu...@armchina.com>
Date: Thu, 26 Sep 2024 22:23:28 +0800
Subject: [PATCH 3/4] more changes for the tests
---
clang/test/Driver/arm-cortex-cpus-2.c | 2 ++
llvm/test/CodeGen/ARM/cmse-cve-2021-35465.ll | 6 ++++++
2 files changed, 8 insertions(+)
diff --git a/clang/test/Driver/arm-cortex-cpus-2.c
b/clang/test/Driver/arm-cortex-cpus-2.c
index 5ce3758655b500..2f17a081404361 100644
--- a/clang/test/Driver/arm-cortex-cpus-2.c
+++ b/clang/test/Driver/arm-cortex-cpus-2.c
@@ -559,8 +559,10 @@
// CHECK-CPUV8MBASE: "-cc1"{{.*}} "-triple" "thumbv8m.base-
// RUN: %clang -target arm -mcpu=cortex-m33 -### -c %s 2>&1 | FileCheck
-check-prefix=CHECK-CORTEX-M33 %s
+// RUN: %clang -target arm -mcpu=star-mc1 -### -c %s 2>&1 | FileCheck
-check-prefix=CHECK-STAR-MC1 %s
// RUN: %clang -target arm -mcpu=cortex-m35p -### -c %s 2>&1 | FileCheck
-check-prefix=CHECK-CORTEX-M35P %s
// CHECK-CORTEX-M33: "-cc1"{{.*}} "-triple" "thumbv8m.main-{{.*}}
"-target-cpu" "cortex-m33"
+// CHECK-STAR-MC1: "-cc1"{{.*}} "-triple" "thumbv8m.main-{{.*}} "-target-cpu"
"star-mc1"
// CHECK-CORTEX-M35P: "-cc1"{{.*}} "-triple" "thumbv8m.main-{{.*}}
"-target-cpu" "cortex-m35p"
// RUN: %clang -target arm -mcpu=cortex-m55 -### -c %s 2>&1 | FileCheck
-check-prefix=CHECK-CORTEX-M55 %s
diff --git a/llvm/test/CodeGen/ARM/cmse-cve-2021-35465.ll
b/llvm/test/CodeGen/ARM/cmse-cve-2021-35465.ll
index 31a0b9814d7f1f..5be0641420fc29 100644
--- a/llvm/test/CodeGen/ARM/cmse-cve-2021-35465.ll
+++ b/llvm/test/CodeGen/ARM/cmse-cve-2021-35465.ll
@@ -7,6 +7,9 @@
; RUN: llc %s -o - -mtriple=thumbv8m.main -mcpu=cortex-m33
-verify-machineinstrs | \
; RUN: FileCheck %s --check-prefix=CHECK-8M-FP-CVE-2021-35465
;
+; RUN: llc %s -o - -mtriple=thumbv8m.main -mcpu=star-mc1 -verify-machineinstrs
| \
+; RUN: FileCheck %s --check-prefix=CHECK-8M-FP-CVE-2021-35465
+;
; RUN: llc %s -o - -mtriple=thumbv8m.main -mcpu=cortex-m35p
-verify-machineinstrs | \
; RUN: FileCheck %s --check-prefix=CHECK-8M-FP-CVE-2021-35465
;
@@ -17,6 +20,9 @@
; RUN: llc %s -o - -mtriple=thumbv8m.main -mcpu=cortex-m33 -mattr=-fpregs
-verify-machineinstrs | \
; RUN: FileCheck %s --check-prefix=CHECK-8M-NOFP-CVE-2021-35465
;
+; RUN: llc %s -o - -mtriple=thumbv8m.main -mcpu=star-mc1 -mattr=-fpregs
-verify-machineinstrs | \
+; RUN: FileCheck %s --check-prefix=CHECK-8M-NOFP-CVE-2021-35465
+;
; RUN: llc %s -o - -mtriple=thumbv8m.main -mcpu=cortex-m35p -mattr=-fpregs
-verify-machineinstrs | \
; RUN: FileCheck %s --check-prefix=CHECK-8M-NOFP-CVE-2021-35465
;
>From 092cd2648e7666970b04460ac309f7f754d2e89b Mon Sep 17 00:00:00 2001
From: AlbertHuang-CPU <albert.hu...@armchina.com>
Date: Mon, 14 Oct 2024 19:00:13 +0800
Subject: [PATCH 4/4] update FeaturePreLoopAlign32 as the name changed
---
llvm/lib/Target/ARM/ARMProcessors.td | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/lib/Target/ARM/ARMProcessors.td
b/llvm/lib/Target/ARM/ARMProcessors.td
index 293f1fabda7b4c..a769c4669527dc 100644
--- a/llvm/lib/Target/ARM/ARMProcessors.td
+++ b/llvm/lib/Target/ARM/ARMProcessors.td
@@ -365,7 +365,7 @@ def : ProcessorModel<"cortex-m33", CortexM4Model,
[ARMv8mMainline,
def : ProcessorModel<"star-mc1", CortexM4Model, [ARMv8mMainline,
FeatureDSP,
FeatureFPARMv8_D16_SP,
-
FeaturePrefLoopAlign32,
+
FeaturePreferBranchAlign32,
FeatureHasSlowFPVMLx,
FeatureHasSlowFPVFMx,
FeatureUseMISched,
_______________________________________________
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
