Author: Jim Lin Date: 2024-10-14T10:47:59+08:00 New Revision: dba54fb074af1573984807e23640a202e0984a56
URL: https://github.com/llvm/llvm-project/commit/dba54fb074af1573984807e23640a202e0984a56 DIFF: https://github.com/llvm/llvm-project/commit/dba54fb074af1573984807e23640a202e0984a56.diff LOG: [RISCV] Add support for inline asm constraint vd (#111653) It constrains vector registers excluding v0. Refer to https://gcc.gnu.org/onlinedocs/gcc/Machine-Constraints.html RISC-V part. This patch also adds a testcase for constraints vr, vd and vm. Added: llvm/test/CodeGen/RISCV/inline-asm-v-constraint.ll Modified: clang/lib/Basic/Targets/RISCV.cpp clang/test/CodeGen/RISCV/riscv-inline-asm-rvv.c llvm/lib/Target/RISCV/RISCVISelLowering.cpp Removed: ################################################################################ diff --git a/clang/lib/Basic/Targets/RISCV.cpp b/clang/lib/Basic/Targets/RISCV.cpp index 2a225820208c8c..870f0f38bc3057 100644 --- a/clang/lib/Basic/Targets/RISCV.cpp +++ b/clang/lib/Basic/Targets/RISCV.cpp @@ -102,7 +102,7 @@ bool RISCVTargetInfo::validateAsmConstraint( return true; case 'v': // A vector register. - if (Name[1] == 'r' || Name[1] == 'm') { + if (Name[1] == 'r' || Name[1] == 'd' || Name[1] == 'm') { Info.setAllowsRegister(); Name += 1; return true; diff --git a/clang/test/CodeGen/RISCV/riscv-inline-asm-rvv.c b/clang/test/CodeGen/RISCV/riscv-inline-asm-rvv.c index 59adc5c45521ab..879fb1238d83ab 100644 --- a/clang/test/CodeGen/RISCV/riscv-inline-asm-rvv.c +++ b/clang/test/CodeGen/RISCV/riscv-inline-asm-rvv.c @@ -29,6 +29,14 @@ vint32m1_t test_vr(vint32m1_t a, vint32m1_t b) { return ret; } +vint32m1_t test_vd(vint32m1_t a, vint32m1_t b) { +// CHECK-LABEL: define{{.*}} @test_vd +// CHECK: %0 = tail call <vscale x 2 x i32> asm sideeffect "vadd.vv $0, $1, $2", "=^vd,^vd,^vd"(<vscale x 2 x i32> %a, <vscale x 2 x i32> %b) + vint32m1_t ret; + asm volatile ("vadd.vv %0, %1, %2" : "=vd"(ret) : "vd"(a), "vd"(b)); + return ret; +} + vbool1_t test_vm(vbool1_t a, vbool1_t b) { // CHECK-LABEL: define{{.*}} @test_vm // CHECK: %0 = tail call <vscale x 64 x i1> asm sideeffect "vmand.mm $0, $1, $2", "=^vm,^vm,^vm"(<vscale x 64 x i1> %a, <vscale x 64 x i1> %b) diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp index 9fe989bff263fb..133e76bbe6d73f 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -20227,7 +20227,7 @@ RISCVTargetLowering::getConstraintType(StringRef Constraint) const { return C_Other; } } else { - if (Constraint == "vr" || Constraint == "vm") + if (Constraint == "vr" || Constraint == "vd" || Constraint == "vm") return C_RegisterClass; } return TargetLowering::getConstraintType(Constraint); @@ -20275,6 +20275,19 @@ RISCVTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, if (TRI->isTypeLegalForClass(*RC, VT.SimpleTy)) return std::make_pair(0U, RC); } + } else if (Constraint == "vd") { + for (const auto *RC : + {&RISCV::VRNoV0RegClass, &RISCV::VRM2NoV0RegClass, + &RISCV::VRM4NoV0RegClass, &RISCV::VRM8NoV0RegClass, + &RISCV::VRN2M1NoV0RegClass, &RISCV::VRN3M1NoV0RegClass, + &RISCV::VRN4M1NoV0RegClass, &RISCV::VRN5M1NoV0RegClass, + &RISCV::VRN6M1NoV0RegClass, &RISCV::VRN7M1NoV0RegClass, + &RISCV::VRN8M1NoV0RegClass, &RISCV::VRN2M2NoV0RegClass, + &RISCV::VRN3M2NoV0RegClass, &RISCV::VRN4M2NoV0RegClass, + &RISCV::VRN2M4NoV0RegClass}) { + if (TRI->isTypeLegalForClass(*RC, VT.SimpleTy)) + return std::make_pair(0U, RC); + } } else if (Constraint == "vm") { if (TRI->isTypeLegalForClass(RISCV::VMV0RegClass, VT.SimpleTy)) return std::make_pair(0U, &RISCV::VMV0RegClass); diff --git a/llvm/test/CodeGen/RISCV/inline-asm-v-constraint.ll b/llvm/test/CodeGen/RISCV/inline-asm-v-constraint.ll new file mode 100644 index 00000000000000..c04e4fea7b2c29 --- /dev/null +++ b/llvm/test/CodeGen/RISCV/inline-asm-v-constraint.ll @@ -0,0 +1,66 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s \ +; RUN: | FileCheck -check-prefix=RV32I %s +; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s \ +; RUN: | FileCheck -check-prefix=RV64I %s + +define <vscale x 1 x i8> @constraint_vr(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1) nounwind { +; RV32I-LABEL: constraint_vr: +; RV32I: # %bb.0: +; RV32I-NEXT: #APP +; RV32I-NEXT: vadd.vv v8, v8, v9 +; RV32I-NEXT: #NO_APP +; RV32I-NEXT: ret +; +; RV64I-LABEL: constraint_vr: +; RV64I: # %bb.0: +; RV64I-NEXT: #APP +; RV64I-NEXT: vadd.vv v8, v8, v9 +; RV64I-NEXT: #NO_APP +; RV64I-NEXT: ret + %a = tail call <vscale x 1 x i8> asm "vadd.vv $0, $1, $2", "=^vr,^vr,^vr"( + <vscale x 1 x i8> %0, <vscale x 1 x i8> %1) + ret <vscale x 1 x i8> %a +} + +define <vscale x 1 x i8> @constraint_vd(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1) nounwind { +; RV32I-LABEL: constraint_vd: +; RV32I: # %bb.0: +; RV32I-NEXT: #APP +; RV32I-NEXT: vadd.vv v8, v8, v9 +; RV32I-NEXT: #NO_APP +; RV32I-NEXT: ret +; +; RV64I-LABEL: constraint_vd: +; RV64I: # %bb.0: +; RV64I-NEXT: #APP +; RV64I-NEXT: vadd.vv v8, v8, v9 +; RV64I-NEXT: #NO_APP +; RV64I-NEXT: ret + %a = tail call <vscale x 1 x i8> asm "vadd.vv $0, $1, $2", "=^vd,^vr,^vr"( + <vscale x 1 x i8> %0, <vscale x 1 x i8> %1) + ret <vscale x 1 x i8> %a +} + +define <vscale x 1 x i1> @constraint_vm(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1) nounwind { +; RV32I-LABEL: constraint_vm: +; RV32I: # %bb.0: +; RV32I-NEXT: vmv1r.v v9, v0 +; RV32I-NEXT: vmv1r.v v0, v8 +; RV32I-NEXT: #APP +; RV32I-NEXT: vadd.vv v0, v9, v0 +; RV32I-NEXT: #NO_APP +; RV32I-NEXT: ret +; +; RV64I-LABEL: constraint_vm: +; RV64I: # %bb.0: +; RV64I-NEXT: vmv1r.v v9, v0 +; RV64I-NEXT: vmv1r.v v0, v8 +; RV64I-NEXT: #APP +; RV64I-NEXT: vadd.vv v0, v9, v0 +; RV64I-NEXT: #NO_APP +; RV64I-NEXT: ret + %a = tail call <vscale x 1 x i1> asm "vadd.vv $0, $1, $2", "=^vr,^vr,^vm"( + <vscale x 1 x i1> %0, <vscale x 1 x i1> %1) + ret <vscale x 1 x i1> %a +} _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
