llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT--> @llvm/pr-subscribers-backend-risc-v Author: None (dong-miao) <details> <summary>Changes</summary> This commit has completed the Extension for Resumable Non Maskable Interrupts, adding four CRSs and one Trap-Return instruction. Specification link:["Smrnmi" Extension](https://github.com/riscv/riscv-isa-manual/blob/main/src/rnmi.adoc) --- Full diff: https://github.com/llvm/llvm-project/pull/111668.diff 11 Files Affected: - (modified) clang/test/Preprocessor/riscv-target-features.c (+9) - (modified) llvm/docs/RISCVUsage.rst (+1) - (modified) llvm/lib/Target/RISCV/RISCVFeatures.td (+4) - (modified) llvm/lib/Target/RISCV/RISCVInstrInfo.td (+9) - (modified) llvm/lib/Target/RISCV/RISCVSystemOperands.td (+8) - (modified) llvm/test/CodeGen/RISCV/attributes.ll (+4) - (modified) llvm/test/MC/RISCV/attribute-arch.s (+3) - (modified) llvm/test/MC/RISCV/machine-csr-names.s (+60) - (modified) llvm/test/MC/RISCV/priv-invalid.s (+2) - (modified) llvm/test/MC/RISCV/priv-valid.s (+4) - (modified) llvm/unittests/TargetParser/RISCVISAInfoTest.cpp (+1) ``````````diff diff --git a/clang/test/Preprocessor/riscv-target-features.c b/clang/test/Preprocessor/riscv-target-features.c index 05a8534ba13da1..9e986f0143aefa 100644 --- a/clang/test/Preprocessor/riscv-target-features.c +++ b/clang/test/Preprocessor/riscv-target-features.c @@ -30,6 +30,7 @@ // CHECK-NOT: __riscv_smcdeleg {{.*$}} // CHECK-NOT: __riscv_smcsrind {{.*$}} // CHECK-NOT: __riscv_smepmp {{.*$}} +// CHECK-NOT: __riscv_smrnmi {{.*$}} // CHECK-NOT: __riscv_smstateen {{.*$}} // CHECK-NOT: __riscv_ssaia {{.*$}} // CHECK-NOT: __riscv_ssccfg {{.*$}} @@ -1449,6 +1450,14 @@ // RUN: -o - | FileCheck --check-prefix=CHECK-SMEPMP-EXT %s // CHECK-SMEPMP-EXT: __riscv_smepmp 1000000{{$}} +// RUN: %clang --target=riscv32 \ +// RUN: -march=rv32ismrnmi1p0 -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-SMRNMI-EXT %s +// RUN: %clang --target=riscv64 \ +// RUN: -march=rv64ismrnmi1p0 -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-SMRNMI-EXT %s +// CHECK-SMRNMI-EXT: __riscv_smrnmi 1000000{{$}} + // RUN: %clang --target=riscv32-unknown-linux-gnu \ // RUN: -march=rv32izfa -E -dM %s \ // RUN: -o - | FileCheck --check-prefix=CHECK-ZFA-EXT %s diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst index 5736f3807f131b..a7ea36191283a3 100644 --- a/llvm/docs/RISCVUsage.rst +++ b/llvm/docs/RISCVUsage.rst @@ -129,6 +129,7 @@ on support follow. ``Smcdeleg`` Supported ``Smcsrind`` Supported ``Smepmp`` Supported + ``Smrnmi`` Supported ``Smstateen`` Assembly Support ``Ssaia`` Supported ``Ssccfg`` Supported diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td index 3d0e1dae801d39..10b18e33f2abb2 100644 --- a/llvm/lib/Target/RISCV/RISCVFeatures.td +++ b/llvm/lib/Target/RISCV/RISCVFeatures.td @@ -931,6 +931,10 @@ def FeatureStdExtSmepmp : RISCVExtension<"smepmp", 1, 0, "'Smepmp' (Enhanced Physical Memory Protection)">; +def FeatureStdExtSmrnmi + : RISCVExtension<"smrnmi", 1, 0, + "'Smrnmi' (Extension for Resumable Non-Maskable Interrupts)">; + def FeatureStdExtSmcdeleg : RISCVExtension<"smcdeleg", 1, 0, "'Smcdeleg' (Counter Delegation Machine Level)">; diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td index 5d329dceac6519..485fe386187c53 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td @@ -66,6 +66,8 @@ def riscv_sret_glue : SDNode<"RISCVISD::SRET_GLUE", SDTNone, [SDNPHasChain, SDNPOptInGlue]>; def riscv_mret_glue : SDNode<"RISCVISD::MRET_GLUE", SDTNone, [SDNPHasChain, SDNPOptInGlue]>; +def riscv_mnret_glue : SDNode<"RISCVISD::MNRET_GLUE", SDTNone, + [SDNPHasChain, SDNPOptInGlue]>; def riscv_selectcc : SDNode<"RISCVISD::SELECT_CC", SDT_RISCVSelectCC>; def riscv_brcc : SDNode<"RISCVISD::BR_CC", SDT_RISCVBrCC, [SDNPHasChain]>; @@ -813,6 +815,12 @@ def MRET : Priv<"mret", 0b0011000>, Sched<[]> { let rs1 = 0; let rs2 = 0b00010; } + +def MNRET : Priv<"mnret", 0b0111000>, Sched<[]> { + let rd = 0; + let rs1 = 0; + let rs2 = 0b00010; +} } // isBarrier = 1, isReturn = 1, isTerminator = 1 def WFI : Priv<"wfi", 0b0001000>, Sched<[]> { @@ -1581,6 +1589,7 @@ def : Pat<(riscv_call texternalsym:$func), (PseudoCALL texternalsym:$func)>; def : Pat<(riscv_sret_glue), (SRET)>; def : Pat<(riscv_mret_glue), (MRET)>; +def : Pat<(riscv_mnret_glue), (MNRET)>; let isCall = 1, Defs = [X1] in { let Predicates = [NoStdExtZicfilp] in diff --git a/llvm/lib/Target/RISCV/RISCVSystemOperands.td b/llvm/lib/Target/RISCV/RISCVSystemOperands.td index d85b4a9cf77b33..faec8d0b5bc003 100644 --- a/llvm/lib/Target/RISCV/RISCVSystemOperands.td +++ b/llvm/lib/Target/RISCV/RISCVSystemOperands.td @@ -276,6 +276,14 @@ foreach i = 0...15 in { foreach i = 0...63 in def : SysReg<"pmpaddr"#i, !add(0x3B0, i)>; +//===----------------------------------------------------------------------===// +// Machine Non-Maskable Interrupt Handling +//===----------------------------------------------------------------------===// +def:SysReg<"mnscratch",0x740>; +def:SysReg<"mnepc",0x741>; +def:SysReg<"mncause",0x742>; +def:SysReg<"mnstatus",0x744>; + //===----------------------------------------------------------------------===// // Machine Counter and Timers //===----------------------------------------------------------------------===// diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll index 86ce368bc1db66..aa27d63bfa6262 100644 --- a/llvm/test/CodeGen/RISCV/attributes.ll +++ b/llvm/test/CodeGen/RISCV/attributes.ll @@ -118,6 +118,7 @@ ; RUN: llc -mtriple=riscv32 -mattr=+ssqosid %s -o - | FileCheck --check-prefix=RV32SSQOSID %s ; RUN: llc -mtriple=riscv32 -mattr=+smcdeleg %s -o - | FileCheck --check-prefixes=CHECK,RV32SMCDELEG %s ; RUN: llc -mtriple=riscv32 -mattr=+smepmp %s -o - | FileCheck --check-prefixes=CHECK,RV32SMEPMP %s +; RUN: llc -mtriple=riscv32 -mattr=+smrnmi %s -o - | FileCheck --check-prefixes=CHECK,RV32SMRNMI %s ; RUN: llc -mtriple=riscv32 -mattr=+zfbfmin %s -o - | FileCheck --check-prefixes=CHECK,RV32ZFBFMIN %s ; RUN: llc -mtriple=riscv32 -mattr=+zvfbfmin %s -o - | FileCheck --check-prefixes=CHECK,RV32ZVFBFMIN %s ; RUN: llc -mtriple=riscv32 -mattr=+zvfbfwma %s -o - | FileCheck --check-prefixes=CHECK,RV32ZVFBFWMA %s @@ -261,6 +262,7 @@ ; RUN: llc -mtriple=riscv64 -mattr=+ssqosid %s -o - | FileCheck --check-prefix=RV64SSQOSID %s ; RUN: llc -mtriple=riscv64 -mattr=+smcdeleg %s -o - | FileCheck --check-prefixes=CHECK,RV64SMCDELEG %s ; RUN: llc -mtriple=riscv64 -mattr=+smepmp %s -o - | FileCheck --check-prefixes=CHECK,RV64SMEPMP %s +; RUN: llc -mtriple=riscv64 -mattr=+smrnmi %s -o - | FileCheck --check-prefixes=CHECK,RV64SMRNMI %s ; RUN: llc -mtriple=riscv64 -mattr=+zfbfmin %s -o - | FileCheck --check-prefixes=CHECK,RV64ZFBFMIN %s ; RUN: llc -mtriple=riscv64 -mattr=+zvfbfmin %s -o - | FileCheck --check-prefixes=CHECK,RV64ZVFBFMIN %s ; RUN: llc -mtriple=riscv64 -mattr=+zvfbfwma %s -o - | FileCheck --check-prefixes=CHECK,RV64ZVFBFWMA %s @@ -410,6 +412,7 @@ ; RV32SSQOSID: .attribute 5, "rv32i2p1_ssqosid1p0" ; RV32SMCDELEG: .attribute 5, "rv32i2p1_smcdeleg1p0" ; RV32SMEPMP: .attribute 5, "rv32i2p1_smepmp1p0" +; RV32SMRNMI: .attribute 5, "rv32i2p1_smrnmi1p0" ; RV32ZFBFMIN: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfbfmin1p0" ; RV32ZVFBFMIN: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvl32b1p0" ; RV32ZVFBFWMA: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfbfmin1p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvfbfwma1p0_zvl32b1p0" @@ -551,6 +554,7 @@ ; RV64SSQOSID: .attribute 5, "rv64i2p1_ssqosid1p0" ; RV64SMCDELEG: .attribute 5, "rv64i2p1_smcdeleg1p0" ; RV64SMEPMP: .attribute 5, "rv64i2p1_smepmp1p0" +; RV64SMRNMI: .attribute 5, "rv64i2p1_smrnmi1p0" ; RV64ZFBFMIN: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zfbfmin1p0" ; RV64ZVFBFMIN: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvl32b1p0" ; RV64ZVFBFWMA: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zfbfmin1p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvfbfwma1p0_zvl32b1p0" diff --git a/llvm/test/MC/RISCV/attribute-arch.s b/llvm/test/MC/RISCV/attribute-arch.s index 1c0b2a59d0693f..078a58f0139075 100644 --- a/llvm/test/MC/RISCV/attribute-arch.s +++ b/llvm/test/MC/RISCV/attribute-arch.s @@ -327,6 +327,9 @@ .attribute arch, "rv32i_smepmp1p0" # CHECK: attribute 5, "rv32i2p1_smepmp1p0" +.attribute arch, "rv32i_smrnmi1p0" +# CHECK: attribute 5, "rv32i2p1_smrnmid1p0" + .attribute arch, "rv32i_ssccfg1p0" # CHECK: attribute 5, "rv32i2p1_ssccfg1p0" diff --git a/llvm/test/MC/RISCV/machine-csr-names.s b/llvm/test/MC/RISCV/machine-csr-names.s index ae1af1fc8abc35..1e13d5c60b8a48 100644 --- a/llvm/test/MC/RISCV/machine-csr-names.s +++ b/llvm/test/MC/RISCV/machine-csr-names.s @@ -1913,6 +1913,66 @@ csrrs t1, mhpmcounter31, zero csrrs t2, 0xB1F, zero +###################################### +# Machine Counter Setup +###################################### +# mnscratch +# name +# CHECK-INST: csrrs t1, mnscratch, zero +# CHECK-ENC: encoding: [0x73,0x23,0x00,0x74] +# CHECK-INST-ALIAS: csrr t1, mnscratch +# uimm12 +# CHECK-INST: csrrs t2, mnscratch, zero +# CHECK-ENC: encoding: [0xf3,0x23,0x00,0x74] +# CHECK-INST-ALIAS: csrr t2, mnscratch +# name +csrrs t1, mnscratch, zero +# uimm12 +csrrs t2, 0x740, zero + +# mnepc +# name +# CHECK-INST: csrrs t1, mnepc, zero +# CHECK-ENC: encoding: [0x73,0x23,0x10,0x74] +# CHECK-INST-ALIAS: csrr t1, mnepc +# uimm12 +# CHECK-INST: csrrs t2, mnepc, zero +# CHECK-ENC: encoding: [0xf3,0x23,0x10,0x74] +# CHECK-INST-ALIAS: csrr t2, mnepc +# name +csrrs t1, mnepc, zero +# uimm12 +csrrs t2, 0x741, zero + +# mncause +# name +# CHECK-INST: csrrs t1, mncause, zero +# CHECK-ENC: encoding: [0x73,0x23,0x20,0x74] +# CHECK-INST-ALIAS: csrr t1, mncause +# uimm12 +# CHECK-INST: csrrs t2, mncause, zero +# CHECK-ENC: encoding: [0xf3,0x23,0x20,0x74] +# CHECK-INST-ALIAS: csrr t2, mncause +# name +csrrs t1, mncause, zero +# uimm12 +csrrs t2, 0x742, zero + +# mnstatus +# name +# CHECK-INST: csrrs t1, mnstatus, zero +# CHECK-ENC: encoding: [0x73,0x23,0x40,0x74] +# CHECK-INST-ALIAS: csrr t1, mnstatus +# uimm12 +# CHECK-INST: csrrs t2, mnstatus, zero +# CHECK-ENC: encoding: [0xf3,0x23,0x40,0x74] +# CHECK-INST-ALIAS: csrr t2, mnstatus +# name +csrrs t1, mnstatus, zero +# uimm12 +csrrs t2, 0x744, zero + + ###################################### # Machine Counter Setup ###################################### diff --git a/llvm/test/MC/RISCV/priv-invalid.s b/llvm/test/MC/RISCV/priv-invalid.s index d0446dbd1f8656..e9ed3c3d0d0ab7 100644 --- a/llvm/test/MC/RISCV/priv-invalid.s +++ b/llvm/test/MC/RISCV/priv-invalid.s @@ -2,6 +2,8 @@ mret 0x10 # CHECK: :[[@LINE]]:6: error: invalid operand for instruction +mnret 0x10 # CHECK: :[[@LINE]]:6: error: invalid operand for instruction + sfence.vma zero, a1, a2 # CHECK: :[[@LINE]]:22: error: invalid operand for instruction sfence.vma a0, 0x10 # CHECK: :[[@LINE]]:16: error: invalid operand for instruction diff --git a/llvm/test/MC/RISCV/priv-valid.s b/llvm/test/MC/RISCV/priv-valid.s index 561c76bf4fa295..75dc8c6b98cc52 100644 --- a/llvm/test/MC/RISCV/priv-valid.s +++ b/llvm/test/MC/RISCV/priv-valid.s @@ -17,6 +17,10 @@ sret # CHECK: encoding: [0x73,0x00,0x20,0x30] mret +# CHECK-INST: mnret +# CHECK: encoding: [0x73,0x00,0x20,0x70] +mnret + # CHECK-INST: wfi # CHECK: encoding: [0x73,0x00,0x50,0x10] wfi diff --git a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp index 33944b64dc1577..ded43a4ff7875a 100644 --- a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp +++ b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp @@ -1065,6 +1065,7 @@ R"(All available -march extensions for RISC-V smcdeleg 1.0 smcsrind 1.0 smepmp 1.0 + smrnmi 1.0 smstateen 1.0 ssaia 1.0 ssccfg 1.0 `````````` </details> https://github.com/llvm/llvm-project/pull/111668 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
