https://github.com/CarolineConcatto updated
https://github.com/llvm/llvm-project/pull/101644
>From 4da98aa5ad88276fc957571bfbebdd57a5f3918d Mon Sep 17 00:00:00 2001
From: Caroline Concatto <caroline.conca...@arm.com>
Date: Fri, 2 Aug 2024 08:47:18 +0000
Subject: [PATCH] [CLANG]Add Scalable vectors for mfloat8_t
This patch adds these new vector sizes for sve:
svmfloat8_t
According to the ARM ACLE PR#323[1].
[1] ARM-software/acle#323
---
.../clang/Basic/AArch64SVEACLETypes.def | 1 +
clang/include/clang/Basic/arm_sve_sme_incl.td | 1 +
.../include/clang/Serialization/ASTBitCodes.h | 2 +-
clang/lib/AST/ASTContext.cpp | 1 +
clang/lib/CodeGen/CodeGenTypes.cpp | 3 +-
clang/test/CodeGen/arm-mfp8.c | 28 ++++++++++++++++
clang/test/Sema/arm-mfp8.cpp | 13 ++++++++
clang/utils/TableGen/SveEmitter.cpp | 33 ++++++++++++++++---
8 files changed, 75 insertions(+), 7 deletions(-)
create mode 100644 clang/test/CodeGen/arm-mfp8.c
create mode 100644 clang/test/Sema/arm-mfp8.cpp
diff --git a/clang/include/clang/Basic/AArch64SVEACLETypes.def
b/clang/include/clang/Basic/AArch64SVEACLETypes.def
index fa9c1ac0491c45..9169af4d3865f3 100644
--- a/clang/include/clang/Basic/AArch64SVEACLETypes.def
+++ b/clang/include/clang/Basic/AArch64SVEACLETypes.def
@@ -72,6 +72,7 @@ SVE_VECTOR_TYPE("__SVFloat32_t", "__SVFloat32_t", SveFloat32,
SveFloat32Ty, 4, 3
SVE_VECTOR_TYPE("__SVFloat64_t", "__SVFloat64_t", SveFloat64, SveFloat64Ty, 2,
64, true, true, false)
SVE_VECTOR_TYPE("__SVBfloat16_t", "__SVBfloat16_t", SveBFloat16,
SveBFloat16Ty, 8, 16, true, false, true)
+SVE_VECTOR_TYPE("__SVMfloat8_t", "__SVMfloat8_t", SveMFloat8, SveMFloat8Ty,
16, 8, false, false, false)
//
// x2
diff --git a/clang/include/clang/Basic/arm_sve_sme_incl.td
b/clang/include/clang/Basic/arm_sve_sme_incl.td
index 37e39255098361..a330aa98269436 100644
--- a/clang/include/clang/Basic/arm_sve_sme_incl.td
+++ b/clang/include/clang/Basic/arm_sve_sme_incl.td
@@ -160,6 +160,7 @@ def EltTyBool16 : EltType<10>;
def EltTyBool32 : EltType<11>;
def EltTyBool64 : EltType<12>;
def EltTyBFloat16 : EltType<13>;
+def EltTyMFloat8 : EltType<14>;
class MemEltType<int val> {
int Value = val;
diff --git a/clang/include/clang/Serialization/ASTBitCodes.h
b/clang/include/clang/Serialization/ASTBitCodes.h
index a4728b1c06b3fe..c6e3790902f7f6 100644
--- a/clang/include/clang/Serialization/ASTBitCodes.h
+++ b/clang/include/clang/Serialization/ASTBitCodes.h
@@ -1109,7 +1109,7 @@ enum PredefinedTypeIDs {
///
/// Type IDs for non-predefined types will start at
/// NUM_PREDEF_TYPE_IDs.
-const unsigned NUM_PREDEF_TYPE_IDS = 503;
+const unsigned NUM_PREDEF_TYPE_IDS = 505;
// Ensure we do not overrun the predefined types we reserved
// in the enum PredefinedTypeIDs above.
diff --git a/clang/lib/AST/ASTContext.cpp b/clang/lib/AST/ASTContext.cpp
index 34aa399fda2f86..f308406483aac6 100644
--- a/clang/lib/AST/ASTContext.cpp
+++ b/clang/lib/AST/ASTContext.cpp
@@ -3908,6 +3908,7 @@ ASTContext::getBuiltinVectorTypeInfo(const BuiltinType
*Ty) const {
llvm_unreachable("Unsupported builtin vector type");
case BuiltinType::SveInt8:
return SVE_INT_ELTTY(8, 16, true, 1);
+ case BuiltinType::SveMFloat8:
case BuiltinType::SveUint8:
return SVE_INT_ELTTY(8, 16, false, 1);
case BuiltinType::SveInt8x2:
diff --git a/clang/lib/CodeGen/CodeGenTypes.cpp
b/clang/lib/CodeGen/CodeGenTypes.cpp
index 0a926e4ac27fe1..452ae6c7077ee4 100644
--- a/clang/lib/CodeGen/CodeGenTypes.cpp
+++ b/clang/lib/CodeGen/CodeGenTypes.cpp
@@ -493,7 +493,8 @@ llvm::Type *CodeGenTypes::ConvertType(QualType T) {
case BuiltinType::SveBFloat16:
case BuiltinType::SveBFloat16x2:
case BuiltinType::SveBFloat16x3:
- case BuiltinType::SveBFloat16x4: {
+ case BuiltinType::SveBFloat16x4:
+ case BuiltinType::SveMFloat8: {
ASTContext::BuiltinVectorTypeInfo Info =
Context.getBuiltinVectorTypeInfo(cast<BuiltinType>(Ty));
return llvm::ScalableVectorType::get(ConvertType(Info.ElementType),
diff --git a/clang/test/CodeGen/arm-mfp8.c b/clang/test/CodeGen/arm-mfp8.c
new file mode 100644
index 00000000000000..ccf0b62cd64bd7
--- /dev/null
+++ b/clang/test/CodeGen/arm-mfp8.c
@@ -0,0 +1,28 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
UTC_ARGS: --version 5
+// RUN: %clang_cc1 -emit-llvm -triple aarch64-arm-none-eabi -target-feature
-fp8 -target-feature +neon -target-feature +sve -o - %s | FileCheck %s
--check-prefixes=CHECK,CHECK-C
+// RUN: %clang_cc1 -emit-llvm -triple aarch64-arm-none-eabi -target-feature
-fp8 -target-feature +neon -target-feature +sve -o - -x c++ %s | FileCheck %s
--check-prefixes=CHECK,CHECK-CXX
+
+// REQUIRES: aarch64-registered-target
+
+#include <arm_sve.h>
+// CHECK-C-LABEL: define dso_local <vscale x 16 x i8> @test_ret_svmfloat8_t(
+// CHECK-C-SAME: <vscale x 16 x i8> [[V:%.*]]) #[[ATTR0]] {
+// CHECK-C-NEXT: [[ENTRY:.*:]]
+// CHECK-C-NEXT: [[V_ADDR:%.*]] = alloca <vscale x 16 x i8>, align 16
+// CHECK-C-NEXT: store <vscale x 16 x i8> [[V]], ptr [[V_ADDR]], align 16
+// CHECK-C-NEXT: [[TMP0:%.*]] = load <vscale x 16 x i8>, ptr [[V_ADDR]],
align 16
+// CHECK-C-NEXT: ret <vscale x 16 x i8> [[TMP0]]
+//
+// CHECK-CXX-LABEL: define dso_local <vscale x 16 x i8>
@_Z20test_ret_svmfloat8_tu13__SVMfloat8_t(
+// CHECK-CXX-SAME: <vscale x 16 x i8> [[V:%.*]]) #[[ATTR0]] {
+// CHECK-CXX-NEXT: [[ENTRY:.*:]]
+// CHECK-CXX-NEXT: [[V_ADDR:%.*]] = alloca <vscale x 16 x i8>, align 16
+// CHECK-CXX-NEXT: store <vscale x 16 x i8> [[V]], ptr [[V_ADDR]], align 16
+// CHECK-CXX-NEXT: [[TMP0:%.*]] = load <vscale x 16 x i8>, ptr [[V_ADDR]],
align 16
+// CHECK-CXX-NEXT: ret <vscale x 16 x i8> [[TMP0]]
+//
+svmfloat8_t test_ret_svmfloat8_t(svmfloat8_t v) {
+ return v;
+}
+//// NOTE: These prefixes are unused and the list is autogenerated. Do not add
tests below this line:
+// CHECK: {{.*}}
diff --git a/clang/test/Sema/arm-mfp8.cpp b/clang/test/Sema/arm-mfp8.cpp
new file mode 100644
index 00000000000000..85b0fae7eeada1
--- /dev/null
+++ b/clang/test/Sema/arm-mfp8.cpp
@@ -0,0 +1,13 @@
+// RUN: %clang_cc1 -fsyntax-only -verify=scalar,neon,sve -triple
aarch64-arm-none-eabi \
+// RUN: -target-feature -fp8 -target-feature +neon -target-feature +sve %s
+
+// REQUIRES: aarch64-registered-target
+
+#include <arm_sve.h>
+void test_vector_sve(svmfloat8_t a, svuint8_t c) {
+ a + c; // sve-error {{cannot convert between vector and non-scalar values
('svmfloat8_t' (aka '__SVMfloat8_t') and 'svuint8_t' (aka '__SVUint8_t'))}}
+ a - c; // sve-error {{cannot convert between vector and non-scalar values
('svmfloat8_t' (aka '__SVMfloat8_t') and 'svuint8_t' (aka '__SVUint8_t'))}}
+ a * c; // sve-error {{cannot convert between vector and non-scalar values
('svmfloat8_t' (aka '__SVMfloat8_t') and 'svuint8_t' (aka '__SVUint8_t'))}}
+ a / c; // sve-error {{cannot convert between vector and non-scalar values
('svmfloat8_t' (aka '__SVMfloat8_t') and 'svuint8_t' (aka '__SVUint8_t'))}}
+}
+
diff --git a/clang/utils/TableGen/SveEmitter.cpp
b/clang/utils/TableGen/SveEmitter.cpp
index 7d25914c735390..e4063ef8808405 100644
--- a/clang/utils/TableGen/SveEmitter.cpp
+++ b/clang/utils/TableGen/SveEmitter.cpp
@@ -67,7 +67,7 @@ class ImmCheck {
};
class SVEType {
- bool Float, Signed, Immediate, Void, Constant, Pointer, BFloat;
+ bool Float, Signed, Immediate, Void, Constant, Pointer, BFloat, MFloat;
bool DefaultType, IsScalable, Predicate, PredicatePattern, PrefetchOp,
Svcount;
unsigned Bitwidth, ElementBitwidth, NumVectors;
@@ -77,10 +77,10 @@ class SVEType {
SVEType(StringRef TS, char CharMod, unsigned NumVectors = 1)
: Float(false), Signed(true), Immediate(false), Void(false),
- Constant(false), Pointer(false), BFloat(false), DefaultType(false),
- IsScalable(true), Predicate(false), PredicatePattern(false),
- PrefetchOp(false), Svcount(false), Bitwidth(128), ElementBitwidth(~0U),
- NumVectors(NumVectors) {
+ Constant(false), Pointer(false), BFloat(false), MFloat(false),
+ DefaultType(false), IsScalable(true), Predicate(false),
+ PredicatePattern(false), PrefetchOp(false), Svcount(false),
+ Bitwidth(128), ElementBitwidth(~0U), NumVectors(NumVectors) {
if (!TS.empty())
applyTypespec(TS);
applyModifier(CharMod);
@@ -103,6 +103,10 @@ class SVEType {
bool isDefault() const { return DefaultType; }
bool isFloat() const { return Float && !BFloat; }
bool isBFloat() const { return BFloat && !Float; }
+ bool isMFloat() const {
+ return MFloat && !BFloat && !Float;
+ ;
+ }
bool isFloatingPoint() const { return Float || BFloat; }
bool isInteger() const {
return !isFloatingPoint() && !Predicate && !Svcount;
@@ -447,6 +451,8 @@ std::string SVEType::builtin_str() const {
else if (isBFloat()) {
assert(ElementBitwidth == 16 && "Not a valid BFloat.");
S += "y";
+ } else if (isMFloat()) {
+ S += "m";
}
if (!isFloatingPoint()) {
@@ -502,6 +508,8 @@ std::string SVEType::str() const {
S += "bool";
else if (isBFloat())
S += "bfloat";
+ else if (isMFloat())
+ S += "mfloat";
else
S += "int";
@@ -567,6 +575,12 @@ void SVEType::applyTypespec(StringRef TS) {
Float = false;
ElementBitwidth = 16;
break;
+ case 'm':
+ MFloat = true;
+ Float = false;
+ BFloat = false;
+ ElementBitwidth = 8;
+ break;
default:
llvm_unreachable("Unhandled type code!");
}
@@ -1018,6 +1032,8 @@ std::string Intrinsic::replaceTemplatedArgs(std::string
Name, TypeSpec TS,
TypeCode = 'b';
else if (T.isBFloat())
TypeCode = "bf";
+ else if (T.isMFloat())
+ TypeCode = "mfp";
else
TypeCode = 'f';
Ret.replace(Pos, NumChars, TypeCode + utostr(T.getElementSizeInBits()));
@@ -1111,6 +1127,11 @@ uint64_t SVEEmitter::encodeTypeFlags(const SVEType &T) {
return encodeEltType("EltTyBFloat16");
}
+ if (T.isMFloat()) {
+ assert(T.getElementSizeInBits() == 8 && "Not a valid MFloat.");
+ return encodeEltType("EltTyMFloat8");
+ }
+
if (T.isPredicateVector() || T.isSvcount()) {
switch (T.getElementSizeInBits()) {
case 8:
@@ -1288,6 +1309,8 @@ void SVEEmitter::createHeader(raw_ostream &OS) {
OS << "#include <arm_bf16.h>\n";
OS << "#include <arm_vector_types.h>\n";
+ OS << "typedef __SVMfloat8_t svmfloat8_t;\n\n";
+
OS << "typedef __SVFloat32_t svfloat32_t;\n";
OS << "typedef __SVFloat64_t svfloat64_t;\n";
OS << "typedef __clang_svint8x2_t svint8x2_t;\n";
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