Wilco1 wrote: So looking at the TRMs, the cores support MTE2 or MTE3 (and MTE3 is again no user visible change), but the hardware can be configured to only support MTE1. [This is also explained here](https://developer.arm.com/documentation/ka005919/1-0).
> I am not exposing any of +mte/+mte2 on the commandline, so there shouldn't be > any concerns for compatibility with GCC. I don't quite get the code, but it seems that +mte or +mte2 may be emitted in disassembly and/or supported by the assembler? https://github.com/llvm/llvm-project/pull/109299 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
