================
@@ -287,6 +288,11 @@ Supported
 ``Za128rs``, ``Za64rs``, ``Zama16b``, ``Zic64b``, ``Ziccamoa``, ``Ziccif``, 
``Zicclsm``, ``Ziccrse``, ``Shcounterenvw``, ``Shgatpa``, ``Shtvala``, 
``Shvsatpa``, ``Shvstvala``, ``Shvstvecd``, ``Ssccptr``, ``Sscounterenw``, 
``Ssstateen``, ``Ssstrict``, ``Sstvala``, ``Sstvecd``, ``Ssu64xl``, ``Svade``, 
``Svbare``
   These extensions are defined as part of the `RISC-V Profiles specification 
<https://github.com/riscv/riscv-profiles/releases/tag/v1.0>`__.  They do not 
introduce any new features themselves, but instead describe existing hardware 
features.
 
+.. _riscv-zacas-note:
+
+``Zacas``
+  The compiler will not generate amocas.d on RV32 or amocas.q on RV64 due to 
ABI compatibilty. These can only be used in the assembler. The extension will 
be left as experimental until `an ABI issue 
<https://github.com/riscv-non-isa/riscv-elf-psabi-doc/issues/444>`__ is 
resolved.
----------------
topperc wrote:

Drop the "experimental" par6t of the comment?

https://github.com/llvm/llvm-project/pull/109651
_______________________________________________
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

Reply via email to