llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT--> @llvm/pr-subscribers-clang Author: Craig Topper (topperc) <details> <summary>Changes</summary> https://github.com/riscv/riscv-control-transfer-records/releases/tag/v1.0_rc3 --- Full diff: https://github.com/llvm/llvm-project/pull/105148.diff 13 Files Affected: - (modified) clang/test/Driver/print-supported-extensions-riscv.c (+2) - (modified) clang/test/Preprocessor/riscv-target-features.c (+18) - (modified) llvm/docs/RISCVUsage.rst (+3) - (modified) llvm/docs/ReleaseNotes.rst (+1) - (modified) llvm/lib/Target/RISCV/RISCVFeatures.td (+13) - (modified) llvm/lib/Target/RISCV/RISCVInstrInfo.td (+8) - (modified) llvm/lib/Target/RISCV/RISCVSystemOperands.td (+9) - (modified) llvm/test/CodeGen/RISCV/attributes.ll (+8) - (modified) llvm/test/MC/RISCV/attribute-arch.s (+6) - (modified) llvm/test/MC/RISCV/hypervisor-csr-names.s (+17) - (modified) llvm/test/MC/RISCV/machine-csr-names.s (+17) - (modified) llvm/test/MC/RISCV/supervisor-csr-names.s (+43) - (modified) llvm/unittests/TargetParser/RISCVISAInfoTest.cpp (+2) ``````````diff diff --git a/clang/test/Driver/print-supported-extensions-riscv.c b/clang/test/Driver/print-supported-extensions-riscv.c index 132422393170a9..d93a3c5c05a654 100644 --- a/clang/test/Driver/print-supported-extensions-riscv.c +++ b/clang/test/Driver/print-supported-extensions-riscv.c @@ -174,8 +174,10 @@ // CHECK-NEXT: zalasr 0.1 'Zalasr' (Load-Acquire and Store-Release Instructions) // CHECK-NEXT: zvbc32e 0.7 'Zvbc32e' (Vector Carryless Multiplication with 32-bits elements) // CHECK-NEXT: zvkgs 0.7 'Zvkgs' (Vector-Scalar GCM instructions for Cryptography) +// CHECK-NEXT: smctr 1.0 'Smctr' (Control Transfer Records Machine Level) // CHECK-NEXT: smmpm 1.0 'Smmpm' (Machine-level Pointer Masking for M-mode) // CHECK-NEXT: smnpm 1.0 'Smnpm' (Machine-level Pointer Masking for next lower privilege mode) +// CHECK-NEXT: ssctr 1.0 'Ssctr' (Control Transfer Records Supervisor Level) // CHECK-NEXT: ssnpm 1.0 'Ssnpm' (Supervisor-level Pointer Masking for next lower privilege mode) // CHECK-NEXT: sspm 1.0 'Sspm' (Indicates Supervisor-mode Pointer Masking) // CHECK-NEXT: ssqosid 1.0 'Ssqosid' (Quality-of-Service (QoS) Identifiers) diff --git a/clang/test/Preprocessor/riscv-target-features.c b/clang/test/Preprocessor/riscv-target-features.c index 517702fab5b919..f66ef3d422f79a 100644 --- a/clang/test/Preprocessor/riscv-target-features.c +++ b/clang/test/Preprocessor/riscv-target-features.c @@ -175,8 +175,10 @@ // Experimental extensions +// CHECK-NOT: __riscv_smctr{{.*$}} // CHECK-NOT: __riscv_smmpm{{.*$}} // CHECK-NOT: __riscv_smnpm{{.*$}} +// CHECK-NOT: __riscv_ssctr{{.*$}} // CHECK-NOT: __riscv_ssnpm{{.*$}} // CHECK-NOT: __riscv_sspm{{.*$}} // CHECK-NOT: __riscv_ssqosid{{.*$}} @@ -1748,6 +1750,22 @@ // RUN: -o - | FileCheck --check-prefix=CHECK-SSQOSID-EXT %s // CHECK-SSQOSID-EXT: __riscv_ssqosid 1000000{{$}} +// RUN: %clang --target=riscv32 -menable-experimental-extensions \ +// RUN: -march=rv32i_smctr1p0 -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-SMCTR-EXT %s +// RUN: %clang --target=riscv64 -menable-experimental-extensions \ +// RUN: -march=rv64i_smctr1p0 -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-SMCTR-EXT %s +// CHECK-SMCTR-EXT: __riscv_smctr 1000000{{$}} + +// RUN: %clang --target=riscv32 -menable-experimental-extensions \ +// RUN: -march=rv32i_ssctr1p0 -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-SSCTR-EXT %s +// RUN: %clang --target=riscv64 -menable-experimental-extensions \ +// RUN: -march=rv64i_ssctr1p0 -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-SSCTR-EXT %s +// CHECK-SSCTR-EXT: __riscv_ssctr 1000000{{$}} + // Misaligned // RUN: %clang --target=riscv32-unknown-linux-gnu -march=rv32i -E -dM %s \ diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst index 3af1428138c021..74893d9aafc51b 100644 --- a/llvm/docs/RISCVUsage.rst +++ b/llvm/docs/RISCVUsage.rst @@ -305,6 +305,9 @@ The primary goal of experimental support is to assist in the process of ratifica ``experimental-zvbc32e``, ``experimental-zvkgs`` LLVM implements the `0.7 release specification <https://github.com/user-attachments/files/16450464/riscv-crypto-spec-vector-extra_v0.0.7.pdf>`__. +``experimental-smctr``, ``experimental-ssctr`` + LLVM implements the `1.0-rc3 specification <https://github.com/riscv/riscv-control-transfer-records/releases/tag/v1.0_rc3>`__. + To use an experimental extension from `clang`, you must add `-menable-experimental-extensions` to the command line, and specify the exact version of the experimental extension you are using. To use an experimental extension with LLVM's internal developer tools (e.g. `llc`, `llvm-objdump`, `llvm-mc`), you must prefix the extension name with `experimental-`. Note that you don't need to specify the version with internal tools, and shouldn't include the `experimental-` prefix with `clang`. Vendor Extensions diff --git a/llvm/docs/ReleaseNotes.rst b/llvm/docs/ReleaseNotes.rst index 005c59e00fb128..af158a7ebb414d 100644 --- a/llvm/docs/ReleaseNotes.rst +++ b/llvm/docs/ReleaseNotes.rst @@ -112,6 +112,7 @@ Changes to the RISC-V Backend means Zve32x and Zve32f will also require Zvl64b. The prior support was largely untested. * The ``Zvbc32e`` and ``Zvkgs`` extensions are now supported experimentally. +* Added ``Smctr`` and ``Ssctr`` extensions. Changes to the WebAssembly Backend ---------------------------------- diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td index a439e75a3d5af4..4e1dcbad462fc0 100644 --- a/llvm/lib/Target/RISCV/RISCVFeatures.td +++ b/llvm/lib/Target/RISCV/RISCVFeatures.td @@ -1054,6 +1054,19 @@ def FeatureStdExtSupm : RISCVExperimentalExtension<"supm", 1, 0, "'Supm' (Indicates User-mode Pointer Masking)">; +def FeatureStdExtSmctr + : RISCVExperimentalExtension<"smctr", 1, 0, + "'Smctr' (Control Transfer Records Machine Level)", + [FeatureStdExtSmcsrind]>; +def FeatureStdExtSsctr + : RISCVExperimentalExtension<"ssctr" ,1, 0, + "'Ssctr' (Control Transfer Records Supervisor Level)", + [FeatureStdExtSscsrind]>; +def HasStdExtSmctrOrSsctr : Predicate<"Subtarget->hasStdExtSmctrOrSsctr()">, + AssemblerPredicate<(any_of FeatureStdExtSmctr, FeatureStdExtSsctr), + "'Smctr' (Control Transfer Records Machine Level) or " + "'Ssctr' (Control Transfer Records Supervisor Level)">; + //===----------------------------------------------------------------------===// // Vendor extensions //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td index 74406bf4b10471..6d0952a42eda9f 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td @@ -839,6 +839,14 @@ def HLV_D : HLoad_r<0b0110110, 0b00000, "hlv.d">, Sched<[]>; def HSV_D : HStore_rr<0b0110111, "hsv.d">, Sched<[]>; } +let Predicates = [HasStdExtSmctrOrSsctr] in { +def SCTRCLR : Priv<"sctrclr", 0b0001000>, Sched<[]> { + let rd = 0; + let rs1 = 0; + let rs2 = 0b00100; +} +} + //===----------------------------------------------------------------------===// // Debug instructions //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/RISCV/RISCVSystemOperands.td b/llvm/lib/Target/RISCV/RISCVSystemOperands.td index a836227e18957c..d85b4a9cf77b33 100644 --- a/llvm/lib/Target/RISCV/RISCVSystemOperands.td +++ b/llvm/lib/Target/RISCV/RISCVSystemOperands.td @@ -455,3 +455,12 @@ def : SysReg<"mnscratch", 0x740>; def : SysReg<"mnepc", 0x741>; def : SysReg<"mncause", 0x742>; def : SysReg<"mnstatus", 0x744>; + +//===----------------------------------------------- +// Control Transfer Records CSRs +//===----------------------------------------------- +def : SysReg<"sctrctl", 0x14e>; +def : SysReg<"sctrstatus", 0x14f>; +def : SysReg<"sctrdepth", 0x15f>; +def : SysReg<"vsctrctl", 0x24e>; +def : SysReg<"mctrctl", 0x34e>; diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll index 3aee484beeaa35..b2078923636132 100644 --- a/llvm/test/CodeGen/RISCV/attributes.ll +++ b/llvm/test/CodeGen/RISCV/attributes.ll @@ -133,6 +133,8 @@ ; RUN: llc -mtriple=riscv32 -mattr=+experimental-sspm %s -o - | FileCheck --check-prefix=RV32SSPM %s ; RUN: llc -mtriple=riscv32 -mattr=+experimental-supm %s -o - | FileCheck --check-prefix=RV32SUPM %s ; RUN: llc -mtriple=riscv32 -mattr=+experimental-ssqosid %s -o - | FileCheck --check-prefix=RV32SSQOSID %s +; RUN: llc -mtriple=riscv32 -mattr=+experimental-smctr %s -o - | FileCheck --check-prefix=RV32SMCTR %s +; RUN: llc -mtriple=riscv32 -mattr=+experimental-ssctr %s -o - | FileCheck --check-prefix=RV32SSCTR %s ; RUN: llc -mtriple=riscv64 %s -o - | FileCheck %s ; RUN: llc -mtriple=riscv64 -mattr=+m %s -o - | FileCheck --check-prefixes=CHECK,RV64M %s @@ -273,6 +275,8 @@ ; RUN: llc -mtriple=riscv64 -mattr=+experimental-sspm %s -o - | FileCheck --check-prefix=RV64SSPM %s ; RUN: llc -mtriple=riscv64 -mattr=+experimental-supm %s -o - | FileCheck --check-prefix=RV64SUPM %s ; RUN: llc -mtriple=riscv64 -mattr=+experimental-ssqosid %s -o - | FileCheck --check-prefix=RV64SSQOSID %s +; RUN: llc -mtriple=riscv64 -mattr=+experimental-smctr %s -o - | FileCheck --check-prefix=RV64SMCTR %s +; RUN: llc -mtriple=riscv64 -mattr=+experimental-ssctr %s -o - | FileCheck --check-prefix=RV64SSCTR %s ; Tests for profile features. ; RUN: llc -mtriple=riscv32 -mattr=+rvi20u32 %s -o - | FileCheck --check-prefix=RVI20U32 %s @@ -421,6 +425,8 @@ ; RV32SSPM: .attribute 5, "rv32i2p1_sspm1p0" ; RV32SUPM: .attribute 5, "rv32i2p1_supm1p0" ; RV32SSQOSID: .attribute 5, "rv32i2p1_ssqosid1p0" +; RV32SMCTR: .attribute 5, "rv32i2p1_smcsrind1p0_smctr1p0" +; RV32SSCTR: .attribute 5, "rv32i2p1_sscsrind1p0_ssctr1p0" ; RV64M: .attribute 5, "rv64i2p1_m2p0_zmmul1p0" ; RV64ZMMUL: .attribute 5, "rv64i2p1_zmmul1p0" @@ -559,6 +565,8 @@ ; RV64SSPM: .attribute 5, "rv64i2p1_sspm1p0" ; RV64SUPM: .attribute 5, "rv64i2p1_supm1p0" ; RV64SSQOSID: .attribute 5, "rv64i2p1_ssqosid1p0" +; RV64SMCTR: .attribute 5, "rv64i2p1_smcsrind1p0_smctr1p0" +; RV64SSCTR: .attribute 5, "rv64i2p1_sscsrind1p0_ssctr1p0" ; RVI20U32: .attribute 5, "rv32i2p1" ; RVI20U64: .attribute 5, "rv64i2p1" diff --git a/llvm/test/MC/RISCV/attribute-arch.s b/llvm/test/MC/RISCV/attribute-arch.s index 0ba15cfd489cb1..7c353145c79981 100644 --- a/llvm/test/MC/RISCV/attribute-arch.s +++ b/llvm/test/MC/RISCV/attribute-arch.s @@ -446,3 +446,9 @@ .attribute arch, "rv64i_supm1p0" # CHECK: attribute 5, "rv64i2p1_supm1p0" + +.attribute arch, "rv32i_smctr1p0" +# CHECK: attribute 5, "rv32i2p1_smcsrind1p0_smctr1p0" + +.attribute arch, "rv32i_ssctr1p0" +# CHECK: attribute 5, "rv32i2p1_sscsrind1p0_ssctr1p0" diff --git a/llvm/test/MC/RISCV/hypervisor-csr-names.s b/llvm/test/MC/RISCV/hypervisor-csr-names.s index 950570c74746a9..2f29e5dacbeb95 100644 --- a/llvm/test/MC/RISCV/hypervisor-csr-names.s +++ b/llvm/test/MC/RISCV/hypervisor-csr-names.s @@ -633,3 +633,20 @@ csrrs t2, 0x25C, zero csrrs t1, vstopi, zero # uimm12 csrrs t2, 0xEB0, zero + +################################## +# Control Transfer Records +################################## + +# vsctrctl +# name +# CHECK-INST: csrrs t1, vsctrctl, zero +# CHECK-ENC: encoding: [0x73,0x23,0xe0,0x24] +# CHECK-INST-ALIAS: csrr t1, vsctrctl +# uimm12 +# CHECK-INST: csrrs t2, vsctrctl, zero +# CHECK-ENC: encoding: [0xf3,0x23,0xe0,0x24] +# CHECK-INST-ALIAS: csrr t2, vsctrctl +csrrs t1, vsctrctl, zero +# uimm12 +csrrs t2, 0x24E, zero diff --git a/llvm/test/MC/RISCV/machine-csr-names.s b/llvm/test/MC/RISCV/machine-csr-names.s index 5f668aea00485d..ae1af1fc8abc35 100644 --- a/llvm/test/MC/RISCV/machine-csr-names.s +++ b/llvm/test/MC/RISCV/machine-csr-names.s @@ -2568,3 +2568,20 @@ csrrs t2, 0x308, zero csrrs t1, mvip, zero # uimm12 csrrs t2, 0x309, zero + +################################## +# Control Transfer Records +################################## + +# mctrctl +# name +# CHECK-INST: csrrs t1, mctrctl, zero +# CHECK-ENC: encoding: [0x73,0x23,0xe0,0x34] +# CHECK-INST-ALIAS: csrr t1, mctrctl +# uimm12 +# CHECK-INST: csrrs t2, mctrctl, zero +# CHECK-ENC: encoding: [0xf3,0x23,0xe0,0x34] +# CHECK-INST-ALIAS: csrr t2, mctrctl +csrrs t1, mctrctl, zero +# uimm12 +csrrs t2, 0x34E, zero diff --git a/llvm/test/MC/RISCV/supervisor-csr-names.s b/llvm/test/MC/RISCV/supervisor-csr-names.s index 481f11e0082b8d..db0fcb381ef2a4 100644 --- a/llvm/test/MC/RISCV/supervisor-csr-names.s +++ b/llvm/test/MC/RISCV/supervisor-csr-names.s @@ -457,3 +457,46 @@ csrrs t2, 0xDB0, zero csrrs t1, scountinhibit, zero # uimm12 csrrs t2, 0x120, zero + +################################## +# Control Transfer Records +################################## + +# sctrctl +# name +# CHECK-INST: csrrs t1, sctrctl, zero +# CHECK-ENC: encoding: [0x73,0x23,0xe0,0x14] +# CHECK-INST-ALIAS: csrr t1, sctrctl +# uimm12 +# CHECK-INST: csrrs t2, sctrctl, zero +# CHECK-ENC: encoding: [0xf3,0x23,0xe0,0x14] +# CHECK-INST-ALIAS: csrr t2, sctrctl +csrrs t1, sctrctl, zero +# uimm12 +csrrs t2, 0x14E, zero + +# sctrstatus +# name +# CHECK-INST: csrrs t1, sctrstatus, zero +# CHECK-ENC: encoding: [0x73,0x23,0xf0,0x14] +# CHECK-INST-ALIAS: csrr t1, sctrstatus +# uimm12 +# CHECK-INST: csrrs t2, sctrstatus, zero +# CHECK-ENC: encoding: [0xf3,0x23,0xf0,0x14] +# CHECK-INST-ALIAS: csrr t2, sctrstatus +csrrs t1, sctrstatus, zero +# uimm12 +csrrs t2, 0x14F, zero + +# sctrdepth +# name +# CHECK-INST: csrrs t1, sctrdepth, zero +# CHECK-ENC: encoding: [0x73,0x23,0xf0,0x15] +# CHECK-INST-ALIAS: csrr t1, sctrdepth +# uimm12 +# CHECK-INST: csrrs t2, sctrdepth, zero +# CHECK-ENC: encoding: [0xf3,0x23,0xf0,0x15] +# CHECK-INST-ALIAS: csrr t2, sctrdepth +csrrs t1, sctrdepth, zero +# uimm12 +csrrs t2, 0x15F, zero diff --git a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp index d1de96477a5ca0..2063c2d5373507 100644 --- a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp +++ b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp @@ -1119,8 +1119,10 @@ Experimental extensions zalasr 0.1 zvbc32e 0.7 zvkgs 0.7 + smctr 1.0 smmpm 1.0 smnpm 1.0 + ssctr 1.0 ssnpm 1.0 sspm 1.0 ssqosid 1.0 `````````` </details> https://github.com/llvm/llvm-project/pull/105148 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
