================
@@ -64,6 +66,27 @@ void CommonSPIRABIInfo::setCCs() {
RuntimeCC = llvm::CallingConv::SPIR_FUNC;
}
+ABIArgInfo SPIRVABIInfo::classifyReturnType(QualType RetTy) const {
+ if (getTarget().getTriple().getVendor() != llvm::Triple::AMD)
+ return DefaultABIInfo::classifyReturnType(RetTy);
+ if (!isAggregateTypeForABI(RetTy) || getRecordArgABI(RetTy, getCXXABI()))
+ return DefaultABIInfo::classifyReturnType(RetTy);
+
+ if (const RecordType *RT = RetTy->getAs<RecordType>()) {
+ const RecordDecl *RD = RT->getDecl();
+ if (RD->hasFlexibleArrayMember())
+ return DefaultABIInfo::classifyReturnType(RetTy);
+ }
+
+ // TODO: The AMDGPU ABI is non-trivial to represent in SPIR-V; in order to
+ // avoid encoding various architecture specific bits here we return
everything
+ // as direct to retain type info for things like aggregates, for later
perusal
+ // when translating back to LLVM/lowering in the BE. This is also why we
+ // disable flattening as the outcomes can mismatch between SPIR-V and AMDGPU.
+ // This will be revisited / optimised in the future.
----------------
AlexVlx wrote:
I think you misunderstand the core problem, which is orthogonal to LLVM: SPIR-V
the IR specification does not [encode byref, only
byval](https://registry.khronos.org/SPIR-V/specs/unified1/SPIRV.html#_function_parameter_attribute).
Whatever you might feel about what is right or wrong is somewhat unhelpful
here, unless you are going to add an extension to that end? Trying to backdoor
this is just a lot of pain.
https://github.com/llvm/llvm-project/pull/102776
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