llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT--> @llvm/pr-subscribers-backend-risc-v @llvm/pr-subscribers-clang Author: Brandon Wu (4vtomat) <details> <summary>Changes</summary> Fix https://github.com/llvm/llvm-project/issues/101526 `vf[n|w]cvt.x[|u].f` for f16 needs `zvfh` instead of `zvfhmin`, current approach is not able to detect this. Ultimately we need to add `zvfh` to RequiredFeatures to check other intrinsics instead, the type check should be done in checkRVVTypeSupport. --- Full diff: https://github.com/llvm/llvm-project/pull/101811.diff 5 Files Affected: - (modified) clang/include/clang/Basic/riscv_vector.td (+42-6) - (modified) clang/include/clang/Basic/riscv_vector_common.td (+2-2) - (modified) clang/include/clang/Support/RISCVVIntrinsicUtils.h (+2-1) - (modified) clang/lib/Sema/SemaRISCV.cpp (+6) - (modified) clang/utils/TableGen/RISCVVEmitter.cpp (+1) ``````````diff diff --git a/clang/include/clang/Basic/riscv_vector.td b/clang/include/clang/Basic/riscv_vector.td index 0cab4b8067f0d..662771d640b69 100644 --- a/clang/include/clang/Basic/riscv_vector.td +++ b/clang/include/clang/Basic/riscv_vector.td @@ -1912,8 +1912,18 @@ def vfcvt_rtz_x_f_v : RVVConvToSignedBuiltin<"vfcvt_rtz_x">; let Log2LMUL = [-3, -2, -1, 0, 1, 2] in { def vfwcvt_rtz_xu_f_v : RVVConvToWidenUnsignedBuiltin<"vfwcvt_rtz_xu">; def vfwcvt_rtz_x_f_v : RVVConvToWidenSignedBuiltin<"vfwcvt_rtz_x">; - def vfwcvt_f_xu_v : RVVConvBuiltin<"Fw", "FwUv", "csi", "vfwcvt_f">; - def vfwcvt_f_x_v : RVVConvBuiltin<"Fw", "Fwv", "csi", "vfwcvt_f">; + def vfwcvt_f_xu_v : RVVConvBuiltin<"Fw", "FwUv", "si", "vfwcvt_f">; + def vfwcvt_f_x_v : RVVConvBuiltin<"Fw", "Fwv", "si", "vfwcvt_f">; + let RequiredFeatures = ["Zvfh"] in { + let Name = "vfwcvt_f_xu_v", + IRName = "vfwcvt_f_xu_v", + MaskedIRName = "vfwcvt_f_xu_v_mask" in + def : RVVConvBuiltin<"Fw", "FwUv", "c", "vfwcvt_f">; + let Name = "vfwcvt_f_x_v", + IRName = "vfwcvt_f_x_v", + MaskedIRName = "vfwcvt_f_x_v_mask" in + def : RVVConvBuiltin<"Fw", "Fwv", "c", "vfwcvt_f">; + } def vfwcvt_f_f_v : RVVConvBuiltin<"w", "wv", "f", "vfwcvt_f">; let RequiredFeatures = ["Zvfhmin"] in def vfwcvt_f_f_v_fp16 : RVVConvBuiltin<"w", "wv", "x", "vfwcvt_f"> { @@ -1927,6 +1937,16 @@ let Log2LMUL = [-3, -2, -1, 0, 1, 2] in { let Log2LMUL = [-3, -2, -1, 0, 1, 2] in { def vfncvt_rtz_xu_f_w : RVVConvToNarrowingUnsignedBuiltin<"vfncvt_rtz_xu">; def vfncvt_rtz_x_f_w : RVVConvToNarrowingSignedBuiltin<"vfncvt_rtz_x">; + let RequiredFeatures = ["Zvfh"] in { + let Name = "vfncvt_rtz_xu_f_w", + IRName = "vfncvt_rtz_xu_f_w", + MaskedIRName = "vfncvt_rtz_xu_f_w_mask" in + def : RVVConvBuiltin<"Uv", "UvFw", "c", "vfncvt_rtz_xu">; + let Name = "vfncvt_rtz_x_f_w", + IRName = "vfncvt_rtz_x_f_w", + MaskedIRName = "vfncvt_rtz_x_f_w_mask" in + def : RVVConvBuiltin<"Iv", "IvFw", "c", "vfncvt_rtz_x">; + } def vfncvt_rod_f_f_w : RVVConvBuiltin<"v", "vw", "xf", "vfncvt_rod_f">; } @@ -2005,10 +2025,18 @@ let ManualCodegen = [{ let Log2LMUL = [-3, -2, -1, 0, 1, 2] in { let OverloadedName = "vfncvt_x" in defm : - RVVConvBuiltinSet<"vfncvt_x_f_w", "csi", [["Iv", "IvFwu"]]>; + RVVConvBuiltinSet<"vfncvt_x_f_w", "si", [["Iv", "IvFwu"]]>; let OverloadedName = "vfncvt_xu" in defm : - RVVConvBuiltinSet<"vfncvt_xu_f_w", "csi", [["Uv", "UvFwu"]]>; + RVVConvBuiltinSet<"vfncvt_xu_f_w", "si", [["Uv", "UvFwu"]]>; + let RequiredFeatures = ["Zvfh"] in { + let OverloadedName = "vfncvt_x" in + defm : + RVVConvBuiltinSet<"vfncvt_x_f_w", "c", [["Iv", "IvFwu"]]>; + let OverloadedName = "vfncvt_xu" in + defm : + RVVConvBuiltinSet<"vfncvt_xu_f_w", "c", [["Uv", "UvFwu"]]>; + } let OverloadedName = "vfncvt_f" in { defm : RVVConvBuiltinSet<"vfncvt_f_x_w", "xf", [["v", "vIwu"]]>; @@ -2055,10 +2083,18 @@ let ManualCodegen = [{ let Log2LMUL = [-3, -2, -1, 0, 1, 2] in { let OverloadedName = "vfncvt_x" in defm : - RVVConvBuiltinSet<"vfncvt_x_f_w", "csi", [["Iv", "IvFw"]]>; + RVVConvBuiltinSet<"vfncvt_x_f_w", "si", [["Iv", "IvFw"]]>; let OverloadedName = "vfncvt_xu" in defm : - RVVConvBuiltinSet<"vfncvt_xu_f_w", "csi", [["Uv", "UvFw"]]>; + RVVConvBuiltinSet<"vfncvt_xu_f_w", "si", [["Uv", "UvFw"]]>; + let RequiredFeatures = ["Zvfh"] in { + let OverloadedName = "vfncvt_x" in + defm : + RVVConvBuiltinSet<"vfncvt_x_f_w", "c", [["Iv", "IvFw"]]>; + let OverloadedName = "vfncvt_xu" in + defm : + RVVConvBuiltinSet<"vfncvt_xu_f_w", "c", [["Uv", "UvFw"]]>; + } let OverloadedName = "vfncvt_f" in { defm : RVVConvBuiltinSet<"vfncvt_f_x_w", "xf", [["v", "vIw"]]>; diff --git a/clang/include/clang/Basic/riscv_vector_common.td b/clang/include/clang/Basic/riscv_vector_common.td index 040db6f0cdbfb..33f6441217a5e 100644 --- a/clang/include/clang/Basic/riscv_vector_common.td +++ b/clang/include/clang/Basic/riscv_vector_common.td @@ -604,10 +604,10 @@ class RVVConvToWidenUnsignedBuiltin<string overloaded_name> : RVVConvBuiltin<"Uw", "Uwv", "xf", overloaded_name>; class RVVConvToNarrowingSignedBuiltin<string overloaded_name> - : RVVConvBuiltin<"Iv", "IvFw", "csi", overloaded_name>; + : RVVConvBuiltin<"Iv", "IvFw", "si", overloaded_name>; class RVVConvToNarrowingUnsignedBuiltin<string overloaded_name> - : RVVConvBuiltin<"Uv", "UvFw", "csi", overloaded_name>; + : RVVConvBuiltin<"Uv", "UvFw", "si", overloaded_name>; let HasMaskedOffOperand = true in { multiclass RVVSignedReductionBuiltin { diff --git a/clang/include/clang/Support/RISCVVIntrinsicUtils.h b/clang/include/clang/Support/RISCVVIntrinsicUtils.h index b4ff61784126e..9a6a2092eb996 100644 --- a/clang/include/clang/Support/RISCVVIntrinsicUtils.h +++ b/clang/include/clang/Support/RISCVVIntrinsicUtils.h @@ -502,7 +502,8 @@ enum RVVRequire : uint32_t { RVV_REQ_Zvksh = 1 << 15, RVV_REQ_Zvfbfwma = 1 << 16, RVV_REQ_Zvfbfmin = 1 << 17, - RVV_REQ_Experimental = 1 << 18, + RVV_REQ_Zvfh = 1 << 18, + RVV_REQ_Experimental = 1 << 19, LLVM_MARK_AS_BITMASK_ENUM(RVV_REQ_Experimental) }; diff --git a/clang/lib/Sema/SemaRISCV.cpp b/clang/lib/Sema/SemaRISCV.cpp index f1c7c0516e671..abf8e4ac2f3e8 100644 --- a/clang/lib/Sema/SemaRISCV.cpp +++ b/clang/lib/Sema/SemaRISCV.cpp @@ -222,6 +222,7 @@ void RISCVIntrinsicManagerImpl::ConstructRVVIntrinsics( {"zvksh", RVV_REQ_Zvksh}, {"zvfbfwma", RVV_REQ_Zvfbfwma}, {"zvfbfmin", RVV_REQ_Zvfbfmin}, + {"zvfh", RVV_REQ_Zvfh}, {"experimental", RVV_REQ_Experimental}}; // Construction of RVVIntrinsicRecords need to sync with createRVVIntrinsics @@ -280,6 +281,11 @@ void RISCVIntrinsicManagerImpl::ConstructRVVIntrinsics( if ((BaseTypeI & Record.TypeRangeMask) != BaseTypeI) continue; + // TODO: Remove the check below and use RequiredFeatures in + // riscv_vector.td to check the intrinsics instead, the type check should + // be done in checkRVVTypeSupport. This check also not able to work on the + // intrinsics that have Float16 but the BaseType is not Float16 such as + // `vfcvt_f_x_v`. if (BaseType == BasicType::Float16) { if ((Record.RequiredExtensions & RVV_REQ_Zvfhmin) == RVV_REQ_Zvfhmin) { if (!TI.hasFeature("zvfhmin")) diff --git a/clang/utils/TableGen/RISCVVEmitter.cpp b/clang/utils/TableGen/RISCVVEmitter.cpp index 7f3cb70c97d09..ef7159fae9fd2 100644 --- a/clang/utils/TableGen/RISCVVEmitter.cpp +++ b/clang/utils/TableGen/RISCVVEmitter.cpp @@ -670,6 +670,7 @@ void RVVEmitter::createRVVIntrinsics( .Case("Zvksh", RVV_REQ_Zvksh) .Case("Zvfbfwma", RVV_REQ_Zvfbfwma) .Case("Zvfbfmin", RVV_REQ_Zvfbfmin) + .Case("Zvfh", RVV_REQ_Zvfh) .Case("Experimental", RVV_REQ_Experimental) .Default(RVV_REQ_None); assert(RequireExt != RVV_REQ_None && "Unrecognized required feature?"); `````````` </details> https://github.com/llvm/llvm-project/pull/101811 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
