================ @@ -0,0 +1,33 @@ +//===-- X86InstrAVX10.td - AVX10 Instruction Set -----------*- tablegen -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// This file describes the X86 AVX10 instruction set, defining the +// instructions, and properties of the instructions which are needed for code +// generation, machine code emission, and analysis. +// +//===----------------------------------------------------------------------===// + +// VMPSADBW +defm VMPSADBW : avx512_common_3Op_rm_imm8<0x42, X86Vmpsadbw, "vmpsadbw", SchedWritePSADBW, + avx512vl_i16_info, avx512vl_i8_info, + HasAVX10_2>, + XS, EVEX_CD8<32, CD8VF>; + +// YMM Rounding +multiclass avx256_fp_binop_p_round<bits<8> opc, string OpcodeStr, SDNode OpNodeRnd, ---------------- FreddyLeaf wrote:
I c. Agree. https://github.com/llvm/llvm-project/pull/101452 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
