https://github.com/azhan92 updated
https://github.com/llvm/llvm-project/pull/99550
>From a2cf264bc8b08364544407650c630c11a475fcab Mon Sep 17 00:00:00 2001
From: Alison Zhang <alisonzh...@ibm.com>
Date: Thu, 18 Jul 2024 14:32:30 -0400
Subject: [PATCH 1/2] support P11 with builtin_cpu_is
---
clang/test/CodeGen/aix-builtin-cpu-is.c | 4 ++++
llvm/include/llvm/TargetParser/PPCTargetParser.def | 3 +++
2 files changed, 7 insertions(+)
diff --git a/clang/test/CodeGen/aix-builtin-cpu-is.c
b/clang/test/CodeGen/aix-builtin-cpu-is.c
index e17cf7353511a..04644dd7020e0 100644
--- a/clang/test/CodeGen/aix-builtin-cpu-is.c
+++ b/clang/test/CodeGen/aix-builtin-cpu-is.c
@@ -50,6 +50,10 @@
// RUN: %clang_cc1 -triple powerpc-ibm-aix7.2.0.0 -emit-llvm -o - %t.c |
FileCheck %s -DVALUE=262144 \
// RUN: --check-prefix=CHECKOP
+// RUN: echo "int main() { return __builtin_cpu_is(\"power11\");}" > %t.c
+// RUN: %clang_cc1 -triple powerpc-ibm-aix7.2.0.0 -emit-llvm -o - %t.c |
FileCheck %s -DVALUE=524288 \
+// RUN: --check-prefix=CHECKOP
+
// CHECK: define i32 @main() #0 {
// CHECK-NEXT: entry:
// CHECK-NEXT: %retval = alloca i32, align 4
diff --git a/llvm/include/llvm/TargetParser/PPCTargetParser.def
b/llvm/include/llvm/TargetParser/PPCTargetParser.def
index 44e97d56a059c..df956a68d75d6 100644
--- a/llvm/include/llvm/TargetParser/PPCTargetParser.def
+++ b/llvm/include/llvm/TargetParser/PPCTargetParser.def
@@ -40,6 +40,7 @@
#undef AIX_PPC8_VALUE
#undef AIX_PPC9_VALUE
#undef AIX_PPC10_VALUE
+#undef AIX_PPC11_VALUE
#else
#ifndef PPC_LNX_FEATURE
#define PPC_LNX_FEATURE(NAME, DESC, ENUMNAME, ENUMVAL, HWCAPN)
@@ -84,6 +85,7 @@
#define AIX_PPC8_VALUE 0x00010000
#define AIX_PPC9_VALUE 0x00020000
#define AIX_PPC10_VALUE 0x00040000
+#define AIX_PPC11_VALUE 0x00080000
// __builtin_cpu_is() and __builtin_cpu_supports() are supported only on
Power7 and up on AIX.
// PPC_CPU(Name, Linux_SUPPORT_METHOD, LinuxID, AIX_SUPPORT_METHOD, AIXID)
@@ -103,6 +105,7 @@ PPC_CPU("ppc476",SYS_CALL,44,BUILTIN_PPC_FALSE,0)
PPC_CPU("power8",SYS_CALL,45,USE_SYS_CONF,AIX_PPC8_VALUE)
PPC_CPU("power9",SYS_CALL,46,USE_SYS_CONF,AIX_PPC9_VALUE)
PPC_CPU("power10",SYS_CALL,47,USE_SYS_CONF,AIX_PPC10_VALUE)
+PPC_CPU("power11",SYS_CALL,48,USE_SYS_CONF,AIX_PPC11_VALUE)
#undef PPC_CPU
// PPC features on Linux:
>From 56c12c533a62a58e64a7f6fcaaa36f91dbd0039f Mon Sep 17 00:00:00 2001
From: Alison Zhang <alisonzh...@ibm.com>
Date: Mon, 22 Jul 2024 15:49:36 -0500
Subject: [PATCH 2/2] Update lit tests for linux
---
clang/test/CodeGen/builtin-cpu-supports.c | 72 +++++++++++++++++++----
1 file changed, 62 insertions(+), 10 deletions(-)
diff --git a/clang/test/CodeGen/builtin-cpu-supports.c
b/clang/test/CodeGen/builtin-cpu-supports.c
index 88eb7b0fa786e..f960040ab094b 100644
--- a/clang/test/CodeGen/builtin-cpu-supports.c
+++ b/clang/test/CodeGen/builtin-cpu-supports.c
@@ -129,25 +129,69 @@ int v4() { return __builtin_cpu_supports("x86-64-v4"); }
// CHECK-PPC: if.else3:
// CHECK-PPC-NEXT: [[CPU_IS:%.*]] = call i32 @llvm.ppc.fixed.addr.ld(i32 3)
// CHECK-PPC-NEXT: [[TMP6:%.*]] = icmp eq i32 [[CPU_IS]], 39
-// CHECK-PPC-NEXT: br i1 [[TMP6]], label [[IF_THEN4:%.*]], label
[[IF_END:%.*]]
+// CHECK-PPC-NEXT: br i1 [[TMP6]], label [[IF_THEN4:%.*]], label
[[IF_ELSE5:%.*]]
// CHECK-PPC: if.then4:
// CHECK-PPC-NEXT: [[TMP7:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK-PPC-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK-PPC-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP7]], [[TMP8]]
// CHECK-PPC-NEXT: store i32 [[ADD]], ptr [[RETVAL]], align 4
// CHECK-PPC-NEXT: br label [[RETURN]]
+// CHECK-PPC: if.else5:
+// CHECK-PPC-NEXT: [[CPU_IS6:%.*]] = call i32 @llvm.ppc.fixed.addr.ld(i32 3)
+// CHECK-PPC-NEXT: [[TMP9:%.*]] = icmp eq i32 [[CPU_IS6]], 45
+// CHECK-PPC-NEXT: br i1 [[TMP9]], label [[IF_THEN7:%.*]], label
[[IF_ELSE9:%.*]]
+// CHECK-PPC: if.then7:
+// CHECK-PPC-NEXT: [[TMP10:%.*]] = load i32, ptr [[A_ADDR]], align 4
+// CHECK-PPC-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP10]], 3
+// CHECK-PPC-NEXT: store i32 [[ADD8]], ptr [[RETVAL]], align 4
+// CHECK-PPC-NEXT: br label [[RETURN]]
+// CHECK-PPC: if.else9:
+// CHECK-PPC-NEXT: [[CPU_IS10:%.*]] = call i32 @llvm.ppc.fixed.addr.ld(i32
3)
+// CHECK-PPC-NEXT: [[TMP11:%.*]] = icmp eq i32 [[CPU_IS10]], 46
+// CHECK-PPC-NEXT: br i1 [[TMP11]], label [[IF_THEN11:%.*]], label
[[IF_ELSE13:%.*]]
+// CHECK-PPC: if.then11:
+// CHECK-PPC-NEXT: [[TMP12:%.*]] = load i32, ptr [[A_ADDR]], align 4
+// CHECK-PPC-NEXT: [[SUB12:%.*]] = sub nsw i32 [[TMP12]], 3
+// CHECK-PPC-NEXT: store i32 [[SUB12]], ptr [[RETVAL]], align 4
+// CHECK-PPC-NEXT: br label [[RETURN]]
+// CHECK-PPC: if.else13:
+// CHECK-PPC-NEXT: [[CPU_IS14:%.*]] = call i32 @llvm.ppc.fixed.addr.ld(i32
3)
+// CHECK-PPC-NEXT: [[TMP13:%.*]] = icmp eq i32 [[CPU_IS14]], 47
+// CHECK-PPC-NEXT: br i1 [[TMP13]], label [[IF_THEN15:%.*]], label
[[IF_ELSE17:%.*]]
+// CHECK-PPC: if.then15:
+// CHECK-PPC-NEXT: [[TMP14:%.*]] = load i32, ptr [[A_ADDR]], align 4
+// CHECK-PPC-NEXT: [[ADD16:%.*]] = add nsw i32 [[TMP14]], 7
+// CHECK-PPC-NEXT: store i32 [[ADD16]], ptr [[RETVAL]], align 4
+// CHECK-PPC-NEXT: br label [[RETURN]]
+// CHECK-PPC: if.else17:
+// CHECK-PPC-NEXT: [[CPU_IS18:%.*]] = call i32 @llvm.ppc.fixed.addr.ld(i32
3)
+// CHECK-PPC-NEXT: [[TMP15:%.*]] = icmp eq i32 [[CPU_IS18]], 48
+// CHECK-PPC-NEXT: br i1 [[TMP15]], label [[IF_THEN19:%.*]], label
[[IF_END:%.*]]
+// CHECK-PPC: if.then19:
+// CHECK-PPC-NEXT: [[TMP16:%.*]] = load i32, ptr [[A_ADDR]], align 4
+// CHECK-PPC-NEXT: [[SUB20:%.*]] = sub nsw i32 [[TMP16]], 7
+// CHECK-PPC-NEXT: store i32 [[SUB20]], ptr [[RETVAL]], align 4
+// CHECK-PPC-NEXT: br label [[RETURN]]
// CHECK-PPC: if.end:
-// CHECK-PPC-NEXT: br label [[IF_END5:%.*]]
-// CHECK-PPC: if.end5:
-// CHECK-PPC-NEXT: br label [[IF_END6:%.*]]
-// CHECK-PPC: if.end6:
-// CHECK-PPC-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_ADDR]], align 4
-// CHECK-PPC-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP9]], 5
-// CHECK-PPC-NEXT: store i32 [[ADD7]], ptr [[RETVAL]], align 4
+// CHECK-PPC-NEXT: br label [[IF_END21:%.*]]
+// CHECK-PPC: if.end21:
+// CHECK-PPC-NEXT: br label [[IF_END22:%.*]]
+// CHECK-PPC: if.end22:
+// CHECK-PPC-NEXT: br label [[IF_END23:%.*]]
+// CHECK-PPC: if.end23:
+// CHECK-PPC-NEXT: br label [[IF_END24:%.*]]
+// CHECK-PPC: if.end24:
+// CHECK-PPC-NEXT: br label [[IF_END25:%.*]]
+// CHECK-PPC: if.end25:
+// CHECK-PPC-NEXT: br label [[IF_END26:%.*]]
+// CHECK-PPC: if.end26:
+// CHECK-PPC-NEXT: [[TMP17:%.*]] = load i32, ptr [[A_ADDR]], align 4
+// CHECK-PPC-NEXT: [[ADD27:%.*]] = add nsw i32 [[TMP17]], 5
+// CHECK-PPC-NEXT: store i32 [[ADD27]], ptr [[RETVAL]], align 4
// CHECK-PPC-NEXT: br label [[RETURN]]
// CHECK-PPC: return:
-// CHECK-PPC-NEXT: [[TMP10:%.*]] = load i32, ptr [[RETVAL]], align 4
-// CHECK-PPC-NEXT: ret i32 [[TMP10]]
+// CHECK-PPC-NEXT: [[TMP18:%.*]] = load i32, ptr [[RETVAL]], align 4
+// CHECK-PPC-NEXT: ret i32 [[TMP18]]
//
int test(int a) {
if (__builtin_cpu_supports("arch_3_00")) // HWCAP2
@@ -156,6 +200,14 @@ int test(int a) {
return a - 5;
else if (__builtin_cpu_is("power7")) // CPUID
return a + a;
+ else if (__builtin_cpu_is("power8"))
+ return a + 3;
+ else if (__builtin_cpu_is("power9"))
+ return a - 3;
+ else if (__builtin_cpu_is("power10"))
+ return a + 7;
+ else if (__builtin_cpu_is("power11"))
+ return a - 7;
return a + 5;
}
#endif
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