Author: James Y Knight Date: 2024-07-20T11:28:06-04:00 New Revision: 3c6ea7b7168fdb4d4396bcf67ea0d69495a558b8
URL: https://github.com/llvm/llvm-project/commit/3c6ea7b7168fdb4d4396bcf67ea0d69495a558b8 DIFF: https://github.com/llvm/llvm-project/commit/3c6ea7b7168fdb4d4396bcf67ea0d69495a558b8.diff LOG: Remove 3DNow! from X86TargetParser. (#99352) This addresses the spurious inclusion of (now unsupported) target features '-3dnow' and '-3dnowa' when disabling mmx (when then caused log output from `clang -mno-mmx`). It should've been part of PR #96246, but was missed. Also tweaks the warning in prfchwintrin.h to not recommend the deprecated mm3dnow.h header. Added: Modified: clang/lib/Headers/prfchwintrin.h clang/test/CodeGen/attr-target-x86.c compiler-rt/lib/builtins/cpu_model/x86.c llvm/include/llvm/TargetParser/X86TargetParser.def llvm/lib/TargetParser/X86TargetParser.cpp Removed: ################################################################################ diff --git a/clang/lib/Headers/prfchwintrin.h b/clang/lib/Headers/prfchwintrin.h index 8a13784543c5f..eaea5f3cf8feb 100644 --- a/clang/lib/Headers/prfchwintrin.h +++ b/clang/lib/Headers/prfchwintrin.h @@ -8,7 +8,7 @@ */ #if !defined(__X86INTRIN_H) && !defined(_MM3DNOW_H_INCLUDED) -#error "Never use <prfchwintrin.h> directly; include <x86intrin.h> or <mm3dnow.h> instead." +#error "Never use <prfchwintrin.h> directly; include <x86intrin.h> instead." #endif #ifndef __PRFCHWINTRIN_H diff --git a/clang/test/CodeGen/attr-target-x86.c b/clang/test/CodeGen/attr-target-x86.c index 3c2b511157f99..b1ae6678531b9 100644 --- a/clang/test/CodeGen/attr-target-x86.c +++ b/clang/test/CodeGen/attr-target-x86.c @@ -64,7 +64,7 @@ void __attribute__((target("avx10.1-512"))) avx10_1_512(void) {} // CHECK: #4 = {{.*}}"target-cpu"="i686" "target-features"="+cmov,+cx8,+x87,-avx,-avx10.1-256,-avx10.1-512,-avx2,-avx512bf16,-avx512bitalg,-avx512bw,-avx512cd,-avx512dq,-avx512f,-avx512fp16,-avx512ifma,-avx512vbmi,-avx512vbmi2,-avx512vl,-avx512vnni,-avx512vp2intersect,-avx512vpopcntdq,-avxifma,-avxneconvert,-avxvnni,-avxvnniint16,-avxvnniint8,-f16c,-fma,-fma4,-sha512,-sm3,-sm4,-sse4.1,-sse4.2,-vaes,-vpclmulqdq,-xop" "tune-cpu"="i686" // CHECK: #5 = {{.*}}"target-cpu"="ivybridge" "target-features"="+avx,+cmov,+crc32,+cx16,+cx8,+f16c,+fsgsbase,+fxsr,+mmx,+pclmul,+popcnt,+rdrnd,+sahf,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+x87,+xsave,+xsaveopt,-aes,-avx10.1-256,-avx10.1-512,-vaes" // CHECK-NOT: tune-cpu -// CHECK: #6 = {{.*}}"target-cpu"="i686" "target-features"="+cmov,+cx8,+x87,-3dnow,-3dnowa,-mmx" +// CHECK: #6 = {{.*}}"target-cpu"="i686" "target-features"="+cmov,+cx8,+x87,-mmx" // CHECK: #7 = {{.*}}"target-cpu"="lakemont" "target-features"="+cx8,+mmx" // CHECK-NOT: tune-cpu // CHECK: #8 = {{.*}}"target-cpu"="i686" "target-features"="+cmov,+cx8,+x87" "tune-cpu"="sandybridge" diff --git a/compiler-rt/lib/builtins/cpu_model/x86.c b/compiler-rt/lib/builtins/cpu_model/x86.c index ab2b685e67ef8..867ed97e57bf2 100644 --- a/compiler-rt/lib/builtins/cpu_model/x86.c +++ b/compiler-rt/lib/builtins/cpu_model/x86.c @@ -141,7 +141,7 @@ enum ProcessorFeatures { FEATURE_AVX512VP2INTERSECT, // FIXME: Below Features has some missings comparing to gcc, it's because gcc // has some not one-to-one mapped in llvm. - FEATURE_3DNOW, + // FEATURE_3DNOW, // FEATURE_3DNOWP, FEATURE_ADX = 40, // FEATURE_ABM, diff --git a/llvm/include/llvm/TargetParser/X86TargetParser.def b/llvm/include/llvm/TargetParser/X86TargetParser.def index 0e4ad873e3639..92798cbe4b4c1 100644 --- a/llvm/include/llvm/TargetParser/X86TargetParser.def +++ b/llvm/include/llvm/TargetParser/X86TargetParser.def @@ -175,8 +175,12 @@ X86_FEATURE_COMPAT(AVX512BF16, "avx512bf16", 34) X86_FEATURE_COMPAT(AVX512VP2INTERSECT, "avx512vp2intersect", 35) // Below Features has some missings comparing to gcc, it's because gcc has some // not one-to-one mapped in llvm. -X86_FEATURE_COMPAT(3DNOW, "3dnow", 0) -X86_FEATURE (3DNOWA, "3dnowa") + +// FIXME: dummy features were added to keep the numeric values of later features +// stable. Since the values need to be ABI stable, they should be changed to +// have explicitly assigned values, and then these dummy features removed. +X86_FEATURE (DUMMYFEATURE1, "__dummyfeature1") +X86_FEATURE (DUMMYFEATURE2, "__dummyfeature2") X86_FEATURE_COMPAT(ADX, "adx", 0) X86_FEATURE (64BIT, "64bit") X86_FEATURE_COMPAT(CLDEMOTE, "cldemote", 0) diff --git a/llvm/lib/TargetParser/X86TargetParser.cpp b/llvm/lib/TargetParser/X86TargetParser.cpp index 141ecb936b708..dcf9130052ac1 100644 --- a/llvm/lib/TargetParser/X86TargetParser.cpp +++ b/llvm/lib/TargetParser/X86TargetParser.cpp @@ -171,14 +171,14 @@ constexpr FeatureBitset FeaturesClearwaterforest = // Geode Processor. constexpr FeatureBitset FeaturesGeode = - FeatureX87 | FeatureCMPXCHG8B | FeatureMMX | Feature3DNOW | Feature3DNOWA; + FeatureX87 | FeatureCMPXCHG8B | FeatureMMX | FeaturePRFCHW; // K6 processor. constexpr FeatureBitset FeaturesK6 = FeatureX87 | FeatureCMPXCHG8B | FeatureMMX; // K7 and K8 architecture processors. constexpr FeatureBitset FeaturesAthlon = - FeatureX87 | FeatureCMPXCHG8B | FeatureMMX | Feature3DNOW | Feature3DNOWA; + FeatureX87 | FeatureCMPXCHG8B | FeatureMMX | FeaturePRFCHW; constexpr FeatureBitset FeaturesAthlonXP = FeaturesAthlon | FeatureFXSR | FeatureSSE; constexpr FeatureBitset FeaturesK8 = @@ -256,8 +256,8 @@ constexpr ProcInfo Processors[] = { // i486-generation processors. { {"i486"}, CK_i486, ~0U, FeatureX87, '\0', false }, { {"winchip-c6"}, CK_WinChipC6, ~0U, FeaturesPentiumMMX, '\0', false }, - { {"winchip2"}, CK_WinChip2, ~0U, FeaturesPentiumMMX | Feature3DNOW, '\0', false }, - { {"c3"}, CK_C3, ~0U, FeaturesPentiumMMX | Feature3DNOW, '\0', false }, + { {"winchip2"}, CK_WinChip2, ~0U, FeaturesPentiumMMX | FeaturePRFCHW, '\0', false }, + { {"c3"}, CK_C3, ~0U, FeaturesPentiumMMX | FeaturePRFCHW, '\0', false }, // i586-generation processors, P5 microarchitecture based. { {"i586"}, CK_i586, ~0U, FeatureX87 | FeatureCMPXCHG8B, '\0', false }, { {"pentium"}, CK_Pentium, ~0U, FeatureX87 | FeatureCMPXCHG8B, 'B', false }, @@ -386,8 +386,8 @@ constexpr ProcInfo Processors[] = { { {"lakemont"}, CK_Lakemont, ~0U, FeatureCMPXCHG8B, '\0', false }, // K6 architecture processors. { {"k6"}, CK_K6, ~0U, FeaturesK6, '\0', false }, - { {"k6-2"}, CK_K6_2, ~0U, FeaturesK6 | Feature3DNOW, '\0', false }, - { {"k6-3"}, CK_K6_3, ~0U, FeaturesK6 | Feature3DNOW, '\0', false }, + { {"k6-2"}, CK_K6_2, ~0U, FeaturesK6 | FeaturePRFCHW, '\0', false }, + { {"k6-3"}, CK_K6_3, ~0U, FeaturesK6 | FeaturePRFCHW, '\0', false }, // K7 architecture processors. { {"athlon"}, CK_Athlon, ~0U, FeaturesAthlon, '\0', false }, { {"athlon-tbird"}, CK_Athlon, ~0U, FeaturesAthlon, '\0', false }, @@ -493,6 +493,7 @@ constexpr FeatureBitset ImpliedFeaturesFXSR = {}; constexpr FeatureBitset ImpliedFeaturesINVPCID = {}; constexpr FeatureBitset ImpliedFeaturesLWP = {}; constexpr FeatureBitset ImpliedFeaturesLZCNT = {}; +constexpr FeatureBitset ImpliedFeaturesMMX = {}; constexpr FeatureBitset ImpliedFeaturesMWAITX = {}; constexpr FeatureBitset ImpliedFeaturesMOVBE = {}; constexpr FeatureBitset ImpliedFeaturesMOVDIR64B = {}; @@ -520,6 +521,8 @@ constexpr FeatureBitset ImpliedFeaturesWBNOINVD = {}; constexpr FeatureBitset ImpliedFeaturesVZEROUPPER = {}; constexpr FeatureBitset ImpliedFeaturesX87 = {}; constexpr FeatureBitset ImpliedFeaturesXSAVE = {}; +constexpr FeatureBitset ImpliedFeaturesDUMMYFEATURE1 = {}; +constexpr FeatureBitset ImpliedFeaturesDUMMYFEATURE2 = {}; // Not really CPU features, but need to be in the table because clang uses // target features to communicate them to the backend. @@ -534,11 +537,6 @@ constexpr FeatureBitset ImpliedFeaturesXSAVEC = FeatureXSAVE; constexpr FeatureBitset ImpliedFeaturesXSAVEOPT = FeatureXSAVE; constexpr FeatureBitset ImpliedFeaturesXSAVES = FeatureXSAVE; -// MMX->3DNOW->3DNOWA chain. -constexpr FeatureBitset ImpliedFeaturesMMX = {}; -constexpr FeatureBitset ImpliedFeatures3DNOW = FeatureMMX; -constexpr FeatureBitset ImpliedFeatures3DNOWA = Feature3DNOW; - // SSE/AVX/AVX512F chain. constexpr FeatureBitset ImpliedFeaturesSSE = {}; constexpr FeatureBitset ImpliedFeaturesSSE2 = FeatureSSE; _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
