github-actions[bot] wrote:
<!--LLVM CODE FORMAT COMMENT: {clang-format}-->
:warning: C/C++ code formatter, clang-format found issues in your code.
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<details>
<summary>
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``````````bash
git-clang-format --diff 3eb666e292baf87c969be733de858b0cb7ead13f
e55375b12aa1da16d27d8d888d707669041303f6 --extensions c,h,cpp --
clang/lib/Basic/Targets/PPC.cpp clang/lib/Basic/Targets/PPC.h
clang/lib/Driver/ToolChains/Arch/PPC.cpp
clang/test/Misc/target-invalid-cpu-note.c clang/test/Preprocessor/init-ppc64.c
llvm/lib/Target/PowerPC/PPCISelLowering.cpp
llvm/lib/Target/PowerPC/PPCInstrInfo.cpp llvm/lib/Target/PowerPC/PPCInstrInfo.h
llvm/lib/Target/PowerPC/PPCSubtarget.h
llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
llvm/lib/TargetParser/Host.cpp llvm/unittests/TargetParser/Host.cpp
``````````
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<details>
<summary>
View the diff from clang-format here.
</summary>
``````````diff
diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
index c8d8f97231..9f7755a30c 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
+++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
@@ -3486,9 +3486,10 @@ unsigned PPCInstrInfo::getSpillTarget() const {
// registers. MMA implies paired vectors, so we can just check that.
bool IsP10Variant = Subtarget.isISA3_1() || Subtarget.pairedVectorMemops();
// P11 uses the P10 target.
- return Subtarget.isISAFuture() ? 4 : IsP10Variant ?
- 2 : Subtarget.hasP9Vector() ?
- 1 : 0;
+ return Subtarget.isISAFuture() ? 4
+ : IsP10Variant ? 2
+ : Subtarget.hasP9Vector() ? 1
+ : 0;
}
ArrayRef<unsigned> PPCInstrInfo::getStoreOpcodesForSpillArray() const {
diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.h
b/llvm/lib/Target/PowerPC/PPCInstrInfo.h
index ea34b45925..b7105b1cdb 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrInfo.h
+++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.h
@@ -125,12 +125,23 @@ enum PPCMachineCombinerPattern : unsigned {
}
#define Pwr11LoadOpcodes
\
- {
\
- PPC::LWZ, PPC::LD, PPC::LFD, PPC::LFS, PPC::RESTORE_CR,
\
- PPC::RESTORE_CRBIT, PPC::LVX, PPC::LXV, PPC::DFLOADf64,
\
- PPC::DFLOADf32, PPC::SPILLTOVSR_LD, PPC::LXVP, PPC::RESTORE_ACC,
\
- PPC::RESTORE_UACC, NoInstr, NoInstr, PPC::RESTORE_QUADWORD
\
- }
+ {PPC::LWZ,
\
+ PPC::LD,
\
+ PPC::LFD,
\
+ PPC::LFS,
\
+ PPC::RESTORE_CR,
\
+ PPC::RESTORE_CRBIT,
\
+ PPC::LVX,
\
+ PPC::LXV,
\
+ PPC::DFLOADf64,
\
+ PPC::DFLOADf32,
\
+ PPC::SPILLTOVSR_LD,
\
+ PPC::LXVP,
\
+ PPC::RESTORE_ACC,
\
+ PPC::RESTORE_UACC,
\
+ NoInstr,
\
+ NoInstr,
\
+ PPC::RESTORE_QUADWORD}
#define FutureLoadOpcodes
\
{
\
@@ -165,12 +176,12 @@ enum PPCMachineCombinerPattern : unsigned {
}
#define Pwr11StoreOpcodes
\
- {
\
- PPC::STW, PPC::STD, PPC::STFD, PPC::STFS, PPC::SPILL_CR, PPC::SPILL_CRBIT,
\
- PPC::STVX, PPC::STXV, PPC::DFSTOREf64, PPC::DFSTOREf32,
\
- PPC::SPILLTOVSR_ST, PPC::STXVP, PPC::SPILL_ACC, PPC::SPILL_UACC,
\
- NoInstr, NoInstr, PPC::SPILL_QUADWORD
\
- }
+ {PPC::STW, PPC::STD, PPC::STFD,
\
+ PPC::STFS, PPC::SPILL_CR, PPC::SPILL_CRBIT,
\
+ PPC::STVX, PPC::STXV, PPC::DFSTOREf64,
\
+ PPC::DFSTOREf32, PPC::SPILLTOVSR_ST, PPC::STXVP,
\
+ PPC::SPILL_ACC, PPC::SPILL_UACC, NoInstr,
\
+ NoInstr, PPC::SPILL_QUADWORD}
#define FutureStoreOpcodes
\
{
\
@@ -182,9 +193,11 @@ enum PPCMachineCombinerPattern : unsigned {
// Initialize arrays for load and store spill opcodes on supported subtargets.
#define StoreOpcodesForSpill
\
- { Pwr8StoreOpcodes, Pwr9StoreOpcodes, Pwr10StoreOpcodes, Pwr11StoreOpcodes,
FutureStoreOpcodes }
+ {Pwr8StoreOpcodes, Pwr9StoreOpcodes, Pwr10StoreOpcodes, Pwr11StoreOpcodes,
\
+ FutureStoreOpcodes}
#define LoadOpcodesForSpill
\
- { Pwr8LoadOpcodes, Pwr9LoadOpcodes, Pwr10LoadOpcodes, Pwr11LoadOpcodes,
FutureLoadOpcodes }
+ {Pwr8LoadOpcodes, Pwr9LoadOpcodes, Pwr10LoadOpcodes, Pwr11LoadOpcodes,
\
+ FutureLoadOpcodes}
class PPCSubtarget;
class PPCInstrInfo : public PPCGenInstrInfo {
diff --git a/llvm/unittests/TargetParser/Host.cpp
b/llvm/unittests/TargetParser/Host.cpp
index c85be8476c..f8dd1d3a60 100644
--- a/llvm/unittests/TargetParser/Host.cpp
+++ b/llvm/unittests/TargetParser/Host.cpp
@@ -536,7 +536,7 @@ TEST(HostTest, AIXHostCPUDetect) {
.Case("POWER 8\n", "pwr8")
.Case("POWER 9\n", "pwr9")
.Case("POWER 10\n", "pwr10")
- .Case("POWER 11\n", "pwr11")
+ .Case("POWER 11\n", "pwr11")
.Default("unknown");
StringRef HostCPU = sys::getHostCPUName();
``````````
</details>
https://github.com/llvm/llvm-project/pull/99511
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