dtcxzyw wrote:
```
dtcxzyw@bananapif3:/data/llvm-build$ bin/clang -mcpu=native
--print-enabled-extensions
clang version 19.0.0git
Target: riscv64-unknown-linux-gnu
Thread model: posix
InstalledDir: /data/llvm-build/bin
Build config: +assertions
Extensions enabled for the given RISC-V target
Name Version Description
i 2.1 'I' (Base Integer Instruction Set)
m 2.0 'M' (Integer Multiplication and Division)
a 2.1 'A' (Atomic Instructions)
f 2.2 'F' (Single-Precision Floating-Point)
d 2.2 'D' (Double-Precision Floating-Point)
c 2.0 'C' (Compressed Instructions)
v 1.0 'V' (Vector Extension for Application
Processors)
zicond 1.0 'Zicond' (Integer Conditional Operations)
zicsr 2.0 'zicsr' (CSRs)
zihintpause 2.0 'Zihintpause' (Pause Hint)
zmmul 1.0 'Zmmul' (Integer Multiplication)
zba 1.0 'Zba' (Address Generation Instructions)
zbb 1.0 'Zbb' (Basic Bit-Manipulation)
zbc 1.0 'Zbc' (Carry-Less Multiplication)
zbs 1.0 'Zbs' (Single-Bit Instructions)
zve32f 1.0 'Zve32f' (Vector Extensions for Embedded
Processors with maximal 32 EEW and F extension)
zve32x 1.0 'Zve32x' (Vector Extensions for Embedded
Processors with maximal 32 EEW)
zve64d 1.0 'Zve64d' (Vector Extensions for Embedded
Processors with maximal 64 EEW, F and D extension)
zve64f 1.0 'Zve64f' (Vector Extensions for Embedded
Processors with maximal 64 EEW and F extension)
zve64x 1.0 'Zve64x' (Vector Extensions for Embedded
Processors with maximal 64 EEW)
zvl128b 1.0 'Zvl' (Minimum Vector Length) 128
zvl32b 1.0 'Zvl' (Minimum Vector Length) 32
zvl64b 1.0 'Zvl' (Minimum Vector Length) 64
Experimental extensions
ISA String:
rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_v1p0_zicond1p0_zicsr2p0_zihintpause2p0_zmmul1p0_zba1p0_zbb1p0_zbc1p0_zbs1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0
dtcxzyw@bananapif3:/data/llvm-build$
```
https://github.com/llvm/llvm-project/pull/94352
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