llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT--> @llvm/pr-subscribers-clang Author: James Y Knight (jyknight) <details> <summary>Changes</summary> The SelectionDAG asm-lowering code can already handle conversion of other vector types to MMX if needed. --- Full diff: https://github.com/llvm/llvm-project/pull/98273.diff 5 Files Affected: - (modified) clang/lib/CodeGen/Targets/X86.cpp (-13) - (modified) clang/test/CodeGen/X86/mmx-inline-asm.c (+1-1) - (modified) clang/test/CodeGen/asm-inout.c (+3-3) - (modified) llvm/lib/Target/X86/X86ISelLowering.cpp (+3-3) - (added) llvm/test/CodeGen/X86/mmx-inlineasm.ll (+20) ``````````diff diff --git a/clang/lib/CodeGen/Targets/X86.cpp b/clang/lib/CodeGen/Targets/X86.cpp index 3146caba1c615..7fb9a4c070873 100644 --- a/clang/lib/CodeGen/Targets/X86.cpp +++ b/clang/lib/CodeGen/Targets/X86.cpp @@ -27,19 +27,6 @@ bool IsX86_MMXType(llvm::Type *IRType) { static llvm::Type* X86AdjustInlineAsmType(CodeGen::CodeGenFunction &CGF, StringRef Constraint, llvm::Type* Ty) { - bool IsMMXCons = llvm::StringSwitch<bool>(Constraint) - .Cases("y", "&y", "^Ym", true) - .Default(false); - if (IsMMXCons && Ty->isVectorTy()) { - if (cast<llvm::VectorType>(Ty)->getPrimitiveSizeInBits().getFixedValue() != - 64) { - // Invalid MMX constraint - return nullptr; - } - - return llvm::Type::getX86_MMXTy(CGF.getLLVMContext()); - } - if (Constraint == "k") { llvm::Type *Int1Ty = llvm::Type::getInt1Ty(CGF.getLLVMContext()); return llvm::FixedVectorType::get(Int1Ty, Ty->getScalarSizeInBits()); diff --git a/clang/test/CodeGen/X86/mmx-inline-asm.c b/clang/test/CodeGen/X86/mmx-inline-asm.c index 19c24a3a91e14..a0702c7f780d1 100644 --- a/clang/test/CodeGen/X86/mmx-inline-asm.c +++ b/clang/test/CodeGen/X86/mmx-inline-asm.c @@ -1,7 +1,7 @@ // RUN: %clang_cc1 -emit-llvm -triple i386 -target-feature +mmx %s -o - | FileCheck %s #include <mmintrin.h> -// CHECK: { x86_mmx, x86_mmx, x86_mmx, x86_mmx, x86_mmx, x86_mmx, x86_mmx } +// CHECK: { <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64> } void foo(long long fill) { __m64 vfill = _mm_cvtsi64_m64(fill); diff --git a/clang/test/CodeGen/asm-inout.c b/clang/test/CodeGen/asm-inout.c index 1383a421efbc2..6d40451b778d9 100644 --- a/clang/test/CodeGen/asm-inout.c +++ b/clang/test/CodeGen/asm-inout.c @@ -38,11 +38,11 @@ int test4(volatile int *addr) { return (int)oldval; } -// This should have both inputs be of type x86_mmx. +// This should have both inputs be of type <1 x i64>. // CHECK: @test5 typedef long long __m64 __attribute__((__vector_size__(8))); __m64 test5(__m64 __A, __m64 __B) { - // CHECK: call x86_mmx asm "pmulhuw $1, $0\0A\09", "=y,y,0,~{dirflag},~{fpsr},~{flags}"(x86_mmx %{{.*}}, x86_mmx %{{.*}}) + // CHECK: call <1 x i64> asm "pmulhuw $1, $0\0A\09", "=y,y,0,~{dirflag},~{fpsr},~{flags}"(<1 x i64> %{{.*}}, <1 x i64> %{{.*}}) asm ("pmulhuw %1, %0\n\t" : "+y" (__A) : "y" (__B)); return __A; } @@ -51,7 +51,7 @@ __m64 test5(__m64 __A, __m64 __B) { int test6(void) { typedef unsigned char __attribute__((vector_size(8))) _m64u8; _m64u8 __attribute__((aligned(16))) Mu8_0, __attribute__((aligned(16))) Mu8_1; - // CHECK: call x86_mmx asm "nop", "=y,0,~{dirflag},~{fpsr},~{flags}"(x86_mmx %1) + // CHECK: call <8 x i8> asm "nop", "=y,0,~{dirflag},~{fpsr},~{flags}"(<8 x i8> %0) asm ("nop" : "=y"(Mu8_1 ) : "0"(Mu8_0 )); return 0; } diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 50cacc3038b0c..d2e7074c59077 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -58150,7 +58150,7 @@ X86TargetLowering::getSingleConstraintMatchWeight( Wt = CW_SpecificReg; break; case 'y': - if (Ty->isX86_MMXTy() && Subtarget.hasMMX()) + if (Ty->getPrimitiveSizeInBits() == 64 && Subtarget.hasMMX()) Wt = CW_SpecificReg; break; case 'Y': @@ -58173,8 +58173,8 @@ X86TargetLowering::getSingleConstraintMatchWeight( return CW_Invalid; // Any MMX reg case 'm': - if (Ty->isX86_MMXTy() && Subtarget.hasMMX()) - return Wt; + if (Ty->getPrimitiveSizeInBits() == 64 && Subtarget.hasMMX()) + return CW_SpecificReg; return CW_Invalid; // Any SSE reg when ISA >= SSE2, same as 'x' case 'i': diff --git a/llvm/test/CodeGen/X86/mmx-inlineasm.ll b/llvm/test/CodeGen/X86/mmx-inlineasm.ll new file mode 100644 index 0000000000000..5a15600a4b312 --- /dev/null +++ b/llvm/test/CodeGen/X86/mmx-inlineasm.ll @@ -0,0 +1,20 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+mmx | FileCheck %s + +;; Verify that the mmx 'y' constraint works with arbitrary IR types. +define <2 x i32> @test_mmx_asm(<2 x i32> %a) nounwind { +; CHECK-LABEL: test_mmx_asm: +; CHECK: # %bb.0: +; CHECK-NEXT: movdq2q %xmm0, %mm0 +; CHECK-NEXT: #APP +; CHECK-NEXT: # %mm0 = %mm0 +; CHECK-NEXT: #NO_APP +; CHECK-NEXT: #APP +; CHECK-NEXT: # %mm0 = %mm0 +; CHECK-NEXT: #NO_APP +; CHECK-NEXT: movq2dq %mm0, %xmm0 +; CHECK-NEXT: retq + %1 = tail call i64 asm sideeffect "# $0 = $1", "=y,y"(<2 x i32> %a) + %2 = tail call <2 x i32> asm sideeffect "# $0 = $1", "=y,y"(i64 %1) + ret <2 x i32> %2 +} `````````` </details> https://github.com/llvm/llvm-project/pull/98273 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
