================
@@ -545,6 +545,25 @@ let TargetPrefix = "aarch64", IntrProperties = [IntrNoMem]
in {
def int_aarch64_neon_vcmla_rot270 : AdvSIMD_3VectorArg_Intrinsic;
}
+let TargetPrefix = "aarch64" in {
+def int_aarch64_neon_vluti2_lane : DefaultAttrsIntrinsic<[llvm_anyvector_ty],
----------------
CarolineConcatto wrote:
I am being picky, but wouldn't be better to have :
def int_aarch64_neon_vluti2_lane : DefaultAttrsIntrinsic<[llvm_anyvector_ty],
[llvm_anyvector_ty, llvm_v8i8_ty,
llvm_i32_ty], [IntrNoMem, ImmArg<ArgIndex<2>>]>;
def int_aarch64_neon_vluti2_laneq : DefaultAttrsIntrinsic<[llvm_anyvector_ty],
[llvm_anyvector_ty, llvm_v16i8_ty,
llvm_i32_ty], [IntrNoMem, ImmArg<ArgIndex<2>>]>;
It is just because I believe it is unusual to see the llvm.ir with 3 overloaded
types.
https://github.com/llvm/llvm-project/pull/96883
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