================
@@ -284,3 +284,48 @@ Example Usage
Base* basePtr = &obj;
basePtr->virtualFunction(); // Allowed since obj is constructed in
device code
}
+
+SPIR-V Support on HIPAMD ToolChain
+==================================
+
+The HIPAMD ToolChain supports targetting
+`AMDGCN Flavoured SPIR-V
<https://llvm.org/docs/SPIRVUsage.html#target-triples>`_.
+The support for SPIR-V in the ROCm and HIPAMD ToolChain is under active
+development.
+
+Compilation Process
+-------------------
+
+When compiling HIP programs with the intent of utilizing SPIR-V, the process
+diverges from the traditional compilation flow:
+
+Using ``--offload-arch=amdgcnspirv``
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+- **Target Triple**: The ``--offload-arch=amdgcnspirv`` flag instructs the
+ compiler to use the target triple ``spirv64-amd-amdhsa``. This approach does
+ generates generic AMDGCN SPIR-V which retains architecture specific elements
+ without hardcoding them, thus allowing for optimal target specific code to be
+ generated at run time, when the concrete target is known.
+
+- **LLVM IR Translation**: The program is compiled to LLVM Intermediate
+ Representation (IR), which is subsequently translated into SPIR-V. In the
+ future, this translation step will be replaced by direct SPIR-V emission via
+ the SPIR-V Back-end.
+
+- **Clang Offload Bundler**: The resulting SPIR-V is embedded in the Clang
+ offload bundler with the bundle ID ``hipv4-hip-spirv64-amd-amdhsa-generic``.
----------------
yxsamliu wrote:
should it be ``hipv4-spirv64-amd-amdhsa-generic`` ?
https://github.com/llvm/llvm-project/pull/96657
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