https://github.com/sstwcw created
https://github.com/llvm/llvm-project/pull/95703
I made a mistake when I tried to make the code handle the backtick character
like the hash character. The code did not recognize the delay control
structure. It caused net names in the declaration to be aligned to the type
name instead of the first net name.
new
```Verilog
wire logic #0 mynet, //
mynet1;
```
old
```Verilog
wire logic #0 mynet, //
mynet1;
```
>From 5982cfd24a59e165795ff8528901e31f80798074 Mon Sep 17 00:00:00 2001
From: sstwcw <su3e8a96kzl...@posteo.net>
Date: Sun, 16 Jun 2024 13:04:27 +0000
Subject: [PATCH] [clang-format] Handle Verilog delay control
I made a mistake when I tried to make the code handle the backtick
character like the hash character. The code did not recognize the delay
control structure. It caused net names in the declaration to be aligned
to the type name instead of the first net name.
new
```Verilog
wire logic #0 mynet, //
mynet1;
```
old
```Verilog
wire logic #0 mynet, //
mynet1;
```
---
clang/lib/Format/TokenAnnotator.cpp | 3 ++-
clang/unittests/Format/FormatTestVerilog.cpp | 9 +++++++++
2 files changed, 11 insertions(+), 1 deletion(-)
diff --git a/clang/lib/Format/TokenAnnotator.cpp
b/clang/lib/Format/TokenAnnotator.cpp
index 1fe3b61a5a81f..82c101a24a998 100644
--- a/clang/lib/Format/TokenAnnotator.cpp
+++ b/clang/lib/Format/TokenAnnotator.cpp
@@ -3410,7 +3410,8 @@ class ExpressionParser {
} else {
break;
}
- } else if (Tok->is(tok::hash)) {
+ } else if (Tok->is(Keywords.kw_verilogHash)) {
+ // Delay control.
if (Next->is(tok::l_paren))
Next = Next->MatchingParen;
if (Next)
diff --git a/clang/unittests/Format/FormatTestVerilog.cpp
b/clang/unittests/Format/FormatTestVerilog.cpp
index b5241a4e0d6ae..fbaf289fbc4d6 100644
--- a/clang/unittests/Format/FormatTestVerilog.cpp
+++ b/clang/unittests/Format/FormatTestVerilog.cpp
@@ -391,6 +391,15 @@ TEST_F(FormatTestVerilog, Declaration) {
verifyFormat("wire mynet, mynet1;");
verifyFormat("wire mynet, //\n"
" mynet1;");
+ verifyFormat("wire #0 mynet, mynet1;");
+ verifyFormat("wire logic #0 mynet, mynet1;");
+ verifyFormat("wire #(1, 2, 3) mynet, mynet1;");
+ verifyFormat("wire #0 mynet, //\n"
+ " mynet1;");
+ verifyFormat("wire logic #0 mynet, //\n"
+ " mynet1;");
+ verifyFormat("wire #(1, 2, 3) mynet, //\n"
+ " mynet1;");
verifyFormat("wire mynet = enable;");
verifyFormat("wire mynet = enable, mynet1;");
verifyFormat("wire mynet = enable, //\n"
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